經濟部智慧財產局員工消費合作社印製 579464 五、發明説明（ 發明領域： 本發明係有關於一種 有關於具有動態路經調整的傳輪=路與方法，特別是 發明背景： 電腦以及相關的技 目ΛΑ 土七 议婀已經改變世界的面貌，並且在 ==卜電：藉由其曰新月異的功能將繼續扮演 示了节見的桌上型電腦，電腦所發展的技 :广漸應用於各種電子設備，例如手機。很明顯地， 更夕電腦技術將被應用於各式各樣的電子設備中。 木構疋決疋電月向性能的主要因素之一。電腦架構包括資 料流的設計。即使有最強的處理器，但是如果欠缺良好 的架構，仍然無法發揮強大的功能。 第1圖繪示一個傳統電腦系統的部分架構圖。中央 處理器101連接到一個積體電路。此積體電路具有核心 邏輯1 02、VGA電路1 03及隨機動態存取記憶體控制電 路1 04積體電路。隨機動態存取記憶體控制電路1 〇4進 一步連接到隨機動態存取記憶體1〇5。首先，中央處理器 1 01根據執行程式產生緣圖資料。接著，這些緣圖資料傳 送到核心邏輯1 02。核心邏輯1 02接著將這些繪圖資料 分派給VGA電路1 〇3。在VGA電路103處理後，對應 的資料傳送到動態隨機存取記憶體控制電路1 04，並且隨 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ...............^.........、可.........>^ (請先閲讀背面之注意事項再場寫本頁) 經濟部智慧財產局員工消費合作社印製 晶 電路 579464 五、發明説明（) 後被填寫到動您隨機存取記憶體1 〇5中。 〇問題出在中央處理器101與核心邏輯102中間的信 號線其頻寬往往大於核心邏輯102與VGA電路1 03間 的化號線。換句話說，當核心邏輯VGA電路103在-個 時間週期接收到的資肖，需I花費數個時間i期才能將 之迗出。如此的設計造成了效能的降低。 /此外’並非所有的資料都必須經由VGA電路1〇3處 理後^才能傳送到隨機存取記憶體控制電路104。然而， 廷些貪料仍然必須通過VGA電路巧〇3。如此的設計著實 造成不必要的時間浪費。 但是，如果直接增加核心邏輯102與VGA電路103 間的頻寬’將是-件耗費成本與增加設計上的複雜度的 工程。=如我們能夠找出一個簡單的調整方法，而不需 大費周章造成成本的提高，將對電腦架構的改進 要的貢獻。 ▼木1 發明目的及概述： 蓉於上述之發明背景中所提及的問題，本 才示即為提出低成本的高效能架構。 、 :發明的一實施例為一傳輸電路。 =路及計算電路。分派電路的例子包括用於電： 片、.且中的核心邏輯，而計算電路的例子包括vg 傳輪電路介於處理電路與記憶體控制電路間。處理 本紙張尺度適财關家標準(CNS)A4規格(2數297公楚「 ...............^.........t.........^ (請先閲讀背面之注意事項再場寫本頁> 五、發明説明（） 連接到分派電路。分派電路經由第二信 =體μ丨t异電路。計算電路經由第三信號線連接到 路。記憶體控制電路則連接到記憶體裝 置例如動恶隨機存取記憶體。 &在分派電路與記憶體控制電路間則是透過快 速n線連接。在傳輸電路運作的過程中，首先處理 路傳送資料流到分派電路。分派電路谓測此時是否符合 件。假如符合加速條件’資料流經由快速信號線 直接傳达到記憶體控制電路。假如不符合加速條件，分 派電路將資料流傳給計算電路進行處理。 加速條件包括偵測資料是否適合直接傳送給記憶體 控制電路。此外，加速條件亦包括仙快速信號線是否 致能或存在可使用。此外，加速條件亦包括侧計算電 路是否處於閒置狀態。當計算電路處於閒置狀態，^為 順序錯誤造成的危險不存在，故此時便能直接將資料流 傳給記憶體控制電路進行寫入動作。 、机 職是，本發明彡成了提供低成本且具有$文能的傳輪 架構。 圈式簡單說明： 本發明的較佳實施例將於往後之說明文字中輔以下 列圖形做更詳細的闡述，其中： 5 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 579464 經濟部智慧財產局員工消費合作社印製 五、發明說明（) 第一圖為習知技術的傳輸架構； 第一圖為依據本發明的傳輸架構的示意圖； 第一圖為第二圖實施例的流程圖； 第四圖為依據本發明實施範例的示意圖；以及 第五圖為第四圖實施範例的流程圖。 圈號對照說明： 1〇1 :處理器 103: VGA 電路 104 :動態隨機存取記 1〇5 :動態隨機存取記 201處理電路 202分派電路 204記憶體控制電路 206快速路徑狀態暫存 211第一信號線 213第三信號線 215記憶體信號線 402核心邏輯電路 404動態隨機存取記憶 405動態隨機存取記憶 407狀態裝置 411主匯流排 102·核心邏輯電路 憶體控制電路 憶體 203計算電路 205記憶體 器207閒置狀態暫存器 212第二信號線 214快速信號線 401中央處理器 403 VGA電路 體控制電路 體406狀態裝置 41積體電路 412 GUI匯流排 裝 訂 · ·»^— f請先閲讀背面之注意事項再場寫本頁) 本紙張尺度適用中關&標準(CNS)A4規格(2獻297公楚） 579464Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 579464 V. Description of the invention (Field of the invention: The present invention relates to a method and method of transfer wheel with dynamic path adjustment, especially the background of the invention: computers and related technologies The title ΛΑ Tuqiyiyi has changed the face of the world, and in == Budian: With its new features, it will continue to play the desktop computer that has shown the best, the technology developed by the computer: the wide application For various electronic devices, such as mobile phones. Obviously, computer technology will be used in a variety of electronic devices. Wooden structure determines one of the main factors for the monthly performance of electricity. Computer architecture includes data flow. Design. Even with the strongest processor, if it lacks a good architecture, it still cannot play powerful functions. Figure 1 shows a partial architecture diagram of a traditional computer system. The central processing unit 101 is connected to an integrated circuit. This product The body circuit has a core logic 1 02, a VGA circuit 103, and a random dynamic access memory control circuit 1 04 integrated circuit. The random dynamic access memory control circuit 104 is further connected to the random dynamic access memory 105. First, the central processing unit 101 generates edge map data according to the execution program. Then, these edge map data are transmitted to the core logic 102. The core logic 102 then These drawing data are assigned to the VGA circuit 103. After processing by the VGA circuit 103, the corresponding data is transmitted to the dynamic random access memory control circuit 104, and the Chinese National Standard (CNS) A4 specification (210X297) is applied with this paper standard. (Mm) ............... ^ ........., but ......... &^; (Please read the notes on the back first Write this page again) Printed crystal circuit 579464 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The description of the invention () is filled in the random access memory 1 0 05. 〇 The problem lies with the central processing unit 101 and The bandwidth of the signal line in the core logic 102 is often larger than the signal line between the core logic 102 and the VGA circuit 103. In other words, when the core logic VGA circuit 103 receives the data in a time period, it costs I It takes several time i periods to figure it out. Such a design causes a decrease in performance. 'Not all data must be processed by the VGA circuit 103 before it can be transferred to the random access memory control circuit 104. However, some data still have to pass through the VGA circuit. Such a design is really unnecessary Time wasted. However, if the bandwidth between core logic 102 and VGA circuit 103 is directly increased, it will be a costly project and increase the complexity of the design. If we can find a simple adjustment method, and It does not need to cost a lot to increase the cost, and it will contribute to the improvement of the computer architecture. ▼ Mu 1 Purpose and Summary of the Invention: The problems mentioned in the background of the above invention are just a low cost solution. High-performance architecture. : An embodiment of the invention is a transmission circuit. = Road and calculation circuit. Examples of dispatching circuits include core logic for electrical: chip, ..., and examples of computing circuits include vg transfer circuits between processing circuits and memory control circuits. Handle this paper in accordance with CNS A4 specifications (2 numbers 297 cm "............... ^ ......... t ... ...... ^ (Please read the notes on the back before writing this page> V. Description of the invention () Connect to the dispatch circuit. The dispatch circuit is via the second letter = body μ 丨 t. The third signal line is connected to the circuit. The memory control circuit is connected to a memory device such as a random access memory. &Amp; The fast circuit is connected between the dispatch circuit and the memory control circuit. It operates in the transmission circuit. In the process, the processing path is first transmitted to the dispatching circuit. The dispatching circuit tests whether the components are met at this time. If the acceleration conditions are met, the data stream is directly transmitted to the memory control circuit through the fast signal line. If the acceleration conditions are not met, the dispatching The circuit transmits the data to the computing circuit for processing. The acceleration conditions include detecting whether the data is suitable for direct transmission to the memory control circuit. In addition, the acceleration conditions include whether the fast signal line is enabled or available for use. In addition, the acceleration conditions also include Side calculation circuit Whether it is in an idle state. When the computing circuit is in an idle state, the danger caused by the sequence error does not exist, so at this time, the data can be directly transmitted to the memory control circuit for writing. At the same time, the invention is completed. Provide low-cost and energy-saving wheel structure. Simple description of the circle: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures, of which: 5 This paper size is applicable China National Standard (CNS) A4 specification (210X297 mm) 579464 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () The first picture is the transmission structure of the conventional technology; the first picture is the transmission according to the invention A schematic diagram of the architecture; the first diagram is a flowchart of the second embodiment; the fourth diagram is a schematic diagram according to an embodiment of the present invention; and the fifth diagram is a flowchart of the fourth embodiment. 1: processor 103: VGA circuit 104: dynamic random access record 105: dynamic random access record 201 processing circuit 202 dispatch circuit 204 memory control circuit 206 fast path State temporary storage 211 first signal line 213 third signal line 215 memory signal line 402 core logic circuit 404 dynamic random access memory 405 dynamic random access memory 407 state device 411 main bus 102 · core logic circuit memory control circuit Memory 203 calculation circuit 205 memory 207 idle state register 212 second signal line 214 fast signal line 401 central processor 403 VGA circuit body control circuit body 406 status device 41 integrated circuit 412 GUI busbar binding ·· » ^ — F Please read the notes on the back before writing this page.) This paper applies the Zhongguan & Standard (CNS) A4 specification (2 offers 297).
發明詳細說明： 、本發明揭露-傳輸電路及方法，供動態調整路徑以加 速處理電路與記憶體控制電路間的傳輸速度。 請參看第2圖。依據本發明實施例的傳輸電路係介於 處理電路201與記憶體控制電路2Q4之間。記憶體控制電 路204經由記憶體信號線連接到記憶體2〇5。傳輸電路包 括分派電路202與計算電路203。 分派電路202經由第一信號線211連接到處理電路 201。分派電路202經由第二信號線212連接到計算電路 203。計算電路203經由第三信號線213連接到記憶體控 制電路204。此外，快速信號線214提供分派電路2〇2直 接連接到記憶體控制電路204。 第一信號線211與快速信號線214的頻寬皆大於第二 信號線212的頻寬。換句話說，分派電路2〇2傳送資料的 時間比接收資料所需的時間還多。舉例來說，在第一信號 線211具有256位元寬，而第二信號線212具有64位元 寬時，分派電路203需要四個時間週期把來自處理電路 201 —個時間週期的資料給送出去。 處理電路201的例子包括各種不同電腦架構裡的中央 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)Detailed description of the invention: The present invention discloses a transmission circuit and method for dynamically adjusting a path to speed up a transmission speed between a processing circuit and a memory control circuit. See Figure 2. The transmission circuit according to the embodiment of the present invention is interposed between the processing circuit 201 and the memory control circuit 2Q4. The memory control circuit 204 is connected to the memory 205 via a memory signal line. The transmission circuit includes a dispatch circuit 202 and a calculation circuit 203. The dispatch circuit 202 is connected to the processing circuit 201 via a first signal line 211. The dispatch circuit 202 is connected to the calculation circuit 203 via a second signal line 212. The calculation circuit 203 is connected to the memory control circuit 204 via a third signal line 213. In addition, the fast signal line 214 provides a dispatch circuit 202 directly connected to the memory control circuit 204. The bandwidths of the first signal line 211 and the fast signal line 214 are larger than the bandwidth of the second signal line 212. In other words, the dispatch circuit 202 takes more time to transmit data than it takes to receive the data. For example, when the first signal line 211 is 256-bit wide and the second signal line 212 is 64-bit wide, the dispatch circuit 203 needs four time periods to send data from the processing circuit 201 for one time period. Go out. Examples of the processing circuit 201 include a central computer in various computer architectures. This paper is sized to the Chinese National Standard (CNS) A4 (210X297 mm).
...............f (請先閲讀背面之注意事項再場寫本頁) 、νφ 線 經濟部智慈財產局員工消費合作社印製 579464 A7............... f (Please read the precautions on the back before writing this page), νφ Line Printed by the Consumer Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs 579464 A7
五、發明説明（） 經濟部智莛財產局員工消費合作社印製 器。此外，分派電路202的例子包括一般晶片組電路 ^核心邏輯電路’以及各種電路中用來分派資料流的邏 輯電路B。此外，計算電路203的例子包括圖形處理号、 聲音處理器、輸出/輸入處理器，以及各種能 能的電路。 丁丁介力 以下’我們將說明上述的實施例如何運作。請同時夫 看第1圖及第2圖。.第2圖為第工圖實施例的運作流程 圖。 快速信號線214預先提供，以連接分派電路2〇2盘纪 憶體控制電誤204(步驟302)。在運作過程中，處理電路 201產生資料流，而此資料流係由一連串的資料組成，並 且此資料流傳送給分派電路202(步驟3〇4)。分派電路2〇2 包含邏輯電4以檢查是否傳輸電路在當時符合加速條件 (步驟306)。如果加速條件符合，分派電路2〇2經由快速 信號線214將資料流傳送至記憶體控制電路2〇4(步驟 308)。如果加速條件不符合，分派電路2〇2將資料流傳給 計算電路203(步驟310)。 資料流包括第一類資料與第二類資料。第一類資料須 預先經由計算電路203處理。舉例來說，第一類資料包= 輸出/輸入指令、二維或三維繪圖指令等等。如果第一=資 料未經過計算電路203的處理，這些資料是不能直接寫I 到記憶體205的。相對地，第二類資料則是那些可以直接 寫入記憶體205的資料。舉例來說，第二類資料包括線性 記憶體寫入資料。當分派電路202發現所處理的資料係第 本紙張尺度適用中國國家標準(CNS)A4規格(21〇χ297公爱） ...............t:.........、可.........^ (請先閲讀背面之注意事項再填、寫本頁) B7 五、發明說明（ 成立。此因為第-類資料需要經 只用來傳輪第二類資：的：理。換句話說，快速信號線214 此外，對於二類=用來㈣第-類資料。 來說，資料處麻M 貝；斗第一類資料交錯的資料流 料;順序也是相當重要的。有時候，因為資 訂 ==::誤，結果的錯誤:二 處於閒置狀自^一十异電路2。3的狀態。當計算電路203 造成資thlg ^ 4 I用快速信號線Μ4傳輸資料流將不會 =穴序的問題。計算電路203的狀態可以存在閒； 在：他：益2〇7中。當然’計算電路2〇3的狀態也可以存 m說種不同的記憶體中。此外，計算電路203的狀態 可以被動由分派電路2Q2查詢，亦可由計算電路2〇3主動 通知分派電路202。 此外在上面所描述的實施例中，傳輸電路也具有一 快速，徑狀態’以標示是否存在一快速信號線或此^速信 號線是否致能。此快速路徑狀態可存於暫存器2〇6中，當 線 然也可存於其他各種不同的記憶體中。快速路徑狀態也可 以從分派電路202外面的電路對之加以設定。在快速路徑 經濟部智慧財產局員工消費合作社印製 狀態為失能或顯示不存在時，上述的加速條件將不會成 立。 為了更清楚地說明本發明，以下提供實際的例子。請 參看第4圖與第5圖。 第4圖中所顯示的例子係應用於今日常見的電腦架 構中。中央處理器401連接到晶片組的積體電路41。至於 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐） 579464 五、發明説明（） 連接在中央處理器與動態隨機記憶體間的積體電路通常 稱做北橋晶片。 積體電路41包括核心邏輯電路402作為前述的分派 電路，VGA電路403作為前述的計算電路，以及動態隨機 存取έ己憶體控制電路404作為前述的記憶體控制電路。中 央處理器401經由主匯流排411連接到核心邏輯電路 402，此主匯流排具有256位元的寬度，以作為前述的第 一信號線。核心邏輯4〇2經由繪圖匯流排412連接到VgA 電路403，此繪圖匯流排412具有64位元寬，以作為前 述的第二信號線。VGA電路4〇3經由記憶體資料匯流排 413連接動態隨機存取記憶體控制電路4〇4，此記憶體資 料匯流排413具有128位元寬，以作為前述的第三信號 線。此外，提供一快速路徑414藉以連接核心邏輯電路4〇2 及動態隨機存取記憶體控制電路4〇4，此快速路徑414具 有128位π寬，以作為前述的快速信號線。動態隨機存取 記憶體405的例子包括128位元的單資料傳輸S[)R128或 256位元的平衡雙資料傳輸DDR256類型。 狀態暫存器406儲存一變EnVGA—FastRdw「，此變數 用來描述是否存在-快速路徑414或快速路徑414是否致 能。另-個狀態暫存器407儲存一變數VGA」d|e， 數描述VGA電路403是否處於閒置狀態。 接著，請參看第5圖，此圖為第4圖範例的運作流程 圖1先，核心邏輯電路4〇2自中央處理器4〇1接收緣圖 資料的資料流(步驟502)。核心邏輯電路碰偵_^^ 10 本纸張尺度適用中國國豕標準(CNS)A4規格(2l〇X297公楚） 五、發明説明（）V. Description of the invention () Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In addition, examples of the dispatch circuit 202 include a general chipset circuit, a core logic circuit, and a logic circuit B for dispatching a data stream among various circuits. In addition, examples of the calculation circuit 203 include a graphics processing number, a sound processor, an output / input processor, and circuits of various capabilities.丁丁 介 力 Below we will explain how the above embodiment works. Please look at pictures 1 and 2 at the same time. Figure 2 is the operation flow chart of the embodiment of the working drawing. The fast signal line 214 is provided in advance to connect the dispatch circuit 202 to the memory control electrical error 204 (step 302). During operation, the processing circuit 201 generates a data stream, and the data stream is composed of a series of data, and the data stream is transmitted to the dispatch circuit 202 (step 304). Dispatching circuit 202 includes logic circuit 4 to check whether the transmission circuit meets the acceleration conditions at that time (step 306). If the acceleration conditions are met, the dispatch circuit 202 transmits the data stream to the memory control circuit 204 via the fast signal line 214 (step 308). If the acceleration conditions are not met, the dispatch circuit 202 passes the data to the calculation circuit 203 (step 310). The data stream includes the first type of data and the second type of data. The first type of data must be processed by the calculation circuit 203 in advance. For example, the first type of data package = export / import instructions, 2D or 3D drawing instructions, etc. If the first data is not processed by the calculation circuit 203, these data cannot be directly written into the memory 205. In contrast, the second type of data is data that can be directly written into the memory 205. For example, the second type of data includes linear memory write data. When the dispatching circuit 202 found that the processed data was the first paper size applicable to the Chinese National Standard (CNS) A4 specification (21〇χ297 公 爱) ............... t: ... ......, can ......... ^ (Please read the notes on the back before filling out and write this page) B7 V. Description of the invention (established. This is because the first-type data needs to be reviewed only It is used to transfer the second type of data: the: management. In other words, the fast signal line 214 In addition, for the second type = for the first-type data. The order of the data is also very important. Sometimes, because the order == :: is wrong, the result is wrong: the second is in a state of idle ^ ten different circuits 2.3. When the calculation circuit 203 caused the resources thlg ^ 4 I will not use the fast signal line M4 to transmit the data stream = the problem of acupoint order. The state of the computing circuit 203 can be idle; in: he: Yi 207. Of course, the state of the 'computing circuit 203 can also be It is stored in a different kind of memory. In addition, the status of the computing circuit 203 can be passively queried by the dispatch circuit 2Q2, or the dispatch circuit 202 can be actively notified by the compute circuit 203. In addition, in the embodiment described above, the transmission circuit also has a fast state, to indicate whether there is a fast signal line or whether the fast signal line is enabled. This fast path state can be stored in the register 2. In 6, the line can also be stored in various other memories. The state of the fast path can also be set from the circuit outside the dispatch circuit 202. The printed status of the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economics of the fast path is When disabling or display does not exist, the above acceleration conditions will not be established. In order to explain the present invention more clearly, the following practical examples are provided. Please refer to Fig. 4 and Fig. 5. The example shown in Fig. 4 is It is used in today's common computer architecture. The central processing unit 401 is connected to the integrated circuit 41 of the chipset. As for this paper standard, the Chinese National Standard (CNS) A4 specification (210X297 mm) 579464 is used. The integrated circuit between the central processing unit and the dynamic random access memory is generally referred to as a Northbridge chip. The integrated circuit 41 includes a core logic circuit 402 as the aforementioned dispatch circuit. The VGA circuit 403 serves as the aforementioned calculation circuit, and the dynamic random access memory control circuit 404 serves as the aforementioned memory control circuit. The central processing unit 401 is connected to the core logic circuit 402 via a main bus 411, which has 256-bit width as the aforementioned first signal line. The core logic 402 is connected to the VgA circuit 403 via a drawing bus 412, which has a 64-bit width as the aforementioned second signal line The VGA circuit 403 is connected to the dynamic random access memory control circuit 404 through a memory data bus 413. The memory data bus 413 has a width of 128 bits and serves as the aforementioned third signal line. In addition, a fast path 414 is provided to connect the core logic circuit 402 and the dynamic random access memory control circuit 404. The fast path 414 has a 128-bit π width as the aforementioned fast signal line. Examples of the dynamic random access memory 405 include a 128-bit single data transmission S [) R128 or a 256-bit balanced dual data transmission DDR256 type. The state register 406 stores a variable EnVGA-FastRdw ", this variable is used to describe whether there is-fast path 414 or whether fast path 414 is enabled. Another state register 407 stores a variable VGA" d | e, number It is described whether the VGA circuit 403 is in an idle state. Next, please refer to FIG. 5, which is the operation flow of the example of FIG. 4. First, the core logic circuit 402 receives the data flow of the edge map data from the central processing unit 401 (step 502). Core logic circuit detection _ ^^ 10 This paper size is applicable to China National Standard (CNS) A4 specification (210 × 297). 5. Description of the invention ()
仏動：於線性'己憶體資料，此線性記憶體資料在傳 ==取記憶體控制電路404之前不需經由VGA 的線性纪情此時’假如所接收的資料並非屬於前述 α匯士排貝料，加速條件不成立，並且此資料經由繪 ==叩傳給VGA電路備進行處理（步驟508)。否 /牛锁玄Γη邏輯電路4〇2 '繼續檢查變數EnVGA-FastRdWr 如果EnvGA—_嶋之值為假，也就是 徑414或是快速路徑414未被致能，此接 貝；’”亦㈣_匯流排412傳給vga電路彻 理（步驟508) 〇 接著’核心邏輯電路402繼續檢查是否vga電路4〇3 =於閒置狀態（步驟510)。假如VGA電路4〇3處於間置狀 :二也就疋說加速模式滿足時’所接收的資料便經由快速 役414傳給動態隨機存取記憶體控制電路例步驟 512)。 …藉由上面的說明與範例’對於習知技藝中人應已能據 以貫作。並且’本發明的優點也在這些敘述中很清楚的得 到證明，這些優點至少包括； 第- ’對於通常扮演效能瓶頸角色連續線性記憶體寫 入指令’我們提供了有效率而且低成本的解決㈣，來達 成資料傳輸的工作。第二，所有軟體無須改寫，因為本發 明具有軟體透通性。第三，本發明所提供的修改具有低成 本。第四，對於那些經由快速路徑傳送的資料來說，傳輸 時間更因為省略了經過VGA電路或其他計算電路，而^ 11 本紙張尺度適用中國國家標準(CNS)A4規格(210x 297公釐) 579464 A7 _B7_ 五、發明説明（） 到實質的降低。 如熟悉此技術之人員所瞭解的，以上所述僅為本發 明之較佳實施例而已，並非用以限定本發明之申請專利 範圍；凡其它未脫離本發明所揭示之精神下所完成之等 效改變或修飾，均應包含在下述之申請專利範圍内。 ...............¥.........、玎.........^ (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)Throbbing: Yu linearity has memorized the data. This linear memory data does not need to pass through the VGA linear record before the memory control circuit 404 is transferred. At this time, if the received data does not belong to the aforementioned α-Hui Shi row It is expected that the acceleration conditions are not established, and this data is transmitted to the VGA circuit device for processing (step 508). No / Niu Suo Xuan Γη logic circuit 402 'Continue to check the variable EnVGA-FastRdWr If the value of EnvGA__ 嶋 is false, that is, the path 414 or the fast path 414 is not enabled, this connection is made;' ”也 ㈣_ 汇流Row 412 is passed to the vga circuit completely (step 508). Then the 'core logic circuit 402 continues to check whether the vga circuit 4 03 = is in an idle state (step 510). If the VGA circuit 4 03 is in an interposed state: the second is Let's say that when the acceleration mode is satisfied, the received data is transmitted to the dynamic random access memory control circuit (step 512) through the fast operation 414.… With the above description and examples, it should be able to be used by those skilled in the art. Consistent operation. And 'The advantages of the present invention are also clearly demonstrated in these narratives. These advantages include at least; Section-' For continuous linear memory write instructions that usually play a performance bottleneck role 'we provide efficient and low The solution of the cost is to achieve the data transmission work. Second, all software does not need to be rewritten because the present invention is software transparent. Third, the modification provided by the present invention has low cost. For those materials transmitted via the fast path, the transmission time is more because the VGA circuit or other calculation circuits are omitted. ^ 11 This paper size applies to the Chinese National Standard (CNS) A4 specification (210x 297 mm) 579464 A7 _B7_ V. Description of the invention () to a substantial reduction. As understood by those skilled in the art, the above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the patent application for the present invention; Equivalent changes or modifications made under the spirit disclosed by the present invention should all be included in the scope of patent application as described below ............... ¥ ....... .., 玎 ......... ^ (Please read the precautions on the back before filling out this page) The paper printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is compliant with China National Standard (CNS) A4 specifications ( 210X297 mm)