TW578391B - Error correction code circuit with reduced hardware complexity - Google Patents

Abstract

An error correction code circuit with reduced hardware complexity is positioned inside a microprocessor. The microprocessor has a Galois field multiplier for performing a Galois field multiplication on data processed by the error correction code circuit. The error correction code circuit has a first register for storing an input data, a plurality of calculation units, a third register for storing an output data corresponding to the input data, and a controller for controlling operation of the error correction code circuit. Each calculation unit has a Galois field adder, and a second register electrically connected to the Galois field adder. The controller transmits data of each calculation unit to the same Galois field multiplier for a corresponding Galois field multiplication, and the result outputted by the Galois field multiplier is transmitted back to the error correction code circuit.

Description

578391

FIELD OF THE INVENTION The present invention provides an error check code operation circuit operation circuit, and more particularly, an error check code operation circuit that reduces hardware complexity. Background: Error correction code (ECC) is commonly used to prevent digital data from generating errors due to noise and other factors. Among them, the Reed-Solomo η error check code has been widely used in digital communications. 'For example, mobile communication, satellite communication, etc., and digital data storage devices, such as optical disks, etc. Please refer to Figure 1. Figure 1 is a conventional error correction system. syst em) 1 0, the error correction system 10 includes an encoder 1 4 which uses Reeed-S ο 1 〇m ο η algorithm to convert an input data 1 2 into a corresponding coded data (code word ) 16 'Reed-Solomon algorithm operates on the input data 12 in a block manner. For example, RS (n, k) represents the encoded data 16 contains n encoding units (symbols), and the input data 1 2 contains There are k coding units, each of which contains m bits, and the encoder 14 will generate (nk) coding unit errors based on the input data Check code. The error check code is appended to the input data 12 and the error check code is generated in a finite field (Ga 1 〇isfie 1 d), such as GF (2 m), and then written into unit 1 8

Page 5 578391 V. Description of the invention (2) The encoded data 16 will be written into a storage unit 20 for storage. A reading unit 22 can be used to retrieve the encoded data 16 stored in the storage unit 20 and transmit it to a decoder 24 to read the corresponding input data 12. The decoder 24 includes a check circuit ( syndrome generator) 26, a polynomial generating circuit 28 ', an error position calculation circuit (error 〇Cating circuit) 30', an error value calculation circuit (6ΓΓ〇Γ value calculator) 32, and an error correcting circuit 34. The check circuit 2 4 is used to test whether the encoded data 1 β generates an error and generate a check code. The check code is generated by the polynomial circuit 2 8 according to the conventional E uc 1 idea η algorithm or Berlekamp-Masse. The y algorithm is used to calculate an err0r location polynomial and an error value polynomial, and the error position calculation circuit 30 calculates the error position polynomial according to a search operation (Chi en search). Calculate the bit position where the error actually occurred, and then the error value calculation circuit 32 calculates the error value of the bit position of the error according to the bit position of the error, the error position polynomial, and the error value polynomial, Finally, the correction circuit 34 can correct the erroneous bit according to the erroneous bit position and its corresponding error value. Please refer to Figs. 2, 3, and 4. Fig. 2 is a schematic circuit diagram of the encoder 14 shown in Fig. 1, Fig. 3 is a schematic circuit diagram of the inspection circuit 26 shown in Fig. 1, and Fig. 4 is shown in Fig. 1. The circuit diagram of the error position arithmetic circuit 30. For the encoder 14, it includes a plurality of registers 36, a plurality of multipliers 38, and a plurality of adders 40. The Reed-Solomon

Page 6 578391 V. Explanation of the invention (3) The algorithm uses a generated 吝 吝, to input data = i (gerrH polynomial) G (x) The peak point evening: η 4 r, the difference is different, and the mother A multiplier 38 is respectively corresponding to the 12 $ line of the material i; a half (χ) ί coefficient (C0effiCient) is used to temporarily operate with the input and output upper stage, and the adder 40 is used to output the multiplier 38. The temporary data stored in the device 36 is added and stored in the temporary device 6, where the adder 40 is used to perform a logical operation of mutual exclusion or ve 0R, χ〇1Ό on exclus. When the input data U has been transferred to the β β τ Μ of 1 2, the temporary storage device stores the corresponding input data error code. Finally, the input data 1 2 and the temporary storage device 36 perform a finite field method to output encoded data 1 6. As for the inspection circuit 26, it is also im: ί 40 ′, a plurality of multipliers 38, and the number of i; fixed storage is 36, according to t know Reed — s〇1〇m〇n algorithm can know the encoding = The generator polynomial G (x) has a multiple relationship. If each coding unit / packet 3 has 8 bits, the encoded data 6 corresponds to an n-degree polynomial R (material 12 corresponds to a polynomial κχ). The generator polynomial G (x) is more than one degree, term, then R (x) = q (x) * G (x) = i (x) · Xn-k + r (x) = Ι (χ) · xnk + I (x) modG (x), where mod is the remainder operation (m〇dul〇divisiQn), the generator polynomial G (x) is n polynomial with n roots (G (x)) = β (χ —α 9 α The instrument is the finite field element of the finite field gf (2 8), so each root of the generator polynomial g (x) is substituted into R (X). Zero, '^ and if the X-coded data 16 contains the wrong data e (X), it results in ..... R (x) = Q (x) * G (x) + E (x), so when Each of the generator polynomials G (x)

Page 7 578391, invention description (4) When the limiter is substituted into the R (x) calculation, a non-zero value will be obtained, and each corresponding value is a check code (syndrom), so the encoding data ^ ^ For each encoding of Luo Qi, the input check circuit 26 performs field addition through the adder and stores the operation result in the temporary register 36, and 38 is corresponding to each ai of the generator polynomial G (x). Perform a finite field multiplication with the operation result stored in the temporary register 36, and then perform a finite field addition operation with another encoding unit. Repeat the above steps until each encoding unit of the encoded data 16 completes the above steps. Each register 36 stores the check code corresponding to the coded data. From three, the time-checked codes are all zero, indicating that the coded data did not generate any error. = 二 After circuit 26 completes the check code operation, As shown in Figure 1: Two: Lu 28 will calculate the production ± one error bit according to the conventional calculus ☆ ^ "Electric P (x): c10nnc9n- + …… + 1, where 2, equals k, and wrong two η room operation (㈤ ... addition—the calculation results in an error finding, the operation circuit 30 contains a plurality of additions Device 4, complex number U, error M, and multiple temporary registers 36. First, temporarily = raft sydrome and polynomial A from the position polynomial of the picker, and the slave A 36 will use the error coefficient and unitary coefficient as initial values, respectively. And each multiplier 38 will separately consider the information ^-two ... after each multiplication 15 38 will be multiplied with the storage of the register 36 and store the results and then cry for each temporarily Wide review, = $ to the corresponding register 36, whether it is-a predetermined value (for example, "Go 0"), so; H: f is true and the wrong location is transported ίϊίο 传 ί :: device 14, check the circuit 26, to Different circuit 3 0 is a technology well known in the industry, and its details

578391, invention description; = ί; the principle of the relevant algorithm is not the focus of this case, so it is not here

s? Because the error check code is generated in a finite field, no matter whether the encoder 1 4 or the decoder 2 4 needs to perform operations through finite field multiplication and finite field addition, it must use a multiplier 3 8 And adder 40 (as shown in Figures 2 to 4), so the conventional technology discloses an integrated arithmetic circuit, in which the same multiplier and adder can be applied to circuits with different functions, such as U.S. Patent No. 4, No. 584, 686 "REED-SOLOMON ERROR ⑶flection apparatus" discloses an arithmetic circuit, which integrates the encoder 14 and the inspection circuit 26 shown in Fig. 1. The encoders 14 and 2 are shared by the same circuit, which are the same as the register, the finite field multiplier, and the finite field adder, so it can save hardware resources and reduce costs. However, the conventional arithmetic circuit needs to make a plurality of finite The field multiplier, because the hardware of the finite field multiplier is more complicated than the finite field adder, so the power consumption of the finite field multiplier is also relatively high, so the second step causes the size of the conventional arithmetic circuit to be large and It is more power-consuming and the plurality of finite field multipliers will also increase the production cost of conventional manure transportation. Summary of the Invention ^ The present invention provides an error check code computing circuit that reduces hardware complexity to solve the above problems.

Page 9 578391 V. Description of the invention (6) The scope of patent application of the present invention provides an arithmetic circuit provided on a micro-processor for calculating an input data to generate an output data. The micro-processing The device includes a finite field multiplier (Galois field multiplier), which is electrically connected to the operation circuit and is used for performing finite field (Ga 丨 〇 丨 sf 丨 e 1 d) multiplication operation on the data calculated by the calculation circuit. The microprocessor is provided with a register file for storing data to be processed, and the arithmetic circuit includes a first register for temporarily storing the input data, a plurality of arithmetic units, and a third, Storage for temporarily storing the output data, and a control circuit for controlling the operation of the operation circuit. The plurality of operation units are connected in series as cade). The first operation unit of the plurality of operation units is connected to the first register, and each operation unit includes an input terminal and a factory output. Terminal, a finite field adder (Galois field adder), electrically connected between the input terminal and the output terminal, and a second temporary storage in the limited field adder. 1 The third register is connected in series; The last-operation unit in the n element. The control circuit will transmit the data of the i and the two operation units that need to be multiplied by the finite field to the same multiplier operation, and return the multiplier to the operation circuit. # Please refer to FIG. 5 for a detailed description of the invention. FIG. 5 is a functional block diagram of the digital signal processor (dlgltal slgnal processor) 40 of the present invention.

Page 10 578391 V. Description of the Invention (7) Processor 4 0 is used to perform the encoding / decoding related operations of Ree d-S ο 1 〇 m ο η error correction code. The digital signal processor 40 includes an operation circuit 4 2 and a finite field multiplier 44, and the operation circuit 42 includes an operation module 46, a control circuit 48, and an input / output port 50. The input / output port 50 receives an input data through an input terminal 5 2 and the control circuit 4 8 transmits the input data to the computing module 46. The computing module 46 is only used to perform a finite field on the input data. Addition operation, and when the input data needs to be multiplied by the finite field, the control circuit 48 will send the input data to the finite field multiplier 4 4 through the input / output port 50 for processing. After the field multiplication operation, the input data will be returned to the arithmetic circuit 42 via the finite field multiplier 4 4, and the control circuit 48 will retrieve the input data through the input / output port 50 and transmit the input data to the arithmetic mode. Group 46 is used for subsequent processing. In this embodiment, the operation module 46 is used to process the finite field addition operation, and the finite field multiplier 44 is used to process the finite field multiplication operation and managed by the control circuit 48. The data transfer between the operation module 46 and the finite field multiplier 4 4 'is until the finite field addition (that is, a mutually exclusive or (XOR) logic operation circuit) and the finite field multiplication operation required for the input data are completed. 50 and then output to the output terminal 54 via an input / output port. Please refer to FIGS. 6, 7, 8 and 9. FIG. 6 is a circuit diagram of the operation module 46 shown in FIG. 5. FIG. 7 is a first equivalent circuit diagram of the operation module 46 shown in FIG. 6. A second equivalent circuit diagram of the operation module 46 shown in FIG. 6, and FIG. 9 is a third equivalent circuit diagram of the operation module 46 shown in FIG. 6. The operation module 46 includes a plurality of operation units 56.

578391 V. Description of the invention (8) The arithmetic unit 56 includes a register (1 ^ § 丨 51 ^ 〇58, a first switch 62, and a second switch 64), and further includes an input register 66 for To temporarily store an input data, the register 68 is used to temporarily store an output data, where the input temporary storage = ^ 6 is connected via a first switch 6 2 and the output temporary το 5 6 is connected via a second switch 6 4 In this embodiment 48, the number of computing units 56 that can be enabled can be activated according to the number of coding units of the required error check code, that is, the controlled computing module 46 performs Reed-Solomon operations. The first switch 62 and the second switch 64 of the stage 56 also generate equivalent circuits with different functions. For example, the equivalent circuits of the iif LS1, S2, and the connection terminal 46 of the second switch 64 are shown in FIG. Please refer to the circuit combination class of the finite field multiplier 44. The register 36, the multiplier 38, and the addition structure in u are the only differences in Figure 2 & i will a. Related finite field addition and finite field Multiplication: ί2 input data # 12 progress-finite field addition operation two = 2 material 16, W in this embodiment ^ ^ temporarily stored 66 is connected to the output register 68 and 60, so the actual calculation procedure 4L is in the form of a weight. For example, ^ ^ ^ ^ The hardware circuit of the above adder, the input register 66 and the output Temporarily store @ 68 & prudent arithmetic program, 隹 — 笮 笮 仔仔 6 8 bei, and add the finite field addition operation. Compare the adder 6 0, the calculation module 4 6 additional package and an output During the calculation of the temporary register 6 6 and the operation single register 6 8 and the operation, the control circuit determines the required starting circuit 4 8 programmable number, and each operation is controlled by the control circuit 4 8 when the first switching point E 2 E 2 Figure 2 and Figure 7 are similar to the encoder 14 composed of the encoder 40 shown in Figure 2. After the pair of input operations are calculated, the module 46 is finally calculated and ^ one addition | § Addition of a finite field That is, the finite field addition module 4 6 and the editor are read separately.

V. Description of the invention (9) Field multiplication 纟 44 takes two 焉 m: The function of multiplier 38 is composed of a finite per-operation unit two; two 8 must add the operation module 4 field addition operation, :::: =; = Can be correctly performed: The finite field multiplier 44 performs a relative input of the zongzi will first pass the calculation: the result back to the operation module 46, multiply the t operation, and then perform the calculation-the finite field addition Operation] = data and this register 58, and finally the output register | 8 ^ =, 2 results, stored in the input data of its temporary register 6 6 and the result of the __ ^ ^ sub operation Input the finite field addition program operation (through the above code data 16), so the operation of Figure 7 Z: = Z is the finite field multiplication operation of the encoder 38 shown in Figure 1 are all given by a finite d = 2, multiplication Therefore, in the arithmetic module 46 of FIG. 7, the hardware of the multiplier 38 is learned at $ 44. Therefore, it is possible to reduce the production of U 疋 56 without including the first switch 6 of the arithmetic module 46 of FIG. 6 and When the second switch 64 is connected to the end points π and μ, the input data of jm: 2 'will be transmitted simultaneously through-= "input: 60, via * corresponding finite field addition * The calculation is combined in register 58 :, and then the control unit will send register 58; sub 3 2 to the finite field multiplier 44 for a finite field multiplication operation, and then $ 578391. V. Invention description (10) Operation The result is transmitted to the arithmetic module adder 60 for subsequent limited input. The input register 66 is stored in the code world register 58, and the code data is stored in the register 58 if each check code is zero. The operation combination shown is the inspection group shown in Fig. 3. The 6 and 6 are each shown in Fig. 3: A finite-field multiplier 44 is used to make 3 errors. Then, the normal operation is repeated. Code (showing that the code 4 6 and the finite 2 6 ′ have the same input 38 through the nasal transport unit 5 6 which is another input data step 'until a corresponding end of the material, where each syndrome code data does not produce a field multiplication The circuit ground of the device 44, the operation mode limited field multiplication operation of FIG. 8 are all used as the operation mode operation of FIG. 6 and the 4 β switch 64 is connected to the end points El, '' th;]: 62 forms a break, and the ninth Yan Qing refers to Figure 4 and Figure 2: 3, and the equivalent electric power of 46 As shown in Figure 30, it is used to perform a continuous accumulative error position operation (Chien search), such as the register multiplication operation of the conventional search operation element ... Π diagram of the error position polynomial of the operation order = term form generation circuit Calculated by 28, there are 172 coding units, each and a series + case theory. If the input data 12 contains personal data, I2 corresponds to a finite field. GF (孓 之 '疋 is 8 in length, that is, loses 媪〇1, the limit% GF (2 «), which contains a plurality of finite two ί terraces (please note that α% is 0), when the figure 1 is edited ΐ ^ ϊ ί: is a generator polynomial G (x) of 20 to Generate encoding data ',, a produces 20 error check codes attached to the input data 1 2, so 578391 V. Description of the invention (π) The encoded data 16 contains 1 8 2 coding units, which corresponds to RS (1 8 2 , 1 7 2), and it can correct a maximum of 10 coding units, so the error position polynomial is P (x) = C1G * X1G + C9 * X9 + ...... + C2 * X2 + C ^ XHl, then The finite field elements α 1, ..., α are the error position polynomials ρ (χ). If P (α ζ) is not 0, it means the second code list in the coded data. wrong. So first, each register 5 8 stores the system of the error position polynomial, h, h. When performing a conventional search operation, the finite field multiplier 44 performs a finite field on each finite field element a 1G, ..., α Correspond to the register 58 (respectively store the coefficient C 1 (Γ ···· c!) For multi-field multiplication and return the results to the f register 58 respectively, that is, each register 58 is temporarily stored Cl () (α 1〇), c9 j α, 9) / ......, C 丨 (a D), and then perform a finite field addition operation on each register via adder 60, so the output is temporarily Register 6 8 will record C 10 · a α 9 + ...... + c ι · «" is P (α 丨) -1. If the first a coded list 70 is correct, then p (a D Should be 0, that is, P (a: i) -1 should be 0 as well. 'Finite field multiplier 4 4 will also be for each finite field element, ..., α 1 and corresponding register 68 (stored separately) ClQ · α Η ·· α performs finite field multiplication at $ 轫 〇 and returns the results to 1G sub ^ 8 respectively, that is, each register 58 will be temporarily stored at this time (Ci〇 · L:: A …)…, ..., (Cl, which is 10 α 10, (C 9 · α 2) · α 9, ... (C · α 2) · α!, So the output is temporarily stored 3! 68 combined magic pr 2,?; You can determine whether the No. 24 i ^ ^ 疋 is correct. After the above operation, you can check the decoding one by one. Ϊ́ There is an error in the coding unit in the code / material 16, so that the circuit diagram shows that the output register 6 8 will Record ρ (X)

Page 15 578391 V. Description of the invention (12): The calculation result of ι, so the coded data is determined by judging whether 疋 is 1 or not 丨 6 produces potassium temporary storage ^ 68 storage 1 material Register 5 8 performs a finite field: method: After the code unit two is set to the right limit field and added, it is stored in the temporary register 68, $ |, where j has the result of P (X), so it can be determined by SJ: J "8 will record whether the data is 0 or not to determine the storage of the round-off register 68 in the encoded data 16. Therefore, the structure of the present invention can be used for the operation of the search operation of the coding unit that generates errors. To determine the number of multipliers 38 = two modes: the multiplier 44 is processed by the figure 46. The heterogeneous father is treated by a finite field input module 46, The π temporarily stored in the register 66 should be input ... and temporarily stored in the output; = after ;; The error check code required for the data must include many total steps 3-version right 4 input early Wu 5 6 ", and when When the number of coding units is large, the number of operations required to perform corresponding output data increases, and the path (Critical p ath), so the operation of the present invention is to increase at least one buffer register (the length of the low critical path) between the operation units 56. For example, if the operation circuit of the present invention includes two buffer registers, the The buffer register can use a plurality of operation units $ 6 and eight as the first and second operation blocks, and the first operation block calculates the input data of the knife register 6 and generates an operation. The result, 578391 V. Description of the invention (13) When the operation result is stored in the input data of the first operation block and an input is generated, the input register 6 can perform the operation, that is, the first can reduce the key Path rate, and to avoid the critical path embodiment, the finite field multiplied by the finite field multiplication operation, and then the calculation table (look-up operation value, so can be calculated by the 0 buffer register, and then the buffer temporary write operation results are used As the second operation ^ to recognize the data, and when the second operation area is used to input another input data-the first t is 1/2, not only can the reasoning path of the second reason be too long and cause the operation It is easy to produce errors. : 44 is a body electric, which is used for priests and the finite field multiplier 44 can also be a ^ le), which contains a table lookup of the finite field multiplication to perform the finite field multiplication. In the conventional technology, when a limited-field adder and a temporary calculation are included, the arithmetic unit calculates the row. Therefore, the operation unit of the present invention, therefore, not only the arithmetic unit of the power-consuming circuit includes an obvious arithmetic circuit, but the equivalent circuit system is different. The purpose of sharing the hardware resource sharing of the present invention is related to the Reed-Solomon operation. A buffer register and a sender are set between the elements, and the data calculation is low. The calculation is small, and the calculation processing with fewer circuits is transmitted to the equivalent electrical circuit that is routed to and from the volume of the switch. There is a limited number of operations through the parallel operation of the present invention. It is not too early. This component, the hardware and circuit can be used for the calculation of the limited field and field multiplication. This issue can be different, so it comes from this. It does not include only the multiplication method to enter the limited field and multiply it. Calculate the purpose of this hair can be reached.

ι · ιι Page 17 578391

Page 18 578391 Simple illustration of the diagram Simple illustration of the diagram Figure 1 is a schematic diagram of a conventional error correction system. FIG. 2 is a circuit diagram of the encoder shown in FIG. 1. FIG. 3 is a schematic circuit diagram of the inspection circuit shown in FIG. 1. FIG. 4 is a circuit diagram of the wrong-positioned nose circuit shown in FIG. 1. FIG. 5 is a functional block diagram of the digital signal processor of the present invention. FIG. 6 is a circuit diagram of the operation module shown in FIG. 5. FIG. 7 is a first equivalent circuit diagram of the arithmetic module shown in FIG. 6. FIG. 8 is a second equivalent circuit diagram of the operation module shown in FIG. 6. FIG. 9 is a third equivalent circuit diagram of the operation module shown in FIG. 6. Explanation of symbols in the diagram 10 Error correction system 12 Input data 14 Encoder 16 Coded data 18 Write unit 20 Storage unit 22 Read unit 24 Decoder 26 Check circuit 28 Polynomial generation circuit 30 Error position calculation circuit 32 Error value calculation circuit 34 Correction circuit 36> 58 register 38 ^ 44 finite field multiplier 60> 40 finite field adder 40 digital signal processor 42 arithmetic circuit

Page 19 578391 Simple illustration of the diagram 46 Computing module 48 Control circuit 50 Input / output port 52 Input terminal 54 Output terminal 56 Computing unit 62 First switch 64 Second switch 66 Input register 68 Output register

Claims (1)

578391 VI. Patent application circuit package), the operations are as follows: 5 operations on a micro-processor to calculate an input data to generate an output data, the micro-processing 3 has a finite field, A Gaois field multiplier is electrically connected to the arithmetic circuit, and is used for multiplying data of the finite field (Galois f ield) of the arithmetic circuit. The arithmetic circuit includes the complex and the generator end device. if 'is used to temporarily store the input data;:, ΐ 单 凡' are connected in a cascade manner, and the first operation unit is connected to the first temporary storage. It includes an input terminal, an output terminal, a Finite field adder), electrically connected to the input terminal and the input-second register, electrically connected to each finite element field of several arithmetic units, each arithmetic unit package (between Galois and 以及 * is used to control the The operation of the arithmetic circuit; the second circuit after the operation will perform a finite field multiplication of each arithmetic unit (i you η) to the same multiplier operation, and return the multiplier operation to the operation Circuit. Field addition 5 ί ί 2 The arithmetic circuit described in item 1 above, wherein the finite operation. ', Is-exclusive OR (X0R) logical operation ί 1 Ϊ f profit range described in item 1 A computing circuit, in which a Reed-So 1 〇mo η error correction code is included in the micro Page 21 578391 6. Scope of patent application Several coding units (s y m b ο 1). 4. The arithmetic circuit as described in item 3 of the scope of patent application, wherein the control unit determines whether to enable the arithmetic unit based on the number of coding units of the Reed-S ο 1 〇m ο η error correction code. number. 5. The arithmetic circuit according to item 1 of the scope of the patent application, wherein the arithmetic unit further comprises: a first switch disposed between the second register and the adder, for controlling the electric power of the adder. Connected to the second register; and a second switch for controlling the adder to be electrically connected to an adder of an adjacent operation unit, or for controlling the adder to be electrically connected to a transmission line. 6. The arithmetic circuit according to item 5 of the scope of patent application, wherein when the first switch electrically connects the adder to the second register, and the second switch electrically connects the adder of the arithmetic unit to the phase When the adder is adjacent to the operation unit, the operation circuit is used to generate an error check code of the input data. 7. The arithmetic circuit according to item 6 of the scope of patent application, wherein when the first switch disconnects the adder from the second register, and the second switch electrically connects the adder to the transmission line The operation circuit is used to generate a syndrome code corresponding to the output data. 8. The arithmetic circuit as described in item 7 of the scope of patent application, wherein when the 578391 Application scope of open device student _ The switch makes the adder and the second temporary storage switch make the arithmetic unit's knowledge, the original cry, * = f _ way and the second :, the operation circuit is used to W location of this check. The calculation circuit described in item 6 of the output range of the body-building circuit is suitable for transporting dung :! It also contains a 'buffer register' (buffer) between the different early and early generations, which connects the Xiegujing Free Scholars. The output data inversely applied to an adjacent operation is used as input data generated by the arithmetic unit, and the operation form after the Haiqiang temporary register stores its output data before the operation unit register before the second register. The arithmetic unit ^ == temporary = stolen 'The connection to the buffer temporarily corresponds to the output data and is calculated from another input data-i ° multiplied by κ :, tm described, the operation circuit, where the software A circuit or a software look-up table. =: Two i !! The arithmetic circuit described in item 1 of the scope, wherein the micro-processing benefit is a digital signal processor (DSP) 〇 •三 2 1 第 如 应用 Patent Section # Register, the operation circuit described in the above item, which further includes — the last operation table connected to the plurality of operation units m SB! M p. 23