發明背景 本發明有關於解調電壓之解調器，該電壓藉由改變_言 位準與-低位準間之振幅而調變，特料詩從卡= 置至晶片卡之無接觸資料傳送。 ·’、、、 曰：：極：效率及廣泛的應用可能性使得具有電子晶片的 B曰片卡取代磁帶而日漸重，在此以接觸式操作的晶片卡I 無接觸式操作的晶Μ卡时差異。以接觸式操作的晶片; 具有的接觸區域於晶片卡已引人讀卡機後與對應的反接觸 互動及具有通孔其中卡上的晶片供有電壓及資料。惟 許多情況下以無接觸式操作的晶片卡是較佳的因為它可以 在不形錢觸之下操作，且不必^讀卡機。目此依規定 卡不具有其本身電壓供給，它不僅必須以無接觸式作資料 傳送，而且以無接觸式傳送功率以便在晶片卡上產生二供 給電壓，這也必須提供的。 曰習知有錢調變方法用以從讀卡機傳送資料到無接觸的 曰曰片卡’藉由改變二個位準間振幅（ASK振幅鍵移）的調變 特別受歡迎。除了稱為100% ASK調變以外，其中信號開 啟及關閉，10〇/。ASK是廣泛使用#。在此從振幅的8到 12%區域中的調變指數執行調變，振幅在此降為0，這產生 的結果特別適用於電源供給。 以10% ASK調變為例，當卡的移動在讀卡機的傳送場中 產生調變效果時，即對於晶片卡上的解調器作特別要求， 但必須有區別。結果，解調電路必須能在不同時段以1 〇% 的位準變動作解調，這是在不同時段操作電壓變動時，其 A7 B7 五、發明説明（2 ) =實祕幅調變大數倍。因此待解調的動態範圍也較大， 口此直有一種危險即下游評估電路被過分調變因而不能 得到滿易的鮮調。 wo 00/287G8敘述-種用於ASK 1〇%調變信號的解調電 路:其中提供―設^階段其中定義比較器的門檻值，該比 較器用以偵測不同的信號位準。 X電路方面杈複雜而另一方面需要一先前設定階段， 此外它不適用於ASK 100%調變信號。 為了利用曰曰片卡其能解調ASK 1〇〇%調變信號及ASK 1〇% 凋變h號，已設定分開的解調器而且適當的解調器已於偵 測到調變類型後作切換。至於ASK 1〇%調變信號，如根據 WO 00/28708使用的電路，至於ASK 1〇〇%調變信號，簡單 的電路即足以偵測間距。 發明總結 口此本發明的目的疋揭示一種解調器，其能解調Μκ 100%調變及ASK 10%調變的信號，且同時能直接且與讀卡 裝置相距較遠之下可靠地操作，因此本發明的解調電路是 最簡單的。 此目的可藉由一種解調電壓之解調器而達成，該電壓藉 由改變一咼位準與一低位準間之振幅而調變，特別適用於 從一卡讀寫裝置至一具有動態壓縮電路之晶片卡之無接觸 資料傳送，而輸入信號則出現在該動態壓縮電路，用以減 少輸入信號之動態，一濾波器其與動態壓縮電路之下游連 接用以濾除一高頻載波信號，一差分器其與濾波器之下游 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 578362 A7 B7 五、發明説明（3 連接用以放大濾波耦合信號中之邊緣，及一比較器其與差 分器之下游連接用以比較差分器之輸出信號與至少一可預 設門檻值。 此一解調器的第一優點是在實際資料傳送前不必設定階 段以判定比較門檻。另一優點是不必切換以便在Ask調變 之10%到100%之不同範圍中操作解調器。 雖然動態壓縮電路也使可用信號衰減，其結果是信號邊 緣更難偵測，這可藉由差分器而得到極大補償以放大邊緣 其與動態壓縮電路之下游連接，能使用比較器以便從放大 邊緣產生可以作進一步處理之信號。 在根據本發明解調器的較佳改良中，由M〇s二極體（其與 一參考電位連接）而形成動態壓縮電路，用於非線性電流/電 壓轉換。在-較佳改良中，#由_電流鏡而從整個電路之 輸入電流而產生通過二極體之電流。 為了定義比較門檻，最好從濾波器之輸出信號產生門檻 及藉由其他比較器而將其與差分器之輸出信號比較。 本發明的其他較佳改良如附屬項所述。 附圖簡單說明 以下用典型實例來詳細說明本發明，其中 圖1是用於晶片卡的電路配置的方塊電路圖， 圖2疋根據本發明的解調器的方塊電路圖， 圖3是實作解調器的特定電路配置，及 圖4是圖3電路配置中的電壓波形圖。 發明詳細說明BACKGROUND OF THE INVENTION The present invention relates to a demodulator for demodulating a voltage. The voltage is modulated by changing the amplitude between the _ speech level and the -low level. A special poem is transmitted from a card to a contactless data set to a chip card. · ',,, and :: Extremely: Efficiency and a wide range of application possibilities make B-chip cards with electronic wafers replace tapes and become heavier. Here, the chip cards that operate in contact I chipless cards that operate without contact Time difference. Chips that operate in contact mode; have contact areas that interact with the corresponding anti-contact after the chip card has been attracted to the card reader and have through holes in which the chip on the card is supplied with voltage and data. However, in many cases, a contactless chip card is preferred because it can be operated without touching the card and does not require a card reader. According to the regulations, the card does not have its own voltage supply. It must not only transmit data in a contactless manner, but also transmit power in a contactless manner in order to generate two supply voltages on the chip card. This must also be provided. The conventional rich modulation method is used to transfer data from the card reader to the contactless, and the smart card is particularly popular by changing the modulation between the two levels of amplitude (ASK amplitude key shift). In addition to the so-called 100% ASK modulation, the signal is on and off, 10 /. ASK is widely used #. The modulation is performed here from a modulation index in the region of 8 to 12% of the amplitude, and the amplitude here is reduced to 0, which produces a result particularly suitable for power supply. Taking the 10% ASK modulation as an example, when the movement of the card produces a modulation effect in the transmission field of the card reader, that is, special requirements are placed on the demodulator on the chip card, but there must be a difference. As a result, the demodulation circuit must be able to demodulate with a level change of 10% in different periods. This is the A7 B7 when the operating voltage changes in different periods. V. Description of the invention (2) = Largest number of real amplitude modulation Times. Therefore, the dynamic range to be demodulated is also large, and there is always a danger that the downstream evaluation circuit is over-modulated so that it cannot obtain a fresh and easy-to-adjust tone. Wo 00 / 287G8 describes a demodulation circuit for ASK 10% modulation signals: it provides the threshold value of the comparator defined in the setting stage, which is used to detect different signal levels. The X circuit is complex on the one hand and requires a previous set-up phase on the other hand, and it is not suitable for ASK 100% modulation signals. In order to use the Japanese khaki to demodulate the ASK 100% modulation signal and the ASK 10% decay h number, a separate demodulator has been set and an appropriate demodulator has been made after detecting the modulation type. Switch. As for the ASK 10% modulation signal, such as the circuit used according to WO 00/28708, as for the ASK 100% modulation signal, a simple circuit is sufficient to detect the pitch. SUMMARY OF THE INVENTION The purpose of the present invention is to disclose a demodulator that can demodulate κ 100% modulation and ASK 10% modulation signals, and at the same time can directly and reliably operate at a distance from the card reader. Therefore, the demodulation circuit of the present invention is the simplest. This purpose can be achieved by a demodulator that demodulates the voltage, which is modulated by changing the amplitude between a chirp level and a low level. It is particularly suitable for a card reader to a device with dynamic compression. The contactless data transmission of the chip card of the circuit, and the input signal appears in the dynamic compression circuit to reduce the dynamics of the input signal. A filter is connected downstream of the dynamic compression circuit to filter out a high-frequency carrier signal. A differentiator downstream of the filter. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 578362 A7 B7. 5. Description of the invention (3 connection to amplify the edge of the filtered coupling signal, and The comparator is connected downstream of the differentiator to compare the output signal of the differentiator with at least one presettable threshold. The first advantage of this demodulator is that it is not necessary to set a stage to determine the comparison threshold before the actual data is transmitted. One advantage is that it is not necessary to switch to operate the demodulator in different ranges from 10% to 100% of the Ask modulation. Although the dynamic compression circuit also attenuates the available signal, the result is a signal edge It is more difficult to detect, which can be greatly compensated by the differential to amplify the edge which is connected downstream of the dynamic compression circuit, and a comparator can be used to generate a signal from the amplified edge that can be further processed. In the demodulator according to the invention In the preferred improvement, a dynamic compression circuit is formed by the Mos diode (which is connected to a reference potential) for non-linear current / voltage conversion. In the -better improvement, # 由 _current mirror from The input current of the entire circuit generates the current through the diode. In order to define the comparison threshold, it is best to generate the threshold from the output signal of the filter and compare it with the output signal of the differentiator by other comparators. The preferred improvements are described in the appendix. Brief description of the drawings The following is a detailed description of the present invention with typical examples, in which FIG. 1 is a block circuit diagram of a circuit configuration for a chip card, and FIG. A circuit diagram, FIG. 3 is a specific circuit configuration for implementing a demodulator, and FIG. 4 is a voltage waveform diagram in the circuit configuration of FIG. 3. DETAILED DESCRIPTION OF THE INVENTION
裝 訂Binding
578362 A7578362 A7
578362 A7 B7 五、發明説明(5 ) ' 即不能偵測邊緣，因此差分器4與窗比較器5的上游連接， 由該差分器4放大濾波器3輸出信號的邊緣。 囪比車父器5接者能藉由參考能界定的門播值而谓測正或負 邊緣。接著在調變電路中提供數位信號處理裂置，但是該 信號處理裝置未在圖2顯示因為在此能使用習知的電路。 '戶3顯示一特多路配置的詳細圖形以實作根據本發明的解 調器。 如上所述，由電流鏡分出的電流值是依與讀寫裝置的距 離而定且會受到大的低頻變動。換言之個別資訊項的位準 變動極小，但是頻率遠高於干擾信號。為了去除緩慢且大 的電流變動，汲取出的電流1經由NMOS二極體D1而導 通，在此具有Μ 0 S二極體的平方根特性曲線的非線性電流/ 電壓轉換發生在二極體的導通電壓之上。在此點，另一非 線性元件如具有對數特性曲線的雙極二極體，也可使用。 輸入電流1的高動態因而映射到具有低動態的電壓信號。 惟動態壓縮的缺點是有用信號也被壓抑。與NM〇s二極體 D1並聯的第一電gC1及連接下游的RC低通濾波器，由電 阻R1及第二電容C2形成，幾乎將載波信號的重疊射頻信號 從電壓信號中器電全濾除。結果是能用與下游連接的差分 器4放大濾波信號的邊緣，及用窗比較器5評估它。從依此 取得的邊緣，一數位邏輯單元（圖中未詳細說明）決定稱為 SOF(訊框開始）及開始位元者，且季列地向fif〇傳送以下 資料位元，收到的資枓能接著以平行方式由cpu&FiF〇中 讀取。578362 A7 B7 V. Description of the invention (5) 'That is, the edge cannot be detected, so the difference 4 is connected upstream of the window comparator 5, and the edge of the output signal of the filter 3 is amplified by the difference 4. The receiver can be measured as a positive or negative edge by referring to a gateable value that can be defined. A digital signal processing split is then provided in the modulation circuit, but the signal processing device is not shown in Figure 2 because conventional circuits can be used here. 'House 3 displays a detailed diagram of a special multiplex configuration to implement a demodulator according to the present invention. As described above, the current value divided by the current mirror depends on the distance from the reader / writer and is subject to large low-frequency fluctuations. In other words, the level of individual information items changes very little, but the frequency is much higher than the interference signal. In order to remove the slow and large current fluctuations, the drawn current 1 is turned on through the NMOS diode D1. Here, the non-linear current / voltage conversion with the square root characteristic curve of the M 0 S diode occurs during the conduction of the diode. Above the voltage. At this point, another non-linear element such as a bipolar diode having a logarithmic characteristic curve may be used. The high dynamics of the input current 1 are thus mapped to voltage signals with low dynamics. The disadvantage of dynamic compression is that useful signals are also suppressed. The first electric gC1 connected in parallel with the NM0s diode D1 and the RC low-pass filter connected downstream are formed by a resistor R1 and a second capacitor C2, which almost completely filters the overlapping RF signal of the carrier signal from the voltage signal generator. except. As a result, the edge of the filtered signal can be amplified by the differential 4 connected downstream, and it can be evaluated by the window comparator 5. From the edge obtained in this way, a digital logic unit (not described in detail in the figure) decides to call the SOF (the start of the frame) and the start bit, and sends the following data bits to fif〇 quarterly, the received information枓 can then be read from cpu & FiF0 in parallel.
578362 A7 B7 五、發明説明（6 ) ~ ' 為了更詳細了解以下電路配置的精確功能，現在參考圖4 其中顯示電路中的數個特性電壓信號。 因此大的電流變動能映射到Ν Μ 0 S二極體D 1的導通電壓 上方區域中的極小電壓變動。運算放大器OP 1，電阻R2， R3及電容C3形成差分器4，電阻R2接在運算放大器ορι的 輸出與反相輸入之間，電阻R2的一端與反相輸入連接，也 經由第三電阻R3及串聯電容C3而接到參考電位。以pll的 迴圈濾波器為例，已證明R2/R3的比值約為1〇是較佳的。 依此由電容C3設定的時間常數能得到最大的可能調和， 但是信號仍然又到達靜止狀態，即使在位元中的待傳送最 大位元率之下（參考圖4的VSIG)。電壓中的緩慢變化是卡 在場中的移動維持幾乎未放大的結果。 此外又提供另一運算放大器ΟΡ2，其與其他電阻R4, R5, R6配合以便在濾波器3的輸出電壓附近產生一窗。在此與渡 波器3的輸出電壓相比，電壓VHIGH高於它一定義的電壓△ U ’而電壓VLOW則低於它一相同絕對值的電壓值 △U ° 電壓VSIG也接在濾波器3的輸出電壓之後，但是與調和 反應以改變電壓。當有正邊緣時，VSIG即超出VHIGH， 而且當有負邊緣時它即對應的降到VLOW之下。圖4定性的 顯示這些電壓的曲線。若乂51(3將窗留在VLOW與VHIGH 之間，這是由比較器Κ1及Κ2偵測，該等比較器比較差分器 4的輸出電壓VSIG與窗門檻值VHIGH及VLOW，且儲存在 下游正反器FF中。 -9 · 本紙張尺度適財B B家辟(CNS) A4規格(210X 297公釐)--- 578362 A7 B7 五、發明説明（7 ) 發生切換後’重置信號RES將正反器FF定位在輸出狀態 以便最先谓測負邊緣。在AS K 1 00%調變信號的例子中.， 這是場間隙’而在ASK 1 0%調變信號的例子中，這是 S OF(訊框開始）。接著在正反器ff的輸出m〇D中可使用解 調信號作進一步處理。 元件符號對照表 1 輸入信號 2 動態壓縮電路 3 濾波器 4 差分器 5 窗比較器 11 線圈 12 橋式整流器 13 電流鏡 14 解調器 15 並聯電壓調節器 16 平滑電容 17 數位電路 T1電流鏡的第一電晶體 T2電流鏡的第二電晶體 D1 NMOS 二極體 c 1第一電容 C2第二電容 C3第三電容 __ 10 - 本紙張尺歧財B B家^格(21G χ 297公爱) 578362 A7 B7 五、發明説明（8 R1，R2，R3，R4，R5，R6 電阻 OP1 差分器的運算放大器 OP2 運算放大器以產生窗 K1 第一比較器 K2 第二比較器 FF 正反器 VSIG 差分器的輸出信號 VHIGH 上窗門檻 VLOW 下窗門檻 RES 重置信號 MOD 輸出信號 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐)578362 A7 B7 V. Description of the invention (6) ~ 'In order to understand the precise function of the following circuit configuration in more detail, please refer to FIG. 4 which shows several characteristic voltage signals in the circuit. Therefore, large current fluctuations can be mapped to extremely small voltage fluctuations in the region above the ON voltage of the NM 0 S diode D1. The operational amplifier OP 1, the resistors R2, R3 and the capacitor C3 form a differentiator 4. The resistor R2 is connected between the output of the operational amplifier ορι and the inverting input. One end of the resistor R2 is connected to the inverting input, and is also connected via the third resistor R3 and The capacitor C3 is connected in series to a reference potential. Taking the loop filter of pll as an example, it has been proved that a ratio of R2 / R3 of about 10 is better. According to this, the time constant set by the capacitor C3 can get the maximum possible harmony, but the signal still reaches the stationary state, even under the maximum bit rate to be transmitted in the bit (refer to VSIG in Fig. 4). The slow change in voltage is a result of the movement of the stuck in the field maintained almost unamplified. In addition, another operational amplifier OP2 is provided, which cooperates with other resistors R4, R5, R6 to generate a window near the output voltage of the filter 3. Compared with the output voltage of the wave transformer 3, the voltage VHIGH is higher than a defined voltage △ U ′ and the voltage VLOW is lower than a voltage value of the same absolute value △ U ° The voltage VSIG is also connected to the filter 3 After outputting the voltage, but reacting with the harmonics to change the voltage. When there are positive edges, VSIG exceeds VHIGH, and when there are negative edges, it falls below VLOW correspondingly. Figure 4 shows the curves of these voltages qualitatively. If 乂 51 (3 leaves the window between VLOW and VHIGH, this is detected by the comparators K1 and K2, which compare the output voltage VSIG of the differential 4 with the window threshold values VHIGH and VLOW, and store it downstream FF in the flip-flop. -9 · The paper size is suitable for BB Jia Pi (CNS) A4 specification (210X 297 mm) --- 578362 A7 B7 V. Description of the invention (7) The reset signal RES will be switched The flip-flop FF is positioned in the output state so that it is called the negative edge first. In the example of AS K 100% modulation signal, this is the field gap 'and in the case of ASK 1 0% modulation signal, this is S OF (frame start). Then the demodulated signal can be used for further processing in the output m0D of the flip-flop. Component symbol comparison table 1 Input signal 2 Dynamic compression circuit 3 Filter 4 Differentializer 5 Window comparator 11 Coil 12 Bridge rectifier 13 Current mirror 14 Demodulator 15 Parallel voltage regulator 16 Smoothing capacitor 17 Digital circuit T1 First transistor of current mirror T2 Second transistor of current mirror D1 NMOS Diode c 1 First capacitor C2 second capacitor C3 third capacitor __ 10-This paper ruler Qi Cai BB home ^ grid (21G χ 297 male Love) 578362 A7 B7 V. Description of the invention (8 R1, R2, R3, R4, R5, R6 Resistor OP1 Differential Op Amp OP2 Op Amp to generate window K1 First Comparator K2 Second Comparator FF Flip-Flop VSIG Differentializer output signal VHIGH Upper window sill VLOW Lower window sill RES Reset signal MOD Output signal -11-This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm)