TW578300B - Trench type capacitor and its forming method - Google Patents

Abstract

The present invention provides a kind of trench type capacitor and its forming method. At first, a semiconductor substrate having trenches is provided. An etch stop layer is provided on the trench surface, and the etch stop layer can conduct electrically. Then, a hemi-spherical crystal growing layer and a doped glass layer are formed on the semiconductor substrate and the etch stop layer surface so as to form a sacrifice layer, which is extruded from the upper half portion of the doped glass layer, in the trench. The sacrifice layer is used as a mask to etch the doped glass layer and the hemi-spherical crystal growing layer till the etch stop layer surface is exposed. Then, the sacrifice layer is removed. After that, the doped glass layer is undergone with an annealing step so as to make the substrate form an ion driven region for use as the bottom electrode. The remaining doped glass layer and the etch stop layer exposing from the surface are stripped. At last, a capacitive dielectric layer is formed on the hemi-spherical crystal growing-layer, and an upper electrode layer is formed on the capacitive dielectric layer.

Description

578300 V. Description of the invention (l) Field of the invention The present invention relates to a method for forming a trench capacitor, and more particularly to a method for increasing the surface area of a trench by forming a semi-spherical crystal growth layer on the trench. Formation method. In the prior art, dynamic random memory, the following internal charge of the capacitor said that the soft error caused by the amplifier in the capacitor is read, that is, the capacitance is more south. Therefore, the important research class is the semi-conductor of memory integration (memory ce is fast. In traditional memory cells, the leakage current of the memory cell must be stored in the electricity storage, you must also consider such as: increase Capacitive access memory (referred to as DRA M between Dynamic Random Access) stores data in the state of memory cell (mem 0 ryce 1 1), which means that the more electric charges it can store (the larger the capacitance value), Then, the situation affected by noise when reading the breeding material (such as alpha particles (Soft Errors), etc.) can be greatly reduced. The larger the value is, the more stable the data stored in the memory will increase the capacitance of the capacitor The value is the industry's longest (^ integrated Circuit (1C)) chip when manufacturing high-body components, we must consider how to reduce the size and power consumption of each memory single 1), so that its operating speed increases in the plane transistor design In order to obtain a minimum size, the gate length of the transistor must be shortened as much as possible to reduce the area. However, this will make it extremely unacceptable to reduce the voltage on the bit line correspondingly, thereby reducing the charge. Therefore, shortening the lateral length of the gate is the same as how to make a capacitor with a large capacitance, such as the area, reducing the effective dielectric thickness between capacitor plates, etc.

υ / ojyjyj V. Description of the invention (2) D: M) Records of the system: body (for example: dynamic random access memory, stacked capacitors, V type, capacitor formation technology ... =: 果 Channel iUeeP —Capacitor. The second channel in the deep channel is formed in the base to form a deep channel and accumulate. &Amp; As an electrical-storage area, it will not occupy the extra area of the memory cell. ^ U2: Figure la is a schematic diagram showing a deep trench of a conventional DRAM. The figure shows a straight line not shown along the tangent line BB of Figure 1a = reference electrode conductors 4 The system is connected to the -moving region 2. The other is that the ice bean and the source / drain diffusion region are made in the phase L of the active region 2. The ditch 12 series are respectively arranged on the adjacent main dotted line 38 and are connected as follows. And the dotted line 8 refers to: a memory cell area, and a diffusion area. Wang 'is used to electrically connect the bit line 6 to the source / drain setting. For example, its surface is above and below, and the deep buried layer 20 is formed in the P-type well layer M base iO, and the P-type well layer 22 is cut into the buried layer until the area below Shixi 12 = ^ Enlarged Layer 14 is formed around the deep trench trench electrical layer: it is the electrode of the deep trench trench capacitor; it is used as the deep trench trench capacitor: = side wall and bottom of the square wheel, it is effective to cover it with 夕, 、 Be, one brother and one polycrystalline silicon layer 18 is filled with wood: the area under the trench 12 is used as a storage node (storagen〇de) for deep trench capacitors. And,-collar type u〇iiw oxide layer ml set 6 pages 0593-9104twf (nl); 91071tw; clai re.ptd 578300

A second polycrystalline silicon layer 26 is filled on the sidewalls of the area above the deep trench 12, a region above the deep trench 12 and a third polysilicon layer 28 is disposed on the deep trench 12 The top is used as a buried strap (BS) electrically connecting the deep trench capacitor to the source / drain diffusion region 34. In addition, a shallow trench isolation (STI) structure 30 is provided between adjacent deep trenches 12, and a contact plug 38 is provided between two predetermined gate conductors 4, which can The element line 6 is electrically connected to the source / drain diffusion region. 34 The manufacturing steps of traditional deep trench capacitors are quite cumbersome. U.S. Pat. No. 4, 3 5 3, 086 has deep trench capacitors. Zhilong has a detailed description. y However, with the continuous reduction of the DR AM process, the diameter of the deep channel trench 2 has also been reduced, which affects the circumferential area of the deep channel trench 12, thereby reducing the surface area of the electrode of the deep channel trench capacitor, which is difficult to maintain. Sufficient electrical capacity. SUMMARY OF THE INVENTION In view of this, an object of the present invention is to provide a method for forming a trench capacitor 'on a sidewall of a trench to form a hemispherical crystal growth layer to increase the sidewall area of the trench capacitor. According to the above, the present invention provides a method for forming a trench capacitor, including the following steps: providing a semiconductor substrate, and a cover layer on the surface of the conductor substrate, wherein the semiconductor substrate has a trench; on the surface of the trench An etch stop layer is formed on the upper compliance, and the etched earth layer can be electrically conducted; on the surface of the semiconductor substrate and the etch stop layer, sequentially conformally formed-a hemispherical crystal growth layer and a -doped vitreous layer; in the trench Trough forming a sacrifice

V. Description of the invention (4) layer, lower layer of sacrificial layer; removing sacrificial layer by sacrificial layer layer and hemisphere; forming a method of exposing the surface dielectric root, surface conduction on the surface; the spherical crystal sacrificial layer is named The surface is doped with semiconducting glass. According to the above method, the layer on the surface; the remaining layer on the ion-driven surface; and according to the above, including the doped glass entrance region below the top of the trench as an etch mask crystal growth layer as an undercut stop layer; for capacitor dielectric purposes, The steps of this step are as follows: the exposed grooves are sequentially carved to the vines and the engraved layers to be tempered; one is removed from the hemispherical crystal layer to form a bright one, and then a cover layer is formed. The substrate and the trench layer and the top of a doped trench are exposed by doping to remove the sacrificial layer to form an ion on the hemispherical crystal to form an upper surface that conforms to the growth of the semiconductor below the trench etching mask; the bulk substrate glass layer; According to the above, the electrical layer includes the following steps: forming a surface glass layer patterned for half of the semiconductor worms to stop the groove; a doped glass layer; a doped growth region electrode; a conductive substrate stop layer; and a broken glass to exposed glass As a surface step on the layer and the stop layer in the upper half of the upper trench, the remaining electrode-doped doped body is grown on the upper electrode layer. A trench-type electrical substrate, the semiconductor has a doped surface with a trench doped; the conductor substrate breaks the glass layer and the surface of the formed body forming an electrical valley, and the trench 'money stop layer is electrically conductive Form half of the trenches in order to form a sacrificial layer in accordance with the order; use a sacrificial body to grow the layer to fire the step to remove the residual to form a capacitive dielectric layer; except for exposing the surface, a hemispherical glass layer is formed on the top half of the layer Go back to the lower electrode; go to heading 2. The present invention also provides _ edge supply—semiconductor with a mask layer and a | right photoresist layer Λ uranium book /, horse etching mask, according to the formation of a trench capacitor substrate, Patterned photoresist sequential etching mask layer and semiconductor for surface opening of semiconductor substrate

0593-9104twf (nl); 91071tw; claire.ptd $ 8 page 5. Description of the invention (5) ^, bottom to form-trench; in the trench stop layer, the etch stop layer can be electrically conformable ^ on the surface to form a compliance Sequentially conformable shapes on the etched surface = exposed glass layers on semiconductor substrates and trenches; hemispherical crystal growth layers and a doped groove on the arsenic-doped glass layer; the sacrificial layer is returned to 22 t-sacrificial Layer, and the sacrificial layer fills the trench with a first predetermined height, and the sacrificial layer is lower than the top of the trench and has an etching mask, and the surface of the doped glass layer is oblique; the etching is exposed by the sacrificial layer. Stop the doped doped glass breaking layer and the hemispherical crystal growth layer to reach the second opening: A 2 surface; remove the sacrificial layer; perform θ 2 abundance compliance on the semiconductor substrate to form a first oxide layer, and The semiconductor is sequentially removed in the second step so that the semiconductor substrate forms an ion drive-in region; a layer; the semiconductor layer is doped with a glass layer and an etch stop layer is exposed on the semiconductor surface; conforming to the surface of the semiconductor and the trench Forming a capacitive dielectric pair to conduct lightning show 1 > forming a conductive layer on the soil bottom, The conductive layer fills the trench; the second step is to carry out the money-back engraving step until the conductive layer is lower than the top of the trench and has one; the capacitance and the surface of the capacitor dielectric layer are exposed; the exposed surface of the oxide layer is removed, and the semiconductor The compliance of the substrate and the trench forms a second line of "tropical tempering step, and forms a second oxide layer into the wall-collar-type dielectric = the surface of the electrical layer" so as to achieve the above purpose on the side of the trench ^ 1. The method of the invention, ^ & The present invention further provides a formation surface of a trench capacitor ::: Step: Provide-semiconductor substrate, the surface layer of the semiconductor substrate; Figure Chong = a cover layer and an opening The patterned photoresist substrate base 2 is formed as a mask, and the mask layer and semiconducting grooves are sequentially carved in order to form a worm engraved on the surface of the groove. Page 9 〇593.9104twf (nl); 9107ltw; claire.ptd V. Description of the invention (6) Out: The electrically conductive surface of the stopper layer is sequentially compliant to form 玟: semiconductor substrate and trench exposed layer, doped slope layer The above surface-shaped crystal growth layer and one doping: two etch back step sacrificing the sacrificial layer ', The sacrificial layer fills the trench with a predetermined height, and the + λ sacrificial layer is lower than the top of the trench and is doped for 1 minute; the surface of the glass layer; up to the surface of the sacrificial layer; removing the sacrificial layer The conformal formation on the crystal growth layer-the surface of the cut body substrate and the second opening π is abruptly produced, and the semiconductor substrate is tempered, and the bottom is removed in order. Dielectric; Yu Semiconductor; 4 length: j: the upper conformal layer fills the trench; a ¥¥ ㉟ is formed on the conductive reed and the second soil & and the conductive tip has — 帛: both j: ding Step S: The conductive layer is lower than the trench to guide the return of lightning, and the surface of the capacitor dielectric layer is exposed. I_g: A mask is used to etch the exposed capacitor dielectric layer and hemisphere to expose the surface. Stop the surface of the layer; remove the exposed surface gas; τ layer 〃, and form a second year on the semiconductor substrate and trench compliance / Tempering the second oxide layer, and advance the second oxide layer = Directional money is engraved until the surface of the conductive layer is exposed to form a collar-type dielectric on the sidewall of the trench Floor. Heart side Another object of the present invention is to provide a trench capacitor having a hemispherical crystal growth layer. According to the above object, the present invention provides a trench capacitor, including: a semiconductor substrate, the semiconductor substrate is formed with a trench; an etch stop layer is formed on the sidewall of the lower portion of the trench, and has a predetermined height; , 0593-9104twf (nl); 91071tw; claire.ptd Page 10 578300

V. Description of the invention (7) Where the etch stop property is formed by money carved on a hemispherical crystal with a degree of orientation and a bottom layer of 0 can be electrically conductive; the surface of the stop layer is grown on the surface of the growth layer; and the semi-spherical crystal of the lower electrode is a capacitor An upper electrode of the electric layer is formed in the growth layer outside the trench, and conformance is formed in the trench. The semiconductor substrate on the side is for easy understanding of the present invention, and a detailed description is given below. The heart, day, J, pride, and advantages can better explain the best embodiment, and in conjunction with the drawings to make the ancient sheep implementation: For the first embodiment, please refer to Figures 2a-2j. — 2J is a schematic diagram showing the formation method of the cover seed bucket capacitor according to the present invention, which is a schematic diagram of an example of the J% wind in the fog-groove electric closing day. With reference to the picture of the younger brother 2a, the prime minister is sitting on the board. # —Η 秘 曾 —πλι Since there is no, neodymium is supplied + conductor substrate 201, and the semiconductor substrate 201 is sequentially formed with right ^ ^ JS π π 77 77 ^ y The cover layer 202 and a patterned photoresist layer 203 having an opening 204. Among them, θ /, T ', V-substrate substrate 2 0 1 is, for example, a silicon-based mask layer 2 2, for example, a nitride layer. -Please refer to FIG. 2b, using the patterned photoresist layer 203 as an etching mask, and sequentially etching the mask layer 202 and the semiconductor substrate 201 to form a trench 205; then, patterning The photoresist layer 203 is removed. 'Please refer to Figure 2c. A thin lining layer is formed on the sidewall of the trench 205 as an etch stop layer. The thickness is less than 8 A, preferably 8 ^'. Conduction; for example, nitriding the semiconductor substrate 201 to form an etch stop layer 206 under the surrounding of ammonia gas.

〇593-9l04twf (nl); 91071tw; clai re.ptd 578300

* Please refer to Figure 2d of the tea test, in order to form a semi-spherical crystal growth (Henn Sp% rical, HSG) layer 2 0 7 in compliance with the surface of the mask layer 2 02 and the worm-cut stop layer 2 06. And a doped glass layer 208, the thickness of the doped glass is greater than that of the hemispherical crystal growth layer 207, and will cover the hemispherical crystal growth layer 207 ^ " '/ 疋 王. Among them, the hemispherical crystal growth layer 207 is, for example, a hafnium-spherical silicon crystal; the doped glass layer 208 is, for example, an arsenic-doped glass layer (^ seruc Silicate Glass, ASG). Please refer to FIG. 2e. Next, a sacrificial layer such as a photoresist layer or an organic material layer is formed on the semiconductor substrate 201, and the photoresist layer will form the trench 2 05.

Fill it; and etch back the photoresist layer to make the photoresist layer 209 lower than the top of the trench 205 to expose the doped glass 208 in the upper half of the trench 205. Please refer to FIG. 2f, with the photoresist layer 209 as an etching mask, and sequentially etch the doped glass layer 208 and the hemispherical crystal growth layer 207 on the exposed surface to expose the worm cut τ stop layer 2 0. To the surface of 6 'to form a doped glass layer 20a and a hemispherical crystal growth layer 207a. The etching method is isotropic etching, such as wet etching or dry etching with ammonia hydroxide (Νί ^ ΟΗ). Therefore, the height of the doped glass layer 208a and the hemispherical crystal growth layer 207a is usually slightly Below the photoresist layer 209. Referring to FIG. 2g, after the photoresist layer 209 is removed, an oxide layer 2 1 0 is formed on the surface of the semiconductor substrate 2 01 and the trench 2 05 in conformity, and the oxide layer 2 1 0 is, for example, oxalic acid A tetraethyl oxide layer (τ etra E thy 1 SiO Si icate, TEOS) is used as a sacrificial layer, and can be used as a barrier layer during thermal ox i da ti on implantation or tempering, can

578300 V. Description of the invention (9) Protect the semiconductor substrate 201 from being damaged in the subsequent tempering step, and also prevent the ions in the doped glass layer 20 8 from being driven to unnecessary positions. / Then 'tempering the semiconductor substrate 205 at a temperature of 650 to 1000 degrees Celsius to form an ion driving region 21 1 in the semiconductor substrate 2 〇j outside the trench 205, which is used as The lower electrode of the capacitor; then, the oxide layer 2 10 and the doped glass layer 208 a are removed to expose the hemispherical crystal growth layer 207 a, and the etch stop layer 206 on the exposed surface is removed and left The etch stop layer 206 & covered by the hemispherical crystal growth layer 207 & is shown in FIG. 211. / Please refer to FIG. 2i. A capacitive dielectric layer 212 is conformably formed on the surface of the semiconductor substrate 201 and the groove 2 0 5 having a hemispherical crystal growth layer 2 0 7 a, for example, an oxynitride layer ( N0), which can protect the semiconductor substrate 20 from being damaged during the subsequent etch-back step of the conductive layer; then, a conductive layer is formed on the semiconductor substrate 201, and the conductive layer will fill the trench 2 05 Then, the conductive layer is etched back to form a conductive layer 213 of a predetermined height in the trench 205. ^ Electricity? The height of 213 is higher than the height of the hemispherical crystal growth layer 207a 'and therefore higher than the height of the lower electrode 2111. The conductive layer 2} 3 is, for example, a polycrystalline silicon layer, and is used as an electrode on a capacitor. Referring to FIG. 2j, the conductive dielectric layer 21 3 is used as a cover, and the capacitive dielectric layer 212 on the exposed surface is removed to form a capacitive dielectric layer 212a; then, the surfaces of the body substrate 201 and the trench 2 05 are conformed. An oxide layer is formed, and the oxide layer is subjected to a thermal oxidation or tempering step so that the oxide layer extends toward the half-bottom 201, which can achieve a larger area of collision resistance.

Page 13 578300 V. Description of the invention (ίο) Jinda non-temporal surname is engraved until the surface of the conductive layer 213 is exposed and formed on the side wall of the groove 205-collar-type dielectric layer 214 for protection The surface of the semiconductor substrate 201, which is rattan above 2,0, and the collar-type dielectric / 214, the lower electrode 2U, the remaining stop layer ma, and a hemisphere; there is a gap between 20 7a. ^ Second embodiment-Figures 3a-3j of Figure 2a, Figures 3a-3j are schematic views showing another embodiment of the method for forming trench capacitors of the present invention. For the θ formula, please refer to Figure 3a, 'First', a semiconductor substrate is provided. A body substrate 301 is sequentially formed with a mask layer 302 and a slit = patterned photoresist layer 303 °. The semiconductor substrate is thin. 1 is, for example, a broken substrate. The mask layer 3 0 2 is, for example, a nitride layer. Please refer to Figure 3b, using the patterned photoresist layer as a mask for the engraved mask. The engraved mask layer 3G2 and the semiconductor substrate are formed; after forming the trench 3 () 5, the patterned photoresist layer 3 is formed. 〇3Removed. Please refer to Figure 3c. A thin liner layer conformably formed as an etch stop layer on the sidewall of the trench 305, with a thickness of about 8 A or less, preferably ^ and the money stop layer can be electrically conducted; for example It is surrounded by ammonia gas ", and the semiconductor substrate 301 is nitrided to form a silver-etched stop layer 3006, and the intermediate layer" I "is a nitrided layer. For example, please refer to Section 3 ( Figure 1 'Hemi Spericai Gram Growth (HSG) layer 3 07 and a doped glass 8 layer 308 are formed on the surface of the mask layer 302 and the coin-cut stop layer 306 in order. The thickness is thicker than the hemispherical crystal growth layer 307, and will be = 0593-9104twf (nl); 91071tw; clai re.ptd page 14 578300

V. Description of the invention (12) Enter = Ξ = step I ′ to form a f-drive area 311 in the semiconductor substrate 3Q1 outside the trench 3Q5 to serve as the lower electrode of the capacitor. The glass sound 3 ^ ί ^ 3h picture ′ sequentially the oxide layer 310 and unreacted doped glass = said; ί: and exposed hemispherical crystal growth layer 307. Next, on the surface of the semi-layer, the conformal formation of the thunder layer 307-the capacitive dielectric layer and the beautiful electrical layer 312 are, for example, an oxynitride layer (N0); and then, on the second semiconductor, a V conductive layer., The conductive layer will fill up the trench, and the 2 pairs :: layer will be etched back so that == electricity. The height of the conductive layer 3U is higher than that of the ^ degree electrode of the power-down pair. The ^ electric layer 313 is, for example, a polycrystalline layer, and is used as an electric capacitor on the capacitor. The solar growth layer 3 0 7 forms a thunderbolt electric layer 312 a and a hemispherical crystal growth layer 3 07 a. / 成 电 谷 介 Η H, removes the etch stop layer 3 6 from the exposed surface to form an etch s3〇6a, and then on the semiconductor substrate 301 and the trench 305 table; Responsiveness: forming-an oxide layer, i thermal oxidation of the oxide layer or = step, so that the oxide layer toward the semiconductor substrate 3 〇1 ^ barrier effect; then, the surface of the oxide layer reaches a larger area of the electrical layer 313, and the surface of the trench 2 = 2 = = out of the surface of the lead 3 0. Spreading the trench over 3 0 5 Semiconductor substrate The method for forming a trench capacitor provided by the present invention, (mainly additionally forming an electrically conductive layer with a thickness V equivalent on the sidewall of the trench ": page 5993-9104twf (nl); 91071tw; claire. ptd 578300 V. Description of the invention (13) Etching the stop layer to effectively simplify the process steps of forming a trench capacitor; and by forming a hemispherical shape The body is grown to effectively increase the capacitance area without increasing the volume of the capacitor without affecting the accumulation of semiconductor capacitors. Although the present invention has been disclosed above in a preferred embodiment, it is not intended to limit the present invention. Any familiarity Those skilled in the art can make changes and decorations without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

0593-9104twf (nl); 91071tw; claire.ptd Page 17 578300 Brief description of the drawings Figure 1a shows the arrangement of the deep canals of the conventional DR AM. Figure 1b is a schematic cross-sectional view of the deep trench shown along the tangent line B-B in Figure 1a. Figures 2a-2j are schematic views showing an embodiment of a method for forming a trench capacitor of the present invention. Figures 3a-: 3j are schematic diagrams showing another embodiment of a method for forming a trench capacitor according to the present invention. Explanation of symbols: 2 ~ active area; 4 ~ gate conductor, 6 ~ bit line; 8 ~ memory cell area; 10 ~ chopping base; 1 ~ 2 ~ deep trench; 1 ~ 4 ~ N-type diffusion layer; 1 ~ 6 ~ Dielectric layer; 18 ~ first polycrystalline silicon layer; 20 ~ N type buried layer; 22 ~ P type well layer; 2 ~ 4 collar oxide layer; 26 ~ second polycrystalline silicon layer; 2 8 ~ Third polycrystalline silicon layer; 30 ~ shallow trench isolation structure; 34 ~ source / drain diffusion region;

0593-9104twf (nl); 91071tw; clai re.ptd page 18 578300 Schematic description 3 8 ~ contact plug; 201, 301 ~ semiconductor substrate; 2 0 2, 3 0 2 ~ cover layer; 2 0 3 , 3 0 3 ~ patterned photoresist layer; 2 0 4, 3 0 4 ~ openings; 2 0 5, 3 0 5 ~ grooves; 206, 206a, 306, 306a ~ I insect-cut stop layer; 20 7, 2 0 7a, 3 0 7, 3 0 7a ~ hemispherical crystal growth layer; 208, 208a, 308, 308a ~ doped glass layer; 209, 309 ~ photoresist layer; 2 1 0, 3 1 0 ~ oxide layer; 211 311 ~ ion driving region; 21 2, 21 2a, 312, 312a ~ capacitor dielectric layer; 21 3, 31 3 ~ conductive layer; 214, 314 ~ collar dielectric layer.

0593-9104twf (nl); 91071tw; clai re.ptd page 19

Claims (1)

Sixth, the scope of application for patents is as follows: a method for forming a trench capacitor, including the following: a conductive substrate, the semiconductor substrate table: wherein the semiconductor substrate has a trench, and a cover is stopped: on the surface of the groove Compliance formation-etch stop layer ... reeling this layer can be electrically conductive; etched on the semiconductor substrate and the button = crystal growth layer and a heterogeneous sequence of the substrate to expose the glass layer lower than the Take the sacrificial layer as the etching mask at the top of the trench; the broken glass layer and the hemispherical crystal grow up to the surface of the upper half of the trench; 3 to remove the sacrificial layer from the chrome stop layer; An ion-driven region of the doped glass layer is used as a lower electrode; ν step is performed to form the semiconductor substrate to remove the remaining doped glass-breaking layer and layer; σ out of the surface of the etching stops at the hemispherical crystal formation / A capacitor dielectric layer is formed on the capacitor dielectric layer, and 2. An electrode layer is applied as in the case of applying for a patent. Method, which further includes a step of forming a trench capacitor on the trench sample. 9 + ^ Step of forming a collar-type dielectric layer 3 · As in the method of applying for a patent, where the collar-type dielectric layer is an oxide-grounded trench capacitor, page 20593-9104twf (nl) 91071tw; claire.ptd 6. Scope of patent application 4 · If you apply for the first item of patent scope, 'The far-screen curtain layer is a nitrided layer. Meaning of the formation of trench capacitors 5. As claimed in item 1 of the patent scope, where the # 刻 STOP 层 4nitrided; the formation of the trench-type capacitors I. 6 as in the scope of the patent application item',. The formation method of the trench capacitor described in the thickness of the etch stop layer 7 · As claimed in the first item of the patent application scope, / 18, A. The formation method of the trench capacitor of the hemispherical crystal growth layer · As in the scope of application of the patent application No. j, and, the bull spherical silicon crystal growth layer. Wherein, the doped glass-breaking layer is a method for forming a trench capacitor with a doped element. Please refer to item 1 of the patent scope, wherein the upper electrode is a polycrystalline silicon layer. Forming method of a trench capacitor 1 10. As described in the patent application Fanfei Chu 1 TE wherein the capacitor dielectric layer is a forming method of a nitrogen-oxygen trench capacitor 11. A formation of a trench capacitor θ. Provide-a semiconductor substrate, the engraving step includes the following steps: a layer, wherein the semiconductor substrate has a mask on the surface of the substrate, an etch stop layer is formed, and the surface of the trench is etched along the surface The semiconductor substrate and the trench d :; the layer can be electrically conductive; the hemispherical crystal growth layer and a doped surface are formed sequentially and sequentially-forming a sacrificial residence for the trench, exposing the upper half of the doped glass layer ' The sacrificial layer is below the top of the trench and the sacrificial layer is used to engrav the II hemispherical crystal growth layer: J stop etching the doped glass layer to expose the method method method method method law 0953-91041wf (nl) 9107ltw; clai re.ptd page 21 578300 6. Apply for a patent to remove the sacrificial layer; Temper the tempered doped glass layer to make the semiconductor substrate an ion drive region as the lower electrode; The doped glass layer, forming / capacitive dielectric layer on the hemispherical crystal growth layer; forming an upper electrode on the valley dielectric layer; and removing the etch stop layer on the surface of chromium. 1 2 _ The method for forming a trench capacitor according to item 11 of the scope of patent application, further comprising a step of forming a collar on the upper half of the trench. 1 of the electrical layer · The method for forming a trench capacitor as described in item 12 of the scope of patent application, wherein the collar-type dielectric layer is an oxide layer. 14. The method of forming a trench capacitor according to item n of the scope of the patent application, wherein the mask layer is a nitride layer. 15. The method for forming a trench capacitor according to item 11 of the scope of the patent application, wherein the thickness of the etch stop layer is less than 1 8 A. The method for forming a trench capacitor according to item 11 of the Fang, Guang · Λ VI patent scope, wherein the etch stop layer is a nitride layer. Method 1, 7 The formation of the trench capacitor as described in item 11 of the Zhongshen ^ special f range 丨 / ϋ Λ crystal growth layer is a hemispherical second crystal growth layer. The method for forming a trench capacitor according to item 11 above, wherein the erbium-doped glass layer is an arsenic-doped silica glass erbium layer. 19 · The method according to item 丨 丨 in the scope of patent application, wherein the upper electrode is a polycrystalline silicon layer. The formation of the Japanese-style electric valley 0593-9104twf (nl); 91071tw; claire.ptd Page 22 ^ / OD \ JV I _ VI. Patent application scope 2 〇 If the patent application scope No.,, and method, the capacitor medium Formation of Trench Capacitors by Electroacoustics 21. The formation of a variety of trench capacitors provides a semiconductor substrate, which includes the following steps: a mask layer and an opening with an opening formed in order to form the pattern # 阳 Ｍ & Orientation first barrier layer; the semiconductor substrate to form a trench; the mask sequentially etches the mask layer and conforms to the stop layer's electrical conductivity on the surface of the trench; ^ > into one An etch stop layer, which is formed on the semiconductor substrate and a semi-spherical crystal growth layer formed on the semiconductor substrate and a semi-spherical surface and conforms to the arsenic-doped glass layer to form a $ heterotic glass layer; A sacrificial layer, and the sacrificial layer fills the etched back end of the sacrificial layer and has a first predetermined height, where the sacrificial layer is lower than the top of the trench, the sacrificial layer is used as an etching screen, and the doped layer is exposed. The surface of the frosted glass layer; hemispherical crystal growth layer to Lin After the sequence is finished, the doped glass layer and the sacrificial layer are removed; the surface of the μ-etch stop layer is stopped; ^ is formed on the semiconductor substrate and the second first oxide layer and conforms to the semiconductor sweat surface to form an integrated substrate Forming an ion drive-in area and performing a tempering step to sequentially remove the first oxide from the semiconductor and the etch stop layer; replace the broken glass layer and expose the surface of the semiconductor substrate and the trench A capacitor is formed conformably on the surface of the trench. Page 23 0593-9104twf (nl); 91071tw; claire.ptd 578300 VI. Patent application dielectric layer; A conductive layer is formed on the semiconductor substrate and the conductive layer is filled The groove is repeatedly engraved to the conductive layer until the conductive layer is lower than the top of the trench and has a second predetermined height, and the surface of the capacitor dielectric layer is exposed; the capacitor dielectric layer on the exposed surface is removed ; And a second oxide layer is formed on the semiconductor substrate and the trench compliance, a tempering step is performed on the second oxide layer, and the second oxide layer is anisotropically etched to expose the conductive layer Until the surface to form a dielectric collar on the side walls of the trenches. 2 2. The method for forming a trench capacitor according to item 21 of the scope of patent application, wherein the I-etching stop layer is a nitride layer. 2 3. The method for forming a trench capacitor according to item 21 of the scope of the patent application, wherein the thickness of the etch stop layer is less than 18 A. 24. The method for forming a trench capacitor as described in item 23 of the scope of the patent application, wherein the thickness of the I etch stop layer is 8 A. 2 5. The method for forming a trench capacitor according to item 21 of the patent application, wherein the sacrificial layer is a photoresist layer or an organic material layer. 26. The method for forming a trench capacitor according to item 21 of the scope of patent application, wherein the first oxide layer is a tetraethyl silicate oxide layer. 2 7. The method for forming a trench capacitor according to item 21 of the patent application, wherein the capacitor dielectric layer is an oxynitride layer. 28. The method for forming a trench capacitor according to item 21 of the scope of the patent application, wherein the hemispherical crystal growth layer is a hemispherical silicon crystal growth layer. 0593-9104twf (nl); 91071tw; clai re.ptd page 24. Patent application scope formation 29. The method of patent application scope No. 21, wherein the doped glass layer is 30. of the trench capacitor described in the item. The scope of patent application is the second Er Kun silicon glass layer. Method, wherein the conductive layer is in the shape of a trench capacitor described in a polycrystalline silicon layer. The method, wherein the second predetermined high-yield formation; the formation of the trench capacitor described in ^ 32. As in the patent application; a predetermined height. A method in which the anisotropic etching is described as the shape of a trench capacitor. Reactive Ion Endurance or Plasma # 33 ·-A method for forming a trench capacitor provides a semiconductor substrate. The semiconductor includes the following steps: a cover layer and a door surface on the substrate surface. Sequentially formed, opening patterned photoresist layer; edge-patterned photoresist layer is used as an etching mask and the semiconductor substrate to form a trench; ^ μ * etch the mask and stop: J slot t surface Compliance formation-etch stop, the etch stop layer can be electrically conducted; "& / one: m: sequential compliance formation on the substrate and the exposed surface of the trench = spherical crystal growth layer and a doped Miscellaneous glass layer; groove; / 1 & shape of glass layer & sacrifice, i the sacrificial layer is filled with the sacrificial layer and the money is etched to the end and has a first g ~~ D D, the percentage of low increase is / again τ days only ^ ^, and back again, the surface hemisphere of the doped glass layer is exposed] :: etch mask 'etch the doped glass layer to expose the Niuchen-shaped day The surface of the solar growth layer; 0593-9104twf (nl); 91071tw; clai re.ptd 25th stomach ^ / OJUU :, the scope of the patent application to remove the sacrificial layer; the first oxygen :: the conformation of the conductor substrate and the surface of the second opening °-body Tempering the semiconductor substrate to form an ion drive-in area at the bottom of the semi-conducting lane; removing the first oxide layer and the doped slope layer; electrical layer; ~ hemispherical crystal growth layer Compliance formation on the surface-A conductive layer is formed on the capacitor dielectric half body substrate, and the conductive layer fills the second and fourth conductive layers, and the back-etching step is performed until the conductive layer is lower than the trench top, ^ Has the first predetermined degree 'and exposes the surface of the capacitor dielectric layer; f The ^ electric layer is an engraved mask, and the capacitor dielectric layer and Uhai hemispherical crystal growth layer exposed on the surface are etched to expose the neodymium Until the surface of the stop layer is etched; removing the etch stop layer on the exposed surface; and forming a second oxide layer on the semiconductor substrate and the trench conformance, performing a tempering step on the second oxide layer, and The oxide layer is anisotropically etched until the surface of the conductive layer is exposed So far, to form a dielectric collar on the side walls of the trenches. 34. The method for forming a trench capacitor according to item 33 of the application, wherein the etch stop layer is a nitride layer. 35. The method for forming a trench capacitor according to item 33 of the scope of the patent application, wherein the thickness of the etch stop layer is less than 18 A. 3 6 如 申 致 直 士 丨 #, + ,: Formation of trench capacitors • Ge Jiaming's profit-seeking target method No. 35, where the thickness of the etch stop layer is 8 A 0593-9104twf (nl); 91071tw; claire.ptd 578300 6. Application Patent Range 37 • The method for forming a trench and slot capacitor as described in item 33 of the patent scope of Shenqing ', wherein the first oxide layer is a tetraethyl silicate oxide layer. 38. The method for forming a trench capacitor as described in item 33 of the patent application scope, wherein the capacitor dielectric layer is an oxynitride layer. 39. The method for forming a trench capacitor according to item 33 of the application, wherein the hemispherical crystal growth layer is a hemispherical silicon crystal growth layer. 40. The method for forming a trench capacitor according to item 33 of the scope of the patent application, wherein the doped glass layer is an arsenic-doped silica glass layer. 41. The method for forming a trench capacitor according to item 33 of the patent application scope, wherein the conductive layer is a polycrystalline silicon layer. 42. The method for forming a trench capacitor according to item 33 of the scope of the patent application, wherein the second predetermined height is higher than the first predetermined height. 43. The method for forming a trench capacitor according to item 33 in the scope of the patent application, wherein the anisotropic etching is reactive ion etching or plasma etching. 44. A trench capacitor, comprising: a semiconductor substrate formed with a trench; an etching stop layer formed on a sidewall of a lower portion of the trench with a predetermined height, wherein the etch stop layer Electrically conductive; Hemispherical crystal growth layer 'compliance is formed on the surface of the etch stop layer; An valley dielectric layer' compliance is formed on the surface of the hemispherical crystal growth layer; The upper electrode 'is formed on the groove The groove has the predetermined height; and 0593-9104twf (nl); 91071tw; claire.ptd page 27 578300 6. Scope of patent application The lower electrode is formed on the semiconductor substrate outside the trench. 45. The trench capacitor according to item 44 of the patent application scope, wherein the etch stop layer is a nitride layer. 46. The method for forming a trench capacitor according to item 44 of the scope of the patent application, wherein the thickness of the etch stop layer is less than 18 A. 47. The method for forming a trench capacitor according to item 46 of the scope of patent application, wherein the thickness of the etch stop layer is 8 A. 48. The trench capacitor according to item 44 of the scope of patent application, wherein the hemispherical crystal growth layer is a hemispherical silicon crystal growth layer. 49. The trench capacitor according to item 44 of the scope of patent application, wherein the upper electrode is a polycrystalline silicon layer. 50. The trench capacitor according to item 44 of the scope of patent application, wherein the lower electrode is an ion drive-in region. 51. The trench capacitor according to item 50 of the scope of patent application, wherein the ion driving region is a europium ion driving region. 5 2. The trench capacitor according to item 44 of the patent application scope, wherein the upper portion of the trench further includes a collar-type dielectric layer. 53. The trench capacitor according to item 52 of the scope of patent application, wherein the collar-type dielectric layer is an oxide layer. 0593-9104twf (nl); 91071tw; clai re.ptd page 28