TW578272B - Manufacturing method of bottle shaped trench - Google Patents
Manufacturing method of bottle shaped trench Download PDFInfo
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- TW578272B TW578272B TW091135852A TW91135852A TW578272B TW 578272 B TW578272 B TW 578272B TW 091135852 A TW091135852 A TW 091135852A TW 91135852 A TW91135852 A TW 91135852A TW 578272 B TW578272 B TW 578272B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 239000004065 semiconductor Substances 0.000 claims abstract description 64
- 238000005530 etching Methods 0.000 claims abstract description 29
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 42
- 229920002120 photoresistant polymer Polymers 0.000 claims description 39
- 150000004767 nitrides Chemical group 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 7
- 239000000908 ammonium hydroxide Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000005388 borosilicate glass Substances 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 238000005121 nitriding Methods 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 4
- 239000004020 conductor Substances 0.000 claims 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims 2
- 241001674048 Phthiraptera Species 0.000 claims 2
- 241001465754 Metazoa Species 0.000 claims 1
- 230000032798 delamination Effects 0.000 claims 1
- 238000010899 nucleation Methods 0.000 claims 1
- 239000010458 rotten stone Substances 0.000 claims 1
- 238000004528 spin coating Methods 0.000 claims 1
- 239000000243 solution Substances 0.000 description 12
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 8
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011259 mixed solution Substances 0.000 description 4
- 239000004575 stone Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 239000012634 fragment Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 241000282326 Felis catus Species 0.000 description 1
- OYHQOLUKZRVURQ-HZJYTTRNSA-N Linoleic acid Chemical compound CCCCC\C=C/C\C=C/CCCCCCCC(O)=O OYHQOLUKZRVURQ-HZJYTTRNSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- YZCKVEUIGOORGS-NJFSPNSNSA-N Tritium Chemical compound [3H] YZCKVEUIGOORGS-NJFSPNSNSA-N 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000002309 gasification Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- OYHQOLUKZRVURQ-IXWMQOLASA-N linoleic acid Natural products CCCCC\C=C/C\C=C\CCCCCCCC(O)=O OYHQOLUKZRVURQ-IXWMQOLASA-N 0.000 description 1
- 235000020778 linoleic acid Nutrition 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- 229910052722 tritium Inorganic materials 0.000 description 1
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Abstract
Description
578272578272
發明所屬之技術領域 本發明係有關於一種溝槽的製造方法,特別係有關於 一種動態隨機存取記憶體(Dynamic Rand〇in Access Memory ,DRAM)之溝槽電容用的瓶型深溝槽的形成 先前技術 / ° 隨著動態隨機存取記憶體的密度持續地增加,記憶w 元(memojy cell)亦朝向縮小尺寸以提高密度的方向發$展早 ,而隨著DRAM製程持續縮小,深溝槽之孔徑大小亦隨之限 縮。當溝槽之縱寬比(aspect ratio)已超過35 :1時,作 為電容儲存區之深溝槽將因此而受限;此外,由於電容曰 係與電容電極板之表面積成正比,而溝槽電容之電極== 面積為溝槽之深度與溝槽圓周面積之乘積,溝槽圓周面積 則又與溝槽之孔徑有關,換言之,當製程技術從0.2um縮、 小至0· 1 8um時,溝槽之孔徑隨之變小,連帶使溝槽電容難 以得到足夠之電容表面積以使電容量能夠維持。再者,欲 形成具f較小臨界尺寸之深溝槽,便必須選擇高縱寬比= 方式進行钱刻,同時當溝槽臨界尺寸愈小,即命 保持垂直輪廓。 . —為了增加因為dram的尺寸縮小而變小的溝槽儲存電 容,必需發展增加儲存電容的方法,例如蝕刻半導體基底 以擴大溝槽底部而形成瓶型溝槽(bottle shaped trench) 的方法。 以傳統製程為例,請參考第1 a- 1 j圖,第1 a- 1 j圖係顯 示習知之製造瓶型溝槽之示意圖。TECHNICAL FIELD The present invention relates to a method for manufacturing a trench, and more particularly, to the formation of a bottle-shaped deep trench for a trench capacitor of a dynamic random access memory (DRAM). Prior technology / ° As the density of dynamic random access memory continues to increase, memory cells (memojy cells) are also moving in the direction of reducing size to increase density, and as the DRAM process continues to shrink, the depth of deep trenches The size of the aperture is also reduced accordingly. When the aspect ratio of the trench has exceeded 35: 1, the deep trench as a capacitor storage area will be limited accordingly. In addition, since the capacitance is proportional to the surface area of the capacitor electrode plate, the trench capacitance The electrode == area is the product of the depth of the trench and the circumferential area of the trench, and the circumferential area of the trench is related to the aperture of the trench. In other words, when the process technology shrinks from 0.2um to as small as 0.8 μm, the trench The hole diameter of the trench becomes smaller accordingly, and it is difficult for the trench capacitor to obtain a sufficient surface area to maintain the capacitance. Furthermore, in order to form a deep trench with a smaller critical dimension of f, it is necessary to choose a method of high aspect ratio = to carry out money engraving, and at the same time, as the critical dimension of the trench is smaller, the vertical contour is maintained. -In order to increase the trench storage capacitance which is reduced due to the shrinking of the size of the dram, it is necessary to develop a method for increasing the storage capacitance, such as a method of etching a semiconductor substrate to enlarge the bottom of the trench to form a bottle shaped trench. Taking the traditional manufacturing process as an example, please refer to Figures 1a-1j. Figures 1a-1j are schematic diagrams showing the conventional manufacturing of bottle grooves.
578272 五、發明說明(2) 首先,提供一半導體基底101,於半導體基底101上依 ,形成有一墊層102、一硬罩幕層103及一具有開口之圖案 化光阻層(未顯示),以圖案化光阻層為罩幕,蝕刻硬罩幕 曰1 0 3以在硬罩幕層1 〇 3上形成一開口,接著餘刻墊層 1〇2及半導體基底101以形成溝槽1〇4。其中,半導體基底 1 〇 1例如是矽基底;墊層1 〇 2之材質例如是氮化層;硬罩幕 層1〇3之材質例如是硼矽玻璃絕緣層或是氮化層與硼矽玻 璃之組合,可使溝槽之品質較佳,深度等條件亦較容易控 制;,半導體基底101與墊層102間更可形成一薄氧化層,可 使半導體基底1 〇 1與塾層1 〇 2間之附著性更佳。 請參考第lb圖,接著,在溝槽1〇4中露出表面之半導 ,基底101表面上順應性形成一第一襯層,第一襯層例如 ^在攝氏690至710度之溫度下,對半導體基底1〇1進行熱 氧化作用之氧化層105,其厚度約為25至35 A ;並且,於 半導體基底1 0 1及氧化層1 0 5的表面上順應性形成一第二櫬 層第一襯層例如是在攝氏700至720度之溫度下所形成之 氮化層106,其厚度約為45至55 A ;然後,在攝氏49()至 5 1 0、度之溫度下,於氮化層丨〇 6之表面上順應性形成一厚度 約為75至85 A之導電層107,導電層1〇7例如是多晶矽層或 蟲晶碎層。 一請參考第lc圖,在導電層1〇7的表面上順應性形成一 第三襯層,第三襯層例如是氧化層1 08。然後,在氧化層 =8上形成一犧牲層(未顯示),並以硫酸與雙氧水的混合 溶液(SPM)作為蝕刻液來進行濕蝕刻去除部份之犧牲層至 第6頁 0548-8874twf(Nl) ; 91110 ; Clairc.ptd 五、發明說明(3) 留下溝槽104底部之犧牲層,溝槽1〇4底部之 光阻層109,光阻層1〇9的厚度可根據f θ 1 钱刻的時間越長則光阻層1G9的厚度越薄 行疋進丁/ =間越短則光阻層109的厚度越厚,如第ld圖所丁 的 中,光阻層2 0 9亦可以旋塗玻璃層來取代。 八 睛參考第le圖,接著,以光阻層1〇9為飿 層1〇1遮盍之氧化層1〇8 ’以留下溝槽104底部 二匕^ 後,同、樣以硫酸與雙氧水的混合溶液 乍為蝕刻液來進行濕蝕刻,將光阻層1 〇 9完全去陝。 請參考第If圖,在攝W 〇〇〇至1100度之溫度下,二露 出表面之導電層1 07之表面上順應性形成一氮化層丨丨〇。 因為形成氮化層110時之溫度相當高,因此會導致構成導 電層107之夕日日石夕層或蠢晶石夕層晶格化,而在導電声IQ?上 形成空隙。 曰 請參考第lg圖,接著,以氮化層11()為蝕刻罩幕,依 序去除位於溝槽1〇7底部未被氮化層11〇覆蓋之氧化層i〇8a 及導電層107,而留下導電層i〇7a。 。月參考第1 h圖’以構酸(Hs Ρ Ο* )作為钱刻液體,對氮化 層1 1 〇進行濕蝕刻,同時,位於溝槽丨〇4底部之露出表面之 氮化層1 0 6亦會被去除。 請參考第1 i圖,以緩衝氫氟酸(BHF)為蝕刻液,以導 電層107a及其下方之氮化層i〇6a為蝕刻罩幕,對溝槽1〇4 底部之露出表面之氧化層1 〇 5進行濕蝕刻,以留下氧化層 10 5a ’同時會露出溝槽104底部之半導體基底1〇ι的表面;578272 V. Description of the invention (2) First, a semiconductor substrate 101 is provided. On the semiconductor substrate 101, a pad layer 102, a hard cover curtain layer 103, and a patterned photoresist layer (not shown) having openings are formed. The patterned photoresist layer is used as a mask, and the hard mask is etched to form an opening in the hard mask layer 103, and then the pad layer 102 and the semiconductor substrate 101 are etched to form a trench 10. 4. Among them, the semiconductor substrate 101 is, for example, a silicon substrate; the material of the cushion layer 10 is, for example, a nitride layer; and the material of the hard cover curtain layer 103 is, for example, a borosilicate glass insulation layer or a nitride layer and borosilicate glass. The combination can make the quality of the trench better and the conditions such as depth easier to control; a thin oxide layer can be formed between the semiconductor substrate 101 and the pad layer 102, which can make the semiconductor substrate 1 〇1 and the hafnium layer 1 〇2 Better adhesion. Please refer to FIG. Lb. Next, the surface of the semiconductor is exposed in the groove 104, and a first liner is conformably formed on the surface of the substrate 101. The oxide layer 105 that thermally oxidizes the semiconductor substrate 101 has a thickness of about 25 to 35 A; and conforms to form a second silicon oxide layer on the surfaces of the semiconductor substrate 101 and the oxide layer 105. A liner layer is, for example, a nitrided layer 106 formed at a temperature of 700 to 720 degrees Celsius, and has a thickness of about 45 to 55 A; then, at a temperature of 49 () to 5 10 degrees Celsius, under nitrogen, A conductive layer 107 having a thickness of about 75 to 85 A is compliantly formed on the surface of the chemical layer 〇6. The conductive layer 107 is, for example, a polycrystalline silicon layer or a worm-like fragment. First, referring to FIG. 1c, a third liner layer is conformably formed on the surface of the conductive layer 107, and the third liner layer is, for example, an oxide layer 108. Then, a sacrificial layer (not shown) is formed on the oxide layer = 8, and a mixed solution (SPM) of sulfuric acid and hydrogen peroxide is used as an etching solution to perform wet etching to remove the sacrificial layer. ); 91110; Clairc.ptd V. Description of the invention (3) Leave the sacrificial layer at the bottom of the trench 104, the photoresist layer 109 at the bottom of the trench 104, and the thickness of the photoresist layer 109 can be engraved according to fθ 1 money The longer the time is, the thinner the photoresist layer 1G9 is. The shorter the interval is, the thicker the photoresist layer 109 is. The shorter the photoresist layer 109 is, the higher the photoresist layer 109 can be. Replace with glass. Eight eyes refer to the first figure, and then, the photoresist layer 109 is used as the sacrificial layer 101 to mask the oxide layer 108 ′ to leave the bottom of the trench 104. After that, the same method is used for sulfuric acid and hydrogen peroxide. At first, the mixed solution is an etching solution to perform wet etching, and the photoresist layer 109 is completely removed. Please refer to the If diagram. At a temperature of 5000 to 1100 degrees, a nitride layer is formed on the surface of the conductive layer 107 on the exposed surface. Since the temperature at which the nitrided layer 110 is formed is quite high, it leads to the lattice formation of the conductive layer 107 or the stupid stone layer, and voids are formed in the conductive acoustic IQ ?. Please refer to FIG. 1g, and then use the nitride layer 11 () as an etching mask to sequentially remove the oxide layer 108 and the conductive layer 107 which are not covered by the nitride layer 11 at the bottom of the trench 107. The conductive layer i07a remains. . Referring to Figure 1h, using the acid (Hs P 0 *) as the etching liquid, the nitride layer 1 1 0 is wet-etched, and at the same time, the nitride layer 10 on the exposed surface at the bottom of the trench 1 0 6 will also be removed. Please refer to Figure 1i, using buffered hydrofluoric acid (BHF) as the etching solution, and using the conductive layer 107a and the nitride layer i6a below as the etching mask to oxidize the exposed surface at the bottom of the trench 104 The layer 105 is wet-etched to leave an oxide layer 105a, and at the same time, the surface of the semiconductor substrate 10m at the bottom of the trench 104 is exposed;
0548-8874twf(Nl) ; 91110 ; Claire.ptd 第7頁 578272 五、發明說明(4) 然後,以氫氧化銨(NH4 0H )作為蝕刻液,並以導電層1 〇 7a 為罩幕’對溝槽104底部露出表面之半導體基底1〇1進行濕 蝕刻,以形成一瓶型溝槽丨丨工。 上述之傳統製程的問題在於,進行如第1 f圖所示之氮 化層11 0時,高溫會導致構成導電層丨〇 7之多晶矽層或磊晶 石夕層晶格化而形成空隙,當在利用氫氧化銨(NH4〇h)作為 #刻液來對溝槽1 〇4底部露出表面之半導體基底丨〇1進行濕 #刻以形成瓶型溝槽1 1 1時,餘刻液會藉由空隙侵姓半導 體基底101而產生缺口 112,導致半導體基底1〇1之品質下 降’如第1 j圖所示。 發明内容 ,有鑑於此,本發明之目的在於提供一種在半導體基底 製造瓿型溝槽的方法,可利用將溝槽上部之導電層氧化的 方法來保護半導體基底之結構不會在形成槪型溝槽的過程 中產生損壞。 根據上述目的,本發明提供一種瓶型溝槽的製造方 二列步驟:提供一半導體基底,半導體基底上具 广β、# &層,且半導體基底上形成有—溝槽;於半導體 底及溝槽之表面上依序順應性形成一第一襯層、一第二0548-8874twf (Nl); 91110; Claire.ptd Page 7 578272 V. Description of the invention (4) Then, ammonium hydroxide (NH4 0H) is used as the etching solution, and the conductive layer 107a is used as a mask to face the trench. The semiconductor substrate 101 at the bottom surface of the trench 104 is wet-etched to form a bottle-shaped trench. The problem with the conventional process described above is that when the nitrided layer 110 is performed as shown in Figure 1f, the high temperature will cause the polycrystalline silicon layer or epitaxial layer that constitutes the conductive layer to be latticed to form voids. When ammonium hydroxide (NH4〇h) is used as the #etching solution to wet-etch the semiconductor substrate at the bottom of the groove 104, the surface is exposed to form a bottle-shaped groove 1 1 1. The gap 112 invades the semiconductor substrate 101 and generates a notch 112, which causes the quality of the semiconductor substrate 101 to decrease, as shown in FIG. 1j. SUMMARY OF THE INVENTION In view of this, an object of the present invention is to provide a method for manufacturing a pit-shaped trench on a semiconductor substrate. The method of oxidizing the conductive layer on the top of the trench can be used to protect the structure of the semiconductor substrate from forming a trench. Damage occurred during the groove. According to the above object, the present invention provides a two-step manufacturing method of a bottle-shaped trench: providing a semiconductor substrate having a wide β, # & layer on the semiconductor substrate, and a trench formed on the semiconductor substrate; A first lining layer, a second
層於:::?及於一第三襯層’第一襯層與第二襯層相 罩真入一既定深度之犧牲層;以犧牲層為姓 對^表面之導電層進行氧化步驟以形成 化層為餘刻罩幕,依序去除未被氧化層覆蓋之第丄襯層Layer on :::? And a third liner 'the first liner and the second liner cover the sacrificial layer of a predetermined depth; using the sacrificial layer as a surname to perform an oxidation step on the surface conductive layer to form a chemical layer as a mask Curtain, sequentially remove the third liner that is not covered by the oxide layer
578272 發明說明(5) _ 底::襯f及第-襯層1露出位於溝槽底部之半 及以氧化層…,㈣半導體基底以形 根據上述目的,太名么日日田# 法,包括下列步驟:提;一月=:種瓶型溝槽的製造方 序形成有-墊層、一硬罩幕=體ί;化基= 基底,以在半導體基底:::=、;=層…^ 層;於半導體基底及第一;形成-第-襯 第二襯層及一導電層1 一;士依序順應性形成- 層表面上順應性形成一第三襯;?表 犧牲層’且犧牲層填滿溝ί 上: 在溝槽底邛留下一既定深度之犧牲声; 曰 幕,去除未被犧牲層覆蓋之第三襯^ 〔厂蝕刻罩 表面;將犧牲層去除;胃露出表面‘導;層之 化層覆盍之第三襯層、導電層、第- 、衣破虱 【出位於溝槽底部之半導體基底表;覃以 幕,姓刻半導體基底以形成一瓶型溝槽。 曰為罩 根據上述目的,本發明更提供一 ^ 法,包括下列步驟:提供一半導體η ί槽的製造方 序形成有一第一氮化層、一及上依 ;以圖案化光阻層為蝕刻罩$ ’依序蝕刻第一氮化^且層578272 Description of the invention (5) _ Bottom: The lining f and the first lining layer 1 are exposed at the bottom half of the trench and exposed with an oxide layer ..., the semiconductor substrate is shaped according to the above purpose, the Taiming Modi Hita # method includes the following Steps: mention; January =: The manufacturing sequence of the bottle-shaped groove is formed with-a cushion layer, a hard mask = body ί; chemical base = substrate, to the semiconductor substrate :: = ,; = layer ... ^ Layer; on the semiconductor substrate and the first; forming-the first-lining second lining layer and a conductive layer 1-a; sequential compliance formation-forming a third lining on the surface compliance; The surface sacrificial layer 'and the sacrificial layer fill the trench. On the bottom of the trench, a sacrificial sound of a predetermined depth is left; the curtain is removed, and the third liner that is not covered by the sacrificial layer is removed. Removed; the exposed surface of the stomach is guided; the third layer of the chemical layer is covered with the third conductive layer, the conductive layer, the first, and the second one, the semiconductor substrate at the bottom of the trench; Qin Yimu, the semiconductor substrate is engraved to form Bottle-shaped groove. According to the above purpose, the present invention further provides a method including the following steps: providing a manufacturing sequence of a semiconductor η groove, forming a first nitride layer, a top layer, and using a patterned photoresist layer as etching Mask $ 'sequentially etch the first nitride layer
578272 五、發明說明(6) 矽玻璃層及 並去除圖案 半導體基底,以在 化光阻層;於溝槽 應性形成一第一氧化層;於半 半導體基底 露出之半導 導體基底及 表面上依序 三氮化層; 光阻層填滿 深度之光阻 蓋之第三氮 去除;氧化 以第二氧化 化層覆蓋之 化層,以露 氧化層為罩 槽0 順應性形成 於半導體基 溝槽;蝕刻 層;以光阻 化層以露出 該多晶層以 層為蝕刻罩 第三氮化層 出位於溝槽 幕,對半導 上形成一溝槽, 體基底表面上川貝 該第一氧化層之 弟一氣化層、一多晶碎層及一第 成一光阻層,且 底表面 光阻層 層為钱 部分多 使該多 幕,依 、多晶 底部之 體基底 上順應性形 ,以在溝槽 刻罩幕,去 晶石夕層之表面,將 晶矽層形成 序去除溝槽 底部留下 除未被 既定 光阻層覆 該光阻層 第二氧化層; 矽層、第二 半導體基底 進行濕蝕刻 底部未被第二氧 氮化層及第一氧 表面;及以第二 以形成一瓶型溝 猫旦ί使本發明之上述和其他目的、特徵、和優點能更明 ”、、 ,下文特舉一較佳實施例,並配合所附圖式,作詳 細說明如下: 實施方法: 第2a-2i圖係顯示本發明之製造瓶 請參考第2a-2i圖 型溝槽之示意圖。 请參考第2a圖,首矣 Α L ^百先,提供一半導體基底201,於半 導體基底201上依序形忐士 〇 « ^ „ 成有一墊層202、一硬罩幕層203及 一具有開口之圖案化光阪 罢莖 u ^ ^ 〜1且層(未顯示),以圖案化光阻層為578272 V. Description of the invention (6) Silicon glass layer and pattern semiconductor substrate are removed to form a photoresist layer; a first oxide layer should be formed in the trench; and a semiconducting substrate and surface exposed on the semi-semiconductor substrate Sequential trinitride layer; the photoresist layer fills the depth of the third photoresist cap with the third nitrogen removed; oxidizes the chemical layer covered with the second oxide layer, and exposes the exposed oxide layer as the cover groove. 0 Compliance is formed in the semiconductor base trench Groove; etching layer; photoresistive layer to expose the polycrystalline layer; layer as an etch mask; third nitride layer; located on the trench curtain; a groove is formed on the semiconductor; The layer's brother is a gasification layer, a polycrystalline fragment layer, and a photoresist layer, and the bottom surface photoresist layer is made of money to make the multi-screen, conforming to the conformal shape of the body substrate at the bottom of the polycrystal. The trench is engraved with a mask to remove the surface of the spar layer, and the crystalline silicon layer is formed in order to remove the bottom of the trench, leaving a second oxide layer on the photoresist layer that has not been covered by a predetermined photoresist layer; a silicon layer and a second semiconductor substrate Wet etched bottom not second The nitrided layer and the first oxygen surface; and the second to form a bottle-shaped trench cat to make the above and other objects, features, and advantages of the present invention clearer. ",,, a preferred embodiment is given below. With the accompanying drawings, the detailed description is as follows: Implementation method: Figures 2a-2i show the manufacturing bottle of the present invention. Please refer to the schematic diagram of the grooves of Figure 2a-2i. Please refer to Figure 2a, first L ^ Baixian provided a semiconductor substrate 201 on which the substrates were sequentially formed. «^« Formed with a cushion layer 202, a hard cover curtain layer 203, and a patterned light-emitting stem with openings ^ ^ ~ 1 and layer (not shown), with patterned photoresist layer as
罩幕,蝕刻硬覃暮層?nQ 更皁拳層203 ’以在硬罩幕層2〇3上形成一開Mask, etch hard Tan Mu layer? nQ Gengzao Boxing Layer 203 ′ to form an opening on the hard cover curtain 203
第10頁 578272Page 10 578272
口,接著蝕刻墊層20 2及半導體基底2〇1以形成溝槽2〇4。 半導體基底2 0 1例如是矽基底;墊層2 〇 2之材質例如 ,,化層,硬罩幕層2 〇 3之材質例如是硼矽玻璃絕緣層或 f氮化層與哪矽玻璃之組合,可使溝槽之品質較佳,深度 專條件亦較谷易控制,·半導體基底2 0 1與墊層2 0 2間更可形 成一薄氧化層,可使半導體基底2〇1與墊層2〇2間之附著性 更佳。 5月參考第2b圖,接著,在溝槽204中露出表面之半導 體基底201表面上順應性形成一第一襯層,第一襯層例如 是在攝氏650至750度之溫度下,對半導體基底2〇1進行熱 氧化作用之氧化層205,其厚度約為25至35A ;並且,於 半導體基底2 0 1及氧化層2 0 5的表面上順應性形成一第二襯 層’第二襯層例如是在攝氏7〇〇至720度之溫度下所形成之 氮化層206,其厚度約為45至55A ;然後,在攝氏4 90至 51 〇度之溫度下,於氮化層2 〇 6之表面上順應性形成一厚度 約為75至85A之導電層207,導電層207例如是多晶矽層或 蠢晶矽層。其中,第一襯層與第二襯層之材質必須相異, 以利後續製程之進行。 接下來,進行本發明之一特徵步驟。 請參考第2c圖,在導電層207的表面上順應性形成一 第三襯層,第三襯層例如是在攝氏70 0至720度之溫度下所 形成之厚度約為35至45 A之氮化層208。 然後,在氮化層208上形成一犧牲層(未顯示),並以 硫酸與雙氧水的混合溶液(SPM)作為蝕刻液來進行濕蝕刻Then, the pad layer 202 and the semiconductor substrate 201 are etched to form a trench 204. The semiconductor substrate 2 01 is, for example, a silicon substrate; the material of the cushion layer 2 2 is, for example, a chemical layer, and the hard cover layer 2 3 is a material such as a borosilicate glass insulating layer or a f-nitride layer and a combination of silicon glass It can make the quality of the trench better, and the depth specific conditions are easier to control than the valley. · A thin oxide layer can be formed between the semiconductor substrate 201 and the pad layer 202, which can make the semiconductor substrate 201 and the pad layer Better adhesion between 002. Referring to FIG. 2B in May, a first liner layer is conformably formed on the surface of the semiconductor substrate 201 whose surface is exposed in the trench 204. The first liner layer is, for example, a semiconductor substrate at a temperature of 650 to 750 degrees Celsius. The oxide layer 205 undergoing thermal oxidation has a thickness of about 25 to 35 A; and a second liner layer is formed on the surface of the semiconductor substrate 201 and the oxide layer 205 to conform to the second liner layer. For example, the nitrided layer 206 formed at a temperature of 700 to 720 degrees Celsius has a thickness of about 45 to 55 A; then, at a temperature of 4 90 to 5100 degrees Celsius, the nitrided layer 206 is formed. A conductive layer 207 having a thickness of about 75 to 85 A is compliantly formed on the surface. The conductive layer 207 is, for example, a polycrystalline silicon layer or a staggered silicon layer. Among them, the materials of the first lining layer and the second lining layer must be different to facilitate the subsequent processes. Next, a characteristic step of the present invention is performed. Referring to FIG. 2c, a third liner is conformably formed on the surface of the conductive layer 207. The third liner is, for example, a nitrogen layer having a thickness of about 35 to 45 A at a temperature of 70 to 720 degrees Celsius.化 层 208. The layer 208. Then, a sacrificial layer (not shown) is formed on the nitride layer 208, and wet etching is performed using a mixed solution of sulfuric acid and hydrogen peroxide (SPM) as an etching solution.
0548-8874twf(Nl); 91110 ; Claire.ptd 第11頁 578272 五、發明說明(8) 部份之犧牲層至留下溝槽2〇4底部之犧牲層,溝槽2〇4 =邛之犧牲層例如是光阻層209,光阻層20 9的厚度可根據 需^來決定,進行濕蝕刻的時間越長則光阻層2〇9的厚度 越溥,進行濕蝕刻的時間越短則光阻層2 〇 9的厚度越厚^ ^第2d圖所示。其中,光阻層2〇9亦可以旋塗玻璃層:取 代。 、凊參考第2e圖,接著,以緩衝氫氟酸(BHF)作為蝕刻 液並以光阻層2〇9為蝕刻罩幕,去除未被光阻層2〇9遮蓋 之氮化層208,以留下溝槽204底部之氮化層2〇8& ;狹後, 同樣以硫酸與雙氧水的混合溶液(s p M)作為蝕刻液來進行 濕敍刻,將光阻層2 〇 9完全去除。 接下來,進行本發明之另一特徵步驟。 請參考第2f圖,以氮化層208&為罩幕, 91〇度之溫度下,對露出表面之導電層2〇7進行氧=作用, 以使導電層207形成一厚度約為145至155人之氧化層以^。 請參考第2g圖’以氧化層21〇為蝕刻罩幕,在二氏16〇 至170友度的溫度下,以麟酸(H3p〇4)作為敍刻液,對露出表 面之氮化層208a進行濕敍刻,以完全去除氮化層2〇8a。接 著,以氫氧化銨(NH4〇H)作為蝕刻液,對露出表面之導電 層207進行濕㈣’以去除未被氧化層⑽覆蓋之導電層而 留下導電層2G7a。錢,在攝氏16()至17()度的溫度下以 碗酸(Η3Ρ04)作為餘刻液,對露出表面之氮化 蝕刻,以留下氮化層2〇6a。 …、 請參考第2h圖’以緩衝氫氟酸⑽F)為蝕刻液,以氧 第12頁 0548-8874twf(Nl) ί 91110 » Claire.ptd 578272 五、發明說明(9) =層了為餘刻罩幕,對露出表面之氧化層2〇5進娜 體美底2(1 H化層2〇5& ’同時會露出溝槽204底部之半導 if: MO 因為氧化層210下方形成有氮化層2〇6a J二匕層210之厚度較氧化層2〇5之厚度要來的厚,因此 化層2〇5的過程中’氧化層210及氮化層,可保 產溝槽2 0 4之側壁不會損壞。 :參,第21圖’然後,以氫氧化銨(NH4QH)作為餘刻 美二:化層210為罩幕,對溝槽204底部露出表面之半 導體基底2G1進行濕#刻’以形成—瓶型溝槽川。 开4 ί Ϊ Γ所Ϊ供的方法’主要是讓導電層進行氧化作用 :卞化層’來徹底防止構成導電層之多晶石夕層或蠢晶石夕 = 境下晶格化’所以不會有蝕刻液經由空隙來 ::ί ί底的情況發生,保持半導體基底之完整性, 進而知:咼產品之可靠度。 W 一 ί、、;、本發明已以較佳實施例揭露如上,然其並非用以 發明:任何熟習此技藝者,在不脫離本發明之精神 ^内,§可作更動與潤飾,因此本發明之保護範圍當 視後附之申請專利範圍所界定者為準。0548-8874twf (Nl); 91110; Claire.ptd Page 11 578272 V. Description of the invention (8) part of the sacrificial layer to the sacrificial layer leaving the bottom of the trench 204, trench 204 = sacrificial layer of 邛For example, the photoresist layer 209, the thickness of the photoresist layer 209 can be determined according to requirements. The longer the wet etching time is, the thicker the photoresist layer 209 is, and the shorter the wet etching time is, the photoresist is. The thicker the thickness of the layer 209 is shown in Figure 2d. Among them, the photoresist layer 209 can also be spin-coated with a glass layer: instead. Refer to Figure 2e, and then use buffered hydrofluoric acid (BHF) as the etching solution and the photoresist layer 209 as the etching mask to remove the nitride layer 208 that is not covered by the photoresist layer 209. After the nitride layer 208 at the bottom of the trench 204 is left narrow, wet engraving is also performed using a mixed solution (sp M) of sulfuric acid and hydrogen peroxide as an etching solution, and the photoresist layer 009 is completely removed. Next, another characteristic step of the present invention is performed. Please refer to FIG. 2f. With the nitrided layer 208 & as a mask, the conductive layer 207 exposed at the surface is subjected to oxygen action at a temperature of 91 ° C, so that the conductive layer 207 forms a thickness of about 145 to 155. The human oxide layer is ^. Please refer to Fig. 2g, with the oxide layer 21 as the etching mask, at a temperature of 160 to 170 degrees Celsius, and using linoleic acid (H3p〇4) as the etch liquid, the nitrided layer 208a on the exposed surface A wet engraving is performed to completely remove the nitride layer 208a. Next, using the ammonium hydroxide (NH4OH) as an etching solution, the conductive layer 207 exposed on the surface is wet-etched 'to remove the conductive layer not covered by the oxide layer and leave the conductive layer 2G7a. Qian, using a bowl of acid (Η3Ρ04) as a post-etching solution at a temperature of 16 () to 17 () degrees Celsius, etched the exposed surface by nitriding to leave a nitrided layer 206a. …, Please refer to Figure 2h 'Using buffered hydrofluoric acid (F) as the etching solution and oxygen Page 12 0548-8874twf (Nl) ί 91110 »Claire.ptd 578272 5. Description of the invention (9) = layer is for the time left The mask, the exposed surface of the oxide layer 205 into the body beautiful bottom 2 (1 Hization layer 205 & 'At the same time, the semiconductor at the bottom of the trench 204 will be exposed if: MO because nitride formed under the oxide layer 210 The thickness of the layer 206a and the second layer 210 is thicker than the thickness of the oxide layer 205. Therefore, in the process of forming the layer 205, the oxidized layer 210 and the nitrided layer can guarantee the production of the trench 2 0 4 The side walls will not be damaged .: See, Figure 21 'Then, use ammonium hydroxide (NH4QH) as a finish. Second: The chemical layer 210 is used as a mask, and the semiconductor substrate 2G1 exposed at the bottom of the trench 204 is wet-etched. 'To form-bottle-shaped trenches. The method provided by Kai 4 ί Ϊ Γ' is mainly to allow the conductive layer to oxidize: tritium layer 'to completely prevent the polycrystalline stone layer or stupid stone that constitutes the conductive layer. Xi = Lattice in the environment 'so no etching solution will come through the gap :: ί the bottom will happen, maintaining the integrity of the semiconductor substrate, and then knowing: The reliability of the invention W. The invention has been disclosed above in a preferred embodiment, but it is not intended to invent: Any person skilled in the art can make changes and modifications without departing from the spirit of the invention ^. Retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application.
578272 圖式簡單說明 第1 a- 1 j圖係顯示習知之製造瓶型溝槽之示意圖。 第2a-2i圖係顯示本發明之製造瓶型溝槽之示意圖。 符號說明: 101、 201〜半導體基底; 102、 20 2〜墊層; 1 0 3、2 0 3〜硬罩幕層; 1 0 4、2 0 4〜溝槽; 105、 105a、205、205a〜氧化層; 106、 106a、20 6、20 6a〜氮化層; 107、 107a、20 7、20 7a〜導電層; 108、 108a〜氧化層; 109、 209〜光阻層; 11 0〜氮化層; 111、2 11〜瓶型溝槽; 11 2〜缺口; 208、208a〜氮化層; 2 1 0〜氧化層。578272 Brief description of the drawings Figures 1 a to 1 j are schematic diagrams showing the conventional manufacturing of bottle grooves. Figures 2a-2i are schematic views showing the manufacturing of a bottle groove according to the present invention. Explanation of symbols: 101, 201 ~ semiconductor substrate; 102, 20 2 ~ underlayer; 1 0 3, 2 0 3 ~ hard cover curtain layer; 104, 2 0 4 ~ groove; 105, 105a, 205, 205a ~ Oxidation layer; 106, 106a, 20 6, 20 6a ~ nitride layer; 107, 107a, 20 7, 20 7a ~ conductive layer; 108, 108a ~ oxide layer; 109, 209 ~ photoresist layer; 11 0 ~ nitride 111, 2 11 ~ bottle-shaped groove; 11 2 ~ notch; 208, 208a ~ nitride layer; 2 1 0 ~ oxide layer.
0548-8874twf(Nl) ; 91110 ; Claire.ptd 第14頁0548-8874twf (Nl); 91110; Claire.ptd page 14
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