TW577172B - Dual bit split gate flash memory and manufacturing method thereof - Google Patents

Abstract

The present invention provides a dual bit split gate flash memory. It includes a substrate, a first and second floating gate, a control gate, a select gate, a source, and a drain. The select gate is disposed on the substrate. The first and second floating gate are disposed on the substrate and two sides of the select gate. The control gate is disposed above the first and second floating gate, and the select gate. The source and drain are in the substrate and on two sides of a stack of the first and second floating gate, control gate, and select gate.

Description

577172

FIELD OF THE INVENTION The present invention relates to a flash memory structure and a method for manufacturing the same, and more particularly, to a two-bit separated flash memory structure and a method for manufacturing the same. Excessive operating voltage. Mechanical Prior Technology Non-volatile semiconductor devices with flash memory cells are used to erase and write data electronically, and can even save data without power supply. For this reason, such non-volatile semiconductor devices are commonly used in many different applications. A traditional flash memory uses a memory cell to store a bit of data. The first circle shows the structure of a traditional single-element flash memory. The j flash memory includes an N + source doped region, la, N + / N-drain doped region, and a channel between the two. Zone 12 is separated. The channel region 12 has a portion 12a below the floating gate / pole 13 and a portion 12b below the selection gate 14. Between the channel region 12 and the selection gate 14 and the floating gate 13 there is a gate insulating layer 16a, and on the floating gate 13 there is an insulating layer 6b composed of a thermal oxide layer and a nitride layer. The control gate electrode 7 is formed on the insulating layer 16b. There are insulation 16c on both sides of the floating gate 丨 3 and the control gate 丨 7. The operation of the above-mentioned single-element flash memory is as follows: When writing, 'control the gate to receive a potential of about 17 volts, select the gate to receive a potential of about 1.5 volts, the drain to receive a 5 volt potential, and the source then

577172 V. Description of the invention (2) Grounding. During erasure, the drain receives a 14 volt potential, controls the gate to ground, and the source floats. The high potential required for erasing can be provided by the charge pump circuit, so that only a 5 volt power supply can be used for memory operation. The flash memory structure in Figure 1 has several disadvantages as follows. First, it uses two transistors to memorize a bit of data, which consumes a lot of circuit area. Second, since the length of the selected gate is determined by the height of the floating gate and the control gate, its channel length is short and punchthrough is very easy to occur. Third, due to the selection of a spacer composed of polycrystalline stones outside the gate, the metal silicide layer is not easy to be deposited thereon, so the polycrystalline silicon material selected for the gate can only have an area resistance value of 20 ~ 30ohm. Yuan line RC delay is serious. With the increasing demand for memory capacity of electronic products and the shrinking of the chip area, "high bit density" (high bit density) has become the focus of memory structure research and improvement. Among them, one method to increase the bit density is to use multi-level quasi-memory cells (mul t i-level ce 11). A multi-level memory cell can store multiple charge levels at different levels to achieve the purpose of storing multiple bits. In other words, in a multi-level memory cell, the floating gate must be able to accurately store a plurality of different levels of charge with different threshold voltage values. Therefore, when performing a write operation on a multi-level memory cell, it is necessary to be very careful to store the correct amount of charge in the floating interrogation pole 'so that its operation speed is slower than that of the traditional unit cell memory. In addition, in order to have a sufficient potential range to accommodate multiple threshold voltage levels, the operating voltage required for multi-level memory is also high. High operating voltage will cause the memory use tolerance to deteriorate. ,

577172 V. Description of the invention (3) Another way to increase the memory bit density is to use ^ floating gates in a memory cell instead of multiple levels. One example is a two-bit split gate flash memory structure proposed by the United States No. 5 364 806. As shown in Fig. 2, it includes a first floating closed electrode: a crystal 20, a transistor 22 formed of a second floating gate, and a transistor 24 formed of a selected gate. Transistor 24 is connected in series with transistors 20 and 22. Each memory structure is formed in a p-type silicon substrate 26. The silicon substrate 26 has a drain electrode 20a of the transistor 20 and a drain electrode of the transistor ㈣. Transistor package = connected to the gate 2Gb and the control gate on it. There is a thin gate oxide layer 20d between the floating gate electrode and the earth, and there is an insulating layer between the control gate 20c and the floating gate, and b. Similarly, the transistor "encloses the gate 22b and the control gate 22c thereon. The floating gate 22b and the technology gate have a thin gate oxide layer 22d, and the control gate. It floats between two M Then it has-the insulating layer 22e. The insulating layer 2Gf and the regular bit :: 2:: ί 2. The sub-wire 28 extends above the insulating layer and forms the control gate of the electric body 2 4 The above-mentioned double bit 7G The operation of separating the gate flash memory is as follows: When M =, select the gate to receive the potential of h8 ~ 2 volts, two controls = connect = ... respectively :: two options and = connect: electricity 5: special: a potential, Receive "Volts" and "0 Volts". When "Source" and "Pole" are respectively erased, select the interrogator to receive the potential of 0 Volts. The two control open poles are 503-8775TW (Nl); TSMC2000. 〇695; vIncent.ptd Page 7 577172 V. Description of the invention (4) Both receive a potential of 0 volts, and the two source / drain regions receive the potential and are floated respectively. The advantages of the bit-separated gate flash memory are as follows. He Dan has a complex, 6 brothers, a memory cell can store two bit data. First, used I aligned the etching step so that the gate body length of the gate can be selected more accurately. Third, it has a higher memory. However, 'the length of the required channel length is too long because it is in one', which is not conducive to chip shrinkage. Two control gates are used in the memory cell, and the invention has an increase in the degree of the delta memory bit density of the circuit surface used by the memory. The present invention also has a voltage. In order to solve the above problems, the memory structure and its manufacturing method are operated at a high speed and do not require excessive operation. The first object of the present invention is a memory, including: a substrate; a first and a first; A floating gate electrode, a side; a control gate electrode located above the pole; and a non-electrode and a source electrode, both sides of the first and second floating gate electrodes. A second object of the present invention is to provide a double bit Separate flash memory with higher memory bit density, a two-bit split gate flash flash gate, located above the substrate; two floating gates above the substrate and the selection gate are separated from the selection The substrate and the selection gate closing one seed separating stacked layers of double bit flash gate electrode formed

577172

A method for manufacturing a memory includes the following steps: providing a substrate; forming a selection gate above the substrate; forming first and second floating gates above the substrate and on both sides of the selection gate; 1. A control gate is formed above the second floating gate and the selection gate; and a stacked layer formed in the substrate and the selection gate, the first, second floating gates, and the control gate A drain and a source are formed on both sides. ^ A third object of the present invention is to provide a method for manufacturing a dual-bit discrete gate flash memory, which includes the following steps: providing a substrate; forming on the substrate-a first conductive & A second conductive layer and a third conductive layer are formed on both sides of the first conductive layer; the fourth conductive layer is formed above the first conductive layer; and the first and second conductive layers are formed in the substrate. A first and a second doped region are formed on both sides of a stacked layer formed by the third and fourth conductive layers. In this way, the IQF has two floating gates located under one control gate and isolated by the selected gate, so it can store two bits of data. At the same time, 'Because the two bit systems in a memory cell are respectively independent of writing, reading, and erasing,' the operating voltage is the same as the unit separation, flashing, and flash memory. High bit density 'has faster operating speed and use tolerance. The following 'Jingyou' diagrammatically illustrates an embodiment of a dual structure of the present invention and its manufacturing method. ρ Τ ′ Π A It Embodiments Figures 3 A to 3 E show the two-bit separation gate in the embodiment of the present invention. ^ ^ ^

0503-8775TWF (N1); TSMC2002-0695; vincen t. Ptd page 9 577172 V. Description of the invention (6) Flash memory manufacturing process First, as shown in FIG. 3A, a crystal plane is provided as < 1〇〇 > Which? A silicon substrate 3 is formed, and a selection gate 31 is formed on the silicon substrate 3. Among them, a thin gate oxide layer having a thickness of about 30 f is firstly formed on the surface of the silicon substrate 3 by a thermal oxidation method at a temperature of more than 900 degrees Celsius. After the gate oxide layer is formed, a low-pressure chemical vapor deposition (LPCVD) method is used to deposit a thickness of about 1,000 people in an environment of 60065 ° C and a pressure of 0.3 to 0.6 Torr. The polycrystalline silicon π = above the gate oxide layer. Then it is formed again-the thickness is about the height of a person, the second layer is ⑽) on the polycrystalline stone layer, and the W layer formed by the above steps is engraved with a definition of the H-circle of the selection gate. The selection gate 31, the gate oxide layer 32, and the south temperature oxidation layer 33 above the selection gate 31. Another high-temperature hydrogen mask life, Shi # ^ A ® ^ ^ ^ 〇 gate, the plate oxide layer was deposited on the 3 again, and through the anisotropic dry engraving step = ί on both sides to form a thickness of about 500 The spacer wall 34 of A is exposed on the surface of the silicon substrate 3 of titanium: B. After the formation of the partition wall 34, the method 8 is performed again: a tunnel oxide layer 35 with a thickness of about 80 to 100 A is formed on the surface of the exposed stone eve substrate 3. 'f J' As shown in Fig. 3B, in a polycrystalline silicon layer having a gate filling height lower than that of the stocking layer, 0 3 Λ τ Γ «is deposited at a temperature of 600 to 65 ° C and a pressure / i of two branches. The thickness is about 3mm thick. "Shi Xi :: Then use chemical mechanical polishing (CMP) or Hou Xi: Shi Xi reduced to below the stacked layer. In this way, Bhui separated its homogeneous stacked layer. And the self-alignment f Xi Yue said that the Shi Xi layer 36 was selected before the double gate was selected before the gate stacked layers were selected.

577172 V. Description of the invention (7) Next, as shown in FIG. 3C, an oxygen-nitrogen-oxide layer (〇NO) 37, a polycrystalline silicon layer 38, and a tetraethyl silicate layer (TE0s) 39 are sequentially formed. . The oxygen-gas-oxide layer 37 is composed of a high-temperature oxide layer, a nitride layer, and another high-temperature oxide layer each having a thickness of about 60 A. The oxygen-nitrogen-oxide layer 37 serves as an insulating layer between the polycrystalline silicon layers 36 and 38. Similarly, the polycrystalline silicon layer 38 is also deposited on the oxygen-nitrogen-oxide layer 37 by a low pressure chemical vapor deposition method at a temperature of 600 to 650 degrees Celsius and a pressure of 0 to 6 Torr. 20000λ. After the polycrystalline silicon layer 38 is deposited, a tetraethylsilicate layer 39 of about 1000 A is similarly deposited by a low pressure chemical vapor method. Furthermore, as shown in FIG. 3D, a mask pattern is used to etch a stacked layer composed of an oxygen-nitrogen-oxide layer 37, a polycrystalline silicon layer 38, and a tetraethylsilicate layer 39 to form an exposed tunnel. The groove 40 passing through the oxide layer 35. The mask pattern used here must be aligned with the mask pattern defining the selection gate 31 so that the groove 40 is formed between the two selection gates 31. Greater than ... the layer 31, the two partition walls 34, and the most: 4 not °] = the sum of the allowable widths. Finally, as shown in FIG. 3E, the formation of the two-layer barrier wall 41 formed by the stacked layer consisting of the polycrystalline silicon layer 36, oxygen-nitrogen-oxidation: 3 dipolycrystalline silicon layer 38, and tetraethyl silicate layer 39 is first Low Pressure Chemical Vapor Deposition: "A high temperature oxide layer, a tetraethyl silicate layer, or a mixture of I was deposited on the circle, and then the groove was more than 4021 by anisotropic dry etching. It is formed by leaving the parts on both sides of the stacked layer. When the recessed layer is etched, the through oxide layer 35 is also removed and exposed at the same time: the surface of the substrate 3. The source region 42 and the electrodeless region 43 formation is oxygen-nitrogen-oxygen

577172 V. Description of the invention (8) The stacked layer composed of the chemical layer 37, the polycrystalline silicon layer 38, and the tetraethyl silicate layer 39 is a mask, and phosphorus is used as an ion source to implant phosphorus ions on the entire wafer. 'The concentration is about 1015 / cm2. Therefore, as shown in FIG. 3E, the dual-bit split-gate flash memory system of the present invention is formed on a silicon substrate 3, and includes a selection gate 31 above the silicon substrate 3, a selection gate 31 above the silicon substrate 3, and a selection. The floating gate 36 on both sides of the gate 31, the control gate 38 located above the two floating gates 36 and the selection gate 31, and the silicon gate 3 and the selection gate 31 and two floating gates A drain electrode 42 and a source electrode 42 on both sides of a stacked layer formed by the electrode 36 and the control gate 38. In addition, there is a thin gate oxide layer 32 between the silicon substrate 3 and the selection gate 31. Above 31, there is a high-temperature oxide layer 33, and there are gap walls 34 on both sides of the south-temperature oxide layer 33 and the selection gate 31. Between the control open electrode 38 and the two floating gate electrodes μ and the high-temperature oxide layer μ, a 2: Above the control gate 38, there is a tetraethyl oxalate layer 2. It is composed of two = 36, an oxygen-nitrogen_oxide layer 37, a polycrystalline silicon layer, and a tetraethyl oxalate • -layer 39 There are gap walls 41 on both sides of the stacked layer. The operation of the above-mentioned two-bit split gate flash memory is as follows--101 volt = with: pole-side bit As an example, write the gate 38 to receive the potential of υ, the drain 43 to receive the potential of 5 volts, the thunder potential of 1.8 volts, the potential of Tato ^, and select the gate 31 to 5 v seconds. At this time, it is grounded at 42 and Shixi substrate 3 is grounded. When the gate 36 is continued, the second one is changed? # The electrons will be injected into the floating threshold voltage value on the drain side to reach the level formed by the storage closed-pole. The equivalent transistor pole-side bit, the purpose of the second material. Similarly, the write source control open electrode 38 receives a potential of 10 volts V. Description of the invention (9) 5 volt potential, select the gate 31 Receiving 丨 · 8 ground, famei accepts 4dt ^ special potential '> and pole 42 silicon substrate 3 ground, holding time is 5 # seconds. Parallelism, the hot electron will inject the floating gate on the source side The equivalent transistor threshold current formed by the closed pole on the floor / pole side: the value is equal to the purpose of floating. The value of electricity is 7 翌, and the stored data--5 volts 2Γ :? and the erasure of the pole side bits are achieved. For example, 'control gate 38 receives and receives -1.8 volt potential, and source 42 is grounded. Η: The electrons in side gate 36 will be stored because of the holes. The data is erased. Similarly, when the source-side bit is erased, the control gate 38 receives a voltage of _5 volts, the source 42 receives a potential of 7 volts, and the selected gate 31 receives a voltage of -18 volts. ^ And electrode 43 are grounded, Shixi substrate 3 is grounded, and the duration is 5m seconds. At this time, the electrons in the floating gate 36 on the source side will be lost due to the injection of the hole, so that the data stored in it will be lost. Erase. 3. When the drain side bit is read, control the potential of the gate to 1.5V, drain 43 to ground, select gate 31 to receive 18 volts, and source 42 to receive 5 volts. , Shi Xi substrate 3 is grounded. &, the channel below the source side will generate a dead zone, and the resistance value of the entire channel will be controlled by the amount of stored charge in the non-electrode side floating gate 36, and the stored position will be determined by reading the source current yuan. Similarly, when reading the source-side bit, control the potential of gate 38 to 1.5V, source 42 to ground, select gate 3 to receive a potential of 8V, and drain 43 to receive 1.5V. Potential, the silicon substrate 3 is grounded. At this time, the channel below the drain side will generate an empty region, and the resistance of the entire channel will be

Bits stored in 577172. Provided there is a higher one. Among them, the selection gate. At the same time, the fast operation of writing and reading memory cells is better implemented. This technique can be changed. The scope of patent is away from flashing speed. The operating cell has the action of connecting the gate memory cells. V. INTRODUCTION TO THE INVENTION (ίο) Judging by the 36-pole current of the source-side floating gate, the storage of the above is comprehensive. The structure and manufacturing method of the present invention have no need to operate the power in a control gate. Below the bottom, and can store two bit data, each bit system can separate the voltage and unit cell separately and flash the bit density. It has more than that. Although the present invention has been defined to limit the present invention, within any familiarity and scope, When some protection ranges can be made, it is controlled by the attached application load, and it is read by two kinds of bit memory bits. Each memory pole is isolated and floated because of the same difference between fetching and erasing. Speed and use cases are exposed as above, without desorption and retouching, because the defined ones are quasi-memory for speed two bits, so two of them have higher operation, not with a savvy guarantee. 0503-8775TWF (Nl); TSMC2002-0695; vincent.ptd Page 14 577172 Brief description of the diagram. Figure 1 shows a traditional unit. Figure 2 shows the structure of a traditional dual-bit memory. Flash memory structure, Figures 3A to 3E show the manufacturing process of the flash memory. In the example, the symbol of the two-bit split gate is 4 3 ~ source / drain; 1 la, 1 lb, 20a, 22a, 42 12 ~ channel; 13, 20b, 22b, 36 ~ floating gate; 1 4, 31 ~ select gate; 16a, 16b, 16b, 20d, 20e, 22d, 22e, 20f, 22f, 32, 33, 34, 35, 37, 39, 4b Insulation layer; 1 7, 2 0 c, 2 2 c, 3 8 ~ control gate; 20, 22, 24 ~ transistor; 2 6, 3 ~ substrate; 2 8 ~ word line; 4 0 ~ groove.

0503-8775TWF (Nl); TSMC2002-0695; vincent.ptd Page 15

Claims (1)

577172 VI. Scope of patent application1. A dual-bit discrete gate flash memory, including a substrate; β a selection gate located above the substrate; two poles: the first and second floating idle poles are located at Above the substrate and the selected closed electrode: control gates, located on the first and second floating gates and terminals, and 卞 J one: drain and source, located in the substrate and the selected gates, and- The second j is connected to both sides of a stacked layer formed by the gate electrode and the control gate electrode. The memory is a two-bit separation as described in its base, the quiescent flash interrogation system is a polycrystalline stone layer, the gate is connected to the first year, and the control is two-bit separation as described in the first range of the scope. The closed pole flash δ self-concealing body further includes a plurality of insulating layers that insulate the substrate, the selected closed pole, the first and second floating gates, and the control gate from each other. 5. The dual-bit split-gate fast memory as described in item 4 of the scope of patent application, wherein an interlayer oxide layer is formed between the selection gate and the substrate. 6. The dual-bit separation gate described in the patent application No. 4 is called the S-memory body, wherein a control layer (HTO) and an oxygen layer are included between the control gate and the selection gate. Nitrogen oxide layer (ONO). Gate / Dish ^ 7. Double-bit separation gate flashing as described in item 1 of the scope of the patent application. § Remembrance ’which further includes a tetraethylsilicate layer (TE0s), located in the control 0503-8775TWF (Nl); TSMC2002-0695; vincent.ptd Page 16 577172 6. Scope of patent application Above the gate. 8. · A kind of dual-bit separated gate flash memory is produced by the following steps: privately providing a substrate; forming a selection gate above the substrate; forming a first above the substrate and on both sides of the selection gate Disk-connected to the gate; Yi Leyang formed a # gate on top of the first floating gate and the selected gate; and ~ the control gate base and the selected gate, the first and second gates A drain and a source are formed on both sides of a stacked layer formed by the floating gate and the control gate. ^ 9 · The manufacturing method of the two-bit separation gate fast memory device as described in item 8 of the scope of the patent application, wherein the substrate is a silicon substrate. ^ 10. The method for manufacturing a two-bit split gate flash memory device as described in item 8 of the scope of the patent application, wherein the selection gate, the first 'second volume', and the control gate are polycrystalline silicon layers. 1 · The method for manufacturing a two-bit separated gate fast-recall body as described in the eighth patent claim, which further includes the following steps: 1. Forming a plurality of insulating layers, respectively, the substrate, the selected gate, the first, The second floating gate and the control gate are insulated from each other. 12. The double-bit separation gate flashes as described in item u of the patent application. A method for manufacturing a hidden body, wherein a gate oxide layer is formed between the selection gate and the substrate. '13. The double-bit separation gate extremely fast as described in item u of the scope of patent application i Page 17 0503-8775TW (Nl); TSMC2002 ^; vincen "577172 VI. Manufacturing method of the scope of patent application There is a high-temperature oxide layer (ΗΤ〇) and an oxygen-nitrogen-oxide layer (ΟΝΟ) between the control gate and the selection gate. 1 4 · Double bit as described in item 8 of the scope of patent application The manufacturing method of the split gate flash memory further includes the following steps: A tetraethyl silicate layer (TE0S) is formed above the control gate. 1 5 · — A kind of two-bit split gate flash memory A method for manufacturing a body includes the following steps: providing a substrate; forming a first conductive layer on the substrate; forming a second and third conductive layer on the substrate and on both sides of the first conductive layer; and on the second A third conductive layer forms a fourth conductive layer above the first conductive layer; and two sides of a stacked layer formed in the substrate and the first, second, third, and fourth conductive layers form a fourth conductive layer; The first and second doped regions. The method for manufacturing a dual-bit split gate flash memory as described in item 15 above, wherein the substrate is a silicon substrate. 17. The dual-bit split gate as described in item 15 of the patent application scope is fast A method for manufacturing a flash memory, wherein the first, second, third, and fourth conductive layers are polycrystalline silicon layers. 18. The dual-bit separated gate flash memory as described in item 15 of the scope of patent application. The manufacturing method further includes the following steps: forming a plurality of insulating layers to insulate the substrate, the first, second, third, and fourth conductive layers from each other. 0503-8775TWF (N1); TSMC2002-0695; vincen tp td page 18 577172 6. Application for patent scope 1 9 · Manufacturing method of dual-bit separated gate flash memory as described in item 18 of patent application scope A gate oxide layer is formed between the first conductive layer and the substrate. &Quot; 2 · According to the manufacturing method of the two-bit split gate flash memory described in item 18 of the patent application scope, wherein a high temperature oxidation exists between the fourth conductive layer and the first conductive layer Layer (HT0), and oxygen-nitrogen ~ oxide layer (ONO). 21 · The method for manufacturing a dual-bit separated gate flash memory as described in item 15 of the scope of patent application, further comprising the following steps: forming a 〆tetraethyl silicate layer over the fourth conductive layer (TE0S). 0503-8775TWF (Nl); TSMC2002-0695; Vincent.ptd p. 19