TW575965B - Tunnel bias metal-oxide-semiconductor transistor - Google Patents

Abstract

A tunneling-biased metal-oxide-semiconductor transistor, which is utilized in bulk and substrate with PD SOI to form a tunnel connection between gate terminal and substrate, is disclosed. In the transistor of the present invention, the gate base has a longer length than the one of normal transistor. Moreover, one terminal of the gate base has an ion implanted region whose electrical conductive type is inverted to another terminal of the gate. For example, the gate extension region of a NMOS is a P-type ion implanted region, and the gate extension region of a PMOS is an N-type ion implanted region. Therefore, the holes of the NMOS or the electrons of the PMOS can be tunneled from gate to substrate. Since the holes current has self-limited, the transistor of the present invention can be utilized when the operation voltage is larger than 0.7 V. Moreover, in the transistor of the present invention, there is no disadvantage of larger leakage current of traditional transistor. Otherwise, by utilizing the transistor structure of the present invention, the crosstalk phenomenon between the NMOS and PMOS can be avoided. The manufacturing method of the tunnel bias metal-oxide-semiconductor transistor is disclosed in the present invention also.

Description

575965 ----- Revision of sickle 91137 plus year, month, and day V. Description of the invention (1) — Technical field to which the invention belongs · The invention relates to the structure of metal-Oxide-Semiconductor Transistor (MOS) elements The invention also relates to a method for manufacturing the metal oxide semi-conductive crystal element structure and a method for manufacturing the same. Prior technology: In the past year, the rapid popularity of portable communication products and electronic products such as mobile phones, laptops, and electronic products has made the transfer of information faster, so people ’s demand for such products has increased significantly. In order to increase the convenience of portable communication products and electronic products, how to extend the battery so that one time becomes the focus of consideration in circuit design. Because the semiconductor industry ’s X-exposure test has rapidly increased the operating frequency and computing power of integrated circuits, the capacity of 2 devices and hard disks has increased dramatically, which has made portable communication products ^ electronic products. The enhancement also causes the power consumption of the system to become larger and larger. However, the storage capacity of batteries today cannot keep up with the speed of semiconductor manufacturing processes, and portable communication products and electronic products are limited by battery capacity and capacity. In addition, if the portable communication products and electronic products are stable and the S is too large, it will easily cause the internal temperature of the system to rise and the operating environment will be unsatisfactory. Especially, the smaller the size of the portable communication products and electronic products, the more likely it will occur.

= As can be seen, the size, weight, and use time of the battery have limited the development of circuit systems and memory storage devices for speed. Therefore, when it is desired to make the communications and electronic products lighter and thinner, it must be The direction of designing low power consumption circuits is moving forward. For the next generation of complementary metal oxide semiconducting ultra large integrated circuits ... W 575965

In terms of CMOS VLSI) process development, it is the development goal to make the circuit achieve low operating voltage and low power consumption. Among them, the use of low operating voltage can achieve good stability and lower power consumption. Due to the use of silicon-on-insulator (3111 (: 0) 1_〇11-111 other 1 & 1: 0; referred to as 801) process technology, the circuit has fast speed, low power consumption, high component density, The secondary effect (Second-Order Effect) is small, the radiation resistance is strong, and it can be compatible with the existing integrated circuit technology. Therefore, the Shi Xi process on the insulation layer is generally the best choice to achieve the above requirements.

In today's metal-oxide-semiconductor devices, only about a few hundred nanometers (nm) of the top-level silicon single crystal are used to make the device working area (Act i ve Uyer) for electron transport; The underlying silicon crystal serves as a mechanical support. Such a structure is likely to cause parasitic effects between the device and the substrate. In addition, it is very difficult to use a silicon substrate with semiconducting characteristics as the dielectric insulation (Dielectric lnsuiat0r). Therefore, the idea of a silicon process on the insulating layer was proposed, and an electrically insulating film was placed under the thin silicon single crystal element layer on the surface, and the element layer and the silicon substrate were separated, as shown in FIG. 1. FIG. 1 is a schematic cross-sectional view of a silicon substrate on an insulating layer. Please refer to FIG. 1, wherein the silicon substrate structure on the insulating layer is an insulating layer 12 formed on the original Shi Xi substrate 10. Next, an epitaxial si (14) is placed on the insulating layer (12), so as to form an insulating acoustic si substrate structure. In addition, due to the difference in thickness of the epitaxial silicon 14 on the insulating layer 12, there can be eight parts of the silicon on the partially (Partially Depleted; PD) insulating layer and the silicon on the insulating layer (Fully Depleted; FD for short). As shown in Figure 2 and Figure 3. Please refer to Figure 2, which is shown in Figure 2 as a partially empty multi-level secret, — __, not 575965 overlapping

Case No. 91137753 V. Description of the invention (3) Sectional view of the structure of Shi Xi on the layer. Among them, the substrate is composed of Shixi substrate 30, insulation sound 32, and epitaxial silicon 36, and an element working area is fabricated on the epitaxial silicon 36, and the component working area includes a gate 4 〇, source (source) 42, and drain (0 ^ 4) 44. The silicon on the partially empty insulating layer means that the depth of the empty region 38 of the element is smaller than the thickness of the epitaxial silicon 36. In addition, please refer to Figure 3, which shows the structure cross-section of silicon on a completely empty insulating layer. Among them, the "Shi Xi substrate 60 has an insulating layer 62, and a device working area having a gate 64 and a source 62 to 8", and the device working area is made of stupid silicon. Because the thickness of the epitaxial silicon in the silicon on the completely empty insulating layer is exactly the depth of the empty region of the element, the position of the epitaxial silicon, which is not shown in Fig. 3, overlaps with the position of the work area. In the above silicon with different insulation layers, the middle and eighth silicon devices can be operated at lower voltages and compared with the transmission: silicon yen has lower power loss, and this part can be easily used as an insulation layer. The silicon-on-silicon technology is completely transferred to the existing silicon technology, and the reference = the circuit design of silicon on the empty insulation layer must be properly revised, but it can effectively resist the soft error effect and is easy to make shallow junctions, compared to ^ The dream element on the insulation layer has better electrical performance. Therefore, manufacturers can choose according to their needs. Summary of the Invention: In order to achieve the development of a circuit with low operating voltage and low power consumption, one of the objects of the invention is to provide a transistor element that can be suitable for operation under low voltage and low power. The other purpose of the present invention is that the transistor device can be used under the operating conditions of room temperature and an operating voltage greater than 0.7V, and can avoid excessive junction leakage current (Junctin,

Leakage). In addition, the present invention further provides the above-mentioned transistor element.

y / 5965

For the purpose described above, the present invention provides a through-bias bias metal oxide transistor (TBM0S). The transistor structure of the present invention may be an N-type transistor or a jp-type transistor structure. The present invention is not limited thereto. Among them, taking N-type through-two-metal oxidized semi-conductive crystals as an example, the structure of the present invention includes: i-number 91137753 V. Manufacturing method of invention description (4). △ Main body This p-type main body has a top surface; a first insulating region extends from the top surface to isolate a volume in the p-type main body, thereby forming a P-well opposite to the two long sides-a closed pole seat, and a Λ gate electrode. One end of the block extends the well, and reaches the other end of the gate block; a dielectric layer is located between the gate U and the top surface; the -N type region is located in the P well structure, and the N type region is adjacent to the idler block. The long side of the N-type region has a source and a drain opposite to the source, and the source and the drain are located on the opposite sides of the gate electrode's long side: 萁 =: — ρ region is located in the N-type region On one side and surrounding one end of the gate, this p-type region forms a tunneling connection between the p-well structure and the gate seat. In the human flounder-type transitional metal oxide semi-conductive crystal, it can be used in a silicon (PD) substrate or a bulk (Buik) substrate on an insulating layer. Its-the silicon substrate on the empty insulation layer, the above structure further includes an edge region located in the ρ-type main body and a distance from the top mask, which is connected to the Ip formed under the first insulation region and is separated from the first insulation region. Even if t, then Shangcheng V :: Second must, regionally. If it is applied to the body substrate, the α-structure also includes a floating n-type deep well structure located on the p-type body carcass II: the dynamic I-type 'wood well structure is formed in the first insulation area and is separated from the first An insulation region is connected and is located under the P-well structure. The "electric layer" mentioned above may be selected from the group consisting of oxidized stone, nitrogen cut, and high dielectric constant 575965.

Upper = can be used as a group of gate dielectric materials, and the third 2 'marginal area is at least ^ full of an oxide layer-the ditch structure is a buried area Into the oxide layer (Buried Oxide) In addition, the thickness of the above dielectric layer is between _ to 5 and the thickness of block I is between 200 (m and 10 Α, the width of the gate seat: 1 ::: = ° 00 micron to 〇 · 05 micron t, the length of the pole block is between 4 ^ 4 I to 〇. 05 micron, and the distance between the first insulating region and the page above Is between 1 000 (½ to 100 A. In addition, the above-mentioned area has several acceptor ions (Accepter Ions), and the concentration of the acceptor ions is between 019 ions per square centimeter to 190 cm2丨 〇 ”ions. Using the tunneling bias metal oxide semi-conductive crystal of the present invention can be used when the power supply voltage is greater than 0.7 volts, in addition to reducing the contact area of the body, it also has a good current drive force (Current Drive) And smaller sub-threshold swings.

Referring to FIGS. 4 and 5, FIG. 4 is a top view of the layout of the n-type tunneling bias metal oxide semi-conductive crystal of the present invention, and FIG. 5 is a view of the N-type tunneling of FIG. 4 of the present invention. Equivalent circuit diagram of a tunnel biased metal oxide semiconducting crystal applied to a silicon substrate on a partially empty insulating layer. Please refer to FIG. 4, there is a gate base 1 2 8 on the p-type substrate 120, and the gate base 1 2 8 is respectively located in the N + ion implantation region and the adjacent P + ion implantation region. In addition, the opposite sources and drains in the N + ion implantation region are located on the upper and lower sides of the gate holder 1 2 8. Among them, the P + ion implantation region surrounding the 128-end of the gate base can form a tunneling connection between the p-type substrate 120 and the gate base 128. And Figure 7

Page 13 575965

First, a P-type substrate 120 having an insulating layer 122 is provided. The insulating layer 122 and the surface of the p-type substrate 120 are at a distance 124 from each other. This insulating layer is a buried oxide layer structure (Burie (j oxide; box), generally = silicon dioxide (Si〇2) can be used as a constituent material, the main reason is to consider the oxidation through silicon ..., one of the growth Silicon has better insulation characteristics, and it has the same manufacturing process as silicon wafer 575965 MM 91137753. Rev. 5. Description of invention (7) The integration is high, but the invention is not limited to this. Next, the p-type substrate 12. Another insulating region 130 is formed in the insulating region 130. The insulating region 130 may be formed by a trench structure filled with an oxide layer, and extends from the surface of the p-type substrate i 20 down to the insulating layer 1 2 2 and isolates a volume. Then, a p-well structure is formed. Then, a dielectric layer 126 is formed on the surface of the P-type substrate 120. In a preferred embodiment of the present invention, the thickness of the dielectric layer 126 is between 100 A and 100 A. The material of the dielectric layer 1 2 6 may be composed of, for example, an oxide dream, a nitrided nitride, or other electrical conductivity. The present invention is not limited to this. Then, a gate base 128 is further formed. On the dielectric layer 126, the gate base 28 is a diagonal line portion as shown in FIG. 4. In the present invention In a preferred embodiment, the thickness of the gate base 128 is between 2000a and 1300, the width is between 1000 micrometers and 0.005 micrometers, and the length is between丨 00 micrometers to 0: 005 micrometers. The gate holder 128 of the present invention is an elongated structure, one of which is: across the frost, and then extended to the other end. Then, the non- gated electrode is removed. Gate: implanted in an area. This N + ion implantation area is shaped by Society 2: The i-seat 128 overlaps and is on both sides of the gate-seat 128, which is to form a source and a drain opposite each other. Then, A further ion implantation step is performed, and the other π ions beside the N + ion implantation region of the receptor are implanted in the upper and middle regions of the middle and pelvis. In the present invention-preferred embodiment: we separate: f: The implantation concentration with N + ions is between about -end two = half. Page 15 575965 _ Case No. 91137753 V. Description of the invention (8) Oxidation penetration current in the layer r ion implantation area, and Ip + represents The tunneling current is oxidized in the P + ion implantation region of the polycrystalline silicon layer. The above description shows that the present invention is applied to a tunneling bias gold 2 of a silicon substrate on a partially empty insulating layer. The N-type structure of the semi-conductive crystal is shown in Fig. 8. The p-type tunneling bias metal oxide semi-conductive crystal of Fig. 7 of the present invention is applied to a silicon substrate on a partially empty insulating layer and along the B_B, the section line. Sectional view of the structure. According to FIG. 8, except for replacing the P-type substrate with an N-type substrate, and in the shape of the well region, and the position of the N + ion implantation area and the P + ion implantation area are reversed, other components Both are the same as the N-type tunneling bias metal oxide semi-conductive, so the present invention will not repeat them here. ^ It is worth noting that the above-mentioned N-type tunneling bias metal oxide semi-conductive crystal or P-type tunneling bias metal oxide of the present invention is described above. In the semi-conductive crystal, the shape of the gate base is only an example, and can be changed according to the needs of the product and the process. The present invention is not limited thereto. In addition, regardless of the N-type tunneling bias metal oxide semi-conductive crystal or the p-type tunneling bias metal oxide semi-conductive crystal, the N + ion implantation region and the p + ion implantation region are the same as those shown in FIGS. 4 and 7. It may be outside the two opposite-phase regions which are independent and not overlapping, or may overlap each other as shown in FIGS. 9 and 10, and the present invention is not limited thereto. The layout characteristics of the tunneling bias metal oxide semi-conductive crystal of the present invention are the extension of the gate base and the increase and presence of the gate dielectric layer and the thorium ion implantation area on the P-well structure, which can provide a tunneling connection. . Utilizing the characteristics of the tunneling bias metal oxide semiconducting crystal of the present invention, tunneling holes (Holes) can be provided in N-type tunneling bias metal oxide semiconducting crystals, so that when the element is in the initial state, it improves the Floating Body Potential. Similarly, 'applied to P-type tunneling bias metal oxide semiconductor 575965 No. 1 91137753 Λ ___ η Revision V. Description of the invention (9) Tunneling electrons can be provided in the transistor, so that when the element is in the initial state , Reduce the floating body potential. In addition, the excess carriers in the floating body will reduce the Threshold Voltage to obtain a higher current drive. After the experiment of the present invention, it is found that the tunneling bias metal oxide semi-conductive transistor of the present invention can greatly increase the saturation drain current (iD sat) and maintain a relatively good drain leakage current (IQff). In addition, when the gate voltage (Vg) is equal to the diode cut-off voltage (Vdd), the interface leakage current can be reduced, and when the element is in the Turn-On State, the floating body potential can be maintained at 0 · 7ν the following. Figure 11 shows the data comparison between a general dynamic threshold voltage metal oxide semi-conductive crystal (DTM0S) and the tunnel bias metal oxide semi-conductive crystal of the present invention applied to a silicon substrate on a partially empty insulating layer. Illustration. Please refer to the figure 丨 丨, where the curve X represents the relationship between the source / non-current of the transistor and the gate voltage, and the curve Y represents the current Invented the relationship between the source / dead current of the transistor and the gate voltage. According to the curve X and the curve ', it can be known that' dynamic critical voltage metal oxide semiconducting crystals that are generally used in the silicon process on a partially empty insulating layer, and when the operating voltage is too large, it may make the internal body of the device to the source (B. dy —source), or the diode junction (p —N Juncti〇n) between the body and the drain (Body-Drain), due to forward bias (Forward Bias), generates a large leakage current, which is limited to Use when operating voltage is less than 0 · 7 V. However, the tunneling bias metal oxide semi-conductive crystal of the present invention can be used when the cutoff voltage (Vdd) of the power supply is greater than 0.7V. The range is wider than the dynamic threshold voltage metal oxide semi-conductive crystal. Body contact area (Bodv Contact

Page 17 575965

Region). In addition, the tunneling bias metal oxide semi-conductive crystal of the present invention has the advantages of good current driving force and small subcritical fluctuation. The tunnel bias metal oxide semi-conductive crystal of the present invention is actually applied to a partially empty edge layer. Good component in silicon process. Say

The layout of the N-type or P-type tunneling bias metal oxide semi-conductive crystal of the present invention can be applied to a silicon substrate on a partially empty insulating layer, and can also be applied to a bulk (Bulk) substrate. As shown. FIG. 12 is a cross-sectional view of the structure of the N-type tunneling bias metal oxide semi-conductive crystal applied to the body substrate and taken along the AA ′ section line according to FIG. 4 of the present invention. The structure of the transistor will be described. Referring to FIG. 12, first, a P-type base material 162 is provided, and the following structure is formed in the P-type base material i 62: a plurality of insulating regions 164, and a floating type / not-well located between the insulating regions 164 (D eep-We 11) structure 1 6 6 and shallow retrograde P-well 168 on floating N-type deep well structure 166.

Among them, the above-mentioned insulation region 164 may be a shallow trench isolation structure, and the floating v-type deep well structure 166 located between the insulation regions 164 is not connected to each other, and the insulation region 164 is used for isolation. Next, a dielectric layer 170 is formed on the surface of the p-type substrate 162, and a gate base 172 is formed on the dielectric layer 170. This gate base is also distributed on the N + ions as shown by the diagonal line in FIG. 4 The implantation area and the p + ion implantation area. In addition, since the P-type structure does not have much difference except for the electrical adjustment, the present invention will not repeat them again. It is known that in the metal oxide semiconducting crystal using the bulk substrate, generally the deep well structure is located below the shallow trench isolation structure, and the diffusion well structure is located between the shallow trenches. Therefore, the p-type transistor made on the same substrate and N-type transistors easily cause crosstalk. And using the above-mentioned structure of the present invention, in addition to

Page 18 575965 case number—9113J753 __ Mang Λ 5. Description of the invention (11)

The transistor has its own floating deep well structure to avoid the crosstalk structure, and it can reduce the surface channels or surface contact points of the conventional deep well structure, which has the advantage of simplifying components. In addition, the above-mentioned tunneling bias metal oxide semi-conductive crystal applied to the bulk substrate has the same advantages as the Shi Xi substrate applied to the insulating layer, and can also be applied to an operating voltage greater than Q 7 volts, and Has good current driving force and small sub-critical fluctuations. As will be understood by those familiar with this technology, the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; ^ other completed without departing from the spirit disclosed by the present invention, etc. The effect or decoration should be included in the patent application scope described below. 3 > 575965 --- Case No. 9Π37753 Schematic description of the schema Schematic description of the invention: The preferred embodiment of the invention has been described in more detail in the foregoing explanatory text, in which: Schematic cross-section of the silicon substrate on the insulating layer = ^ The picture shows the structure of the silicon on the partially empty insulating layer and = the structure of the silicon on the insulating layer that is not completely empty =. The picture shows the N type of the invention Tunneling bias metal oxygen, layout top view; The figure of the 35 emulsified + conductive crystal is shown as the first type of wear-through bias of the present invention: the body is applied on a part of the empty insulating layer. Metallized Λ-Semiconducting Profile = The dream substrate on the insulation layer and along η, the section line is shown in Figure 8 of the p-type tunneling bias metal oxide semi-conductive crystal of the present invention. Invented the figure 卩, but the secret shot limit a crystal is applied to the part * / 丄 丄; Λ Λ through, bias metal oxide semiconducting cross-sectional view of the dream substrate on the insulating layer and along the line M, the knot i

Page 20 575965 Case No. 91137753 Revised diagram for simple comparison of data of semiconducting crystals; and Figure 12 shows the N-type tunneling bias metal oxide semiconducting crystal according to Figure 4 of the present invention A cross-sectional view of the structure applied to the body substrate and taken along the AA 'section line. Description of drawing number comparison: 10 broken substrate 12 insulation layer 14 30 silicon substrate 32 insulation layer 36 38 empty area 40 gate 42 source 44 drain 60 $ evening substrate 62 insulation layer 64 gate 66 source 68 drain 120 P-type substrate 122. Insulating layer 124 Distance 126 Dielectric layer 128 Gate base 130 Insulation area 150 N-type substrate 152 Insulation layer 154 Distance 156 Dielectric layer 158 Gate base 160 Insulation area 162 P-type substrate 164 Insulation Area 166 Floating N-type deep well structure 168 P-type shallow diffusion well 170 Dielectric layer 172 Gate base X curve Y curve

Page 21

Claims (1)

575965 Correction • An N-type tunneling bias metal oxide semi-conductive crystal (nTBM0 includes: a type body, wherein the P-type body has a top surface; a first insulation region is located in the P-type body and extends downward from the top surface To isolate a volume in the P-type body, thereby forming a p-well structure; having a gate base with two opposite long sides, wherein one end of the gate base extends across the P-well structure to the gate A dielectric layer is located between the gate base and the top surface; ⑯ an N-type area is located in the p-well structure, and the N-type area is adjacent to the long sides of the gate base, The N-type region has a source and a drain opposite to the source, and the source and the drain are located on opposite sides of the long sides of the gate base; and a P-type region It is located on one side of the N-type region and surrounds the other end of the gate block, wherein the P-type region forms a tunneling connection between the P-well structure and the gate block. 2. If applying for a patent The N-type tunneling bias metal oxide half-servo conductive crystal described in item 1 of the scope, The above-mentioned p-type main system is composed of a part of a PD SOI substrate on a vacant insulating layer. 3. The N-type tunneling bias metal oxide semi-conductive crystal described in the second item of the scope of the patent application, which has more A second insulation region is located in the P-type body and Page 575965 Modification ___ The top surface has a distance, wherein the second insulation region is located below the first edge region and connected to the first insulation region, and the P-well structure is located on the second insulation region. 4 Dao Rushen: The tunneling bias metal oxide half-type transistor described in item 3 of the patent scope, wherein the above-mentioned second insulating region is a buried oxide layer. 5 The conductivity is as straight as possible. The N-type tunneling bias metal oxidized as described in the third paragraph of Fan Λ is half distance away from the second insulation area where you enter the gate, and the distance from the top surface is between 1 00 00A to 10 ( Between ½. Electrical conductivity, application: specifically described in the first item _ wear-resisting bias metal oxidation semi-construction. The main system of the said type is conductive by a bulk (Bulk) substrate as described in the patent application The N-type tunneling bias metal-oxide semi-conserving transistor described in item 6 is more right-handed, and is equipped with 4 Φ /// movable N-type deep well structures located in the ρ-type body. The open, sigma structure is located in the limb isolated by the first insulation area, and continues underneath. /, Diyi insulation area is connected and located in the P-well structure • As the scope of the patent application Chu 1 κ ^ conductive The crystal, in which the tunneling bias metal oxide half mentioned in item Λ, and the dielectric layer on T can be selected from silicon oxide, nitride Page 23 575965 The material of the gate dielectric layer is made of broken, south ', or other materials, and can be used as a group. '9 · The conductive crystal according to item 1 of the scope of patent application, wherein the first at least one trench is formed. The N-type tunneling bias metal oxide semi-insulating region described above is filled by an oxide layer. It is said that the 1 ^ -type tunneling bias metal oxide semi-isoelectric day described in item 1 of the range of interest. The thickness of the electrical layer is between 100A and 5A. · 2 Lei Shenshen patented the scope of the tunneling bias metal oxidation described in item 1 The thickness of the above-mentioned gate base is between 2000 and i⑽. ^ Xue Li Shenyan's patent scope of the first type of tunneling bias metal oxide semi-oxidized body 'wherein the above The width of the gate base is between 1000 and 500 micrometers. 1 = · = The N-type tunneling bias metal oxide semi-electric crystal described in the first item of the patent application scope, wherein The length of the gate block is between 1000 micrometers and 0.005 micrometers. 14. The N-type tunneling bias metal oxide as described in item 1 of the scope of patent application. Page 24 575965-—- face 911377 welcome __year month day __ 6. Application for special fiber ® 'conductive crystal, where the above P-type region has a plurality of acceptor ions (Uccepter Ions), and these receptors The concentration of body ions is between 1019 ions per square centimeter and 1 (p ions per square centimeter). 15 · — A P-type tunneling bias metal oxide semi-conductive crystal (pTBM0s), including at least: An N-type body, wherein the n-type body has a top surface; a first insulating region is located in the N-type body and extends downward from the top surface to isolate a volume in the N-type body, thereby forming an N-well structure; A gate base having two opposite long sides, wherein one end of the gate base extends across the N-well structure to reach the other end of the gate base; a dielectric layer is located between the gate base and the top surface A P-type region is located in the N-well structure, and the p-type region is adjacent to the long sides of the gate base; ten of the P-type region has a source electrode and a drain electrode relative to the source electrode; And the source and the drain are located on opposite sides of the long sides of the gate base; and an N-type region is located on one side of the P-type region and surrounds the other end of the gate base , Wherein the N-type region forms a gap between the N-well region and the gate base. Article with connection. 16. The p-type tunneling bias metal oxide semi-conductive crystal according to item 15 of the scope of the patent application, wherein the above-mentioned N-type main system is composed of a silicon substrate on an insulating layer. earth Page 575965 ^ The p-type tunneling bias metal oxide as described in item 16 of the scope of patent application: 5 crystals, and a second insulating region is located in the N-type body and ... the top mask is a distance, where the first The two insulating regions are located below the first region and are connected to the first insulating region, and the junction structure is located on the second insulating region. Emperor's number 91137753 VI. Scope of patent application 1 Main 8 channels as described in item 17 of the scope of patent application? Type tunneling bias metal oxide layer conductive crystal, in which the above-mentioned second insulating region is a buried oxide 2 · Does it be as described in item 17 of Shen Jing's patent scope? Type tunneling bias metal oxide transistor, in which the above-mentioned second insulating region and the distance are between 1000 0A and 1 (m. Ju Zhi this = p-type as described in item 15 of the patent application scope of Dao Qing The tunneling bias metal is oxidized to form a transistor, in which the above-mentioned N-type main system is constituted by a bulk substrate U 逡 t (please refer to the 1 " type tunneling bias metal oxide body described in item 20 of the patent scope) A floating P-type deep well structure is located away from the N-type main body; two I-moving ?, type deep-well structures are located in the first insulating area, and are connected to the first insulating area, and are connected to the first insulating area, and Located under the N-well structure. Side I Page 26 575965 22. The p-type tunneling bias metal oxide semi-conductive crystal according to item 5 of the scope of the patent application, wherein the above-mentioned dielectric layer system may be selected from the group consisting of silicon oxide 'nitrogen &stone; high dielectric constant A group of materials or other materials that can be used as the gate dielectric layer. 23. The p-type tunneling bias metal oxide semi-conductive crystal according to item 5 of the scope of the patent application, wherein the first insulating region is formed by at least one trench filled with an oxide layer. 24. The p-type tunneling bias metal oxide semi-conductive crystal according to item 5 of the scope of the patent application, wherein the thickness of the above-mentioned dielectric layer is between 100A and H2. 25. The ρ-type tunneling biased metal oxide semi-conductive crystal according to item 5 of the scope of the patent application, wherein the thickness of the above-mentioned gate base is between 2000 (μ to 10 A. As applied The p-type tunneling biased metal oxide semi-conductive crystal described in item 5 of the patent scope, wherein the width of the above-mentioned gate block is between 1000 micrometers and 0.005 micrometers. The p-type tunneling bias metal oxide semi-conductive crystal according to item 15, wherein the length of the above-mentioned gate base is between 1000 micrometers and 0.05 micrometers. Page 27 575965 __Case No. 91137753_ Amendment Date 6 、 Applicable patent scope 28 · The p-type tunneling bias metal oxide semi-conductive crystal described in item 15 of the patent application scope, wherein the above-mentioned N-type region is There are a plurality of donor ions (Donor Ions), and the concentration of these donor ions is between 1019 ions per square centimeter and 1 (p ions per square centimeter). 29 ·-N-type tunneling bias A method for manufacturing a metal oxide semi-conductive crystal includes at least: providing a P-type substrate, wherein the P-type substrate has a top surface; Forming a first insulating region, and the first insulating region facing down from the top surface to isolate a volume in the P-type substrate, thereby forming a p-well structure; forming a dielectric layer on the top surface; Forming a gate base on the dielectric layer, wherein the gate base has two opposite long sides, and one end of the long sides extends across the P-well structure to the other end of one of the long sides; Except for the dielectric layer which is not covered by the gate base; implanting a plurality of donor ions in a first region, and the first region is overlapped with the long sides to form a source, And relative to the source A pole, and the source and the drain are located on opposite sides of the long sides of the gate base; and a plurality of body ions are implanted in a second region, and the second region is connected to the One end of the gate base is overlapped, thereby forming a through connection between a part of the p-well 'structure in the second region and a part of the gate base. Page 575965 = 邋 As described in item 29 of the patent scope, the manufacturing method of the 1 ^ -type tunneling bias metal oxide Ping A electric sun body, further includes forming a second insulating region in the \ earth material, and The top mask has a distance, wherein the second insulation region is formed under the first insulation region and is connected to the first insulation region, and the P-well structure is located on the second insulation region. 31. The manufacturing method of the N-type tunneling bias metal half-oxide and transistor as described in item 29 of the patent scope of the patent further includes forming a floating N-type deep well structure in the P-type body, wherein the floating N-type A deep well structure is formed in the volume isolated by the first insulation region, is connected to the first insulation region, and is located under the P-well structure. 32 * The method for manufacturing an N-type tunneling bias metal oxide semiconducting crystal as described in item 29 of the scope of the patent application, wherein the above-mentioned dielectric layer can be selected from the group consisting of stone oxide, silicon nitride, and high dielectric Coefficient materials or other materials that can be used as the gate dielectric layer. 33. The method for manufacturing an N-type tunneling bias metal oxide semiconducting crystal as described in item 29 of the scope of the patent application, wherein the thickness of the above-mentioned dielectric layer is between 10 and ½ to 34. If the patent is applied for The method for manufacturing an N-type tunneling bias metal oxide semi-conductive crystal according to item 29 of the scope, wherein the thickness of the above-mentioned gate base is between 200 (½ to 10 & The width is between 1000 microns to 575965 --- 91137753_ year, month, day, amendment 6, patent application range ~ &0; 0 0 5 micron. 35. As described in the 29th scope of the patent application A method for manufacturing an n-type tunneling bias metal oxide semi-conductive crystal, wherein the concentration of the donor ions implanted in the first region is between 109 ions per square centimeter and 10 02Q per square centimeter. 36. The method for manufacturing a tunneling bias metal oxide semiconducting crystal according to item 29 in the scope of the patent application, wherein the concentration of the acceptor ions implanted in the second region is intermediary. Between 109 ions per square centimeter and 102 02 ions per square centimeter 37. — The manufacturer of a P-type tunneling biased metal oxide semi-conductive crystal includes at least: providing an N-type substrate, wherein the N-type substrate has a top surface; The area extends downward from the top surface to isolate the 屮 __ ^ from the N-type substrate, thereby forming an N-well structure, forming a dielectric layer on the top surface, and forming a gate electrode. Sitting on the dielectric acoustic dagger, the basin has # long sides and the extensions of the long sides; the pole seat has the opposite two long sides-the other end; R extends across the n-well structure to the removals. The dielectric implanted part of the plurality of acceptor ions that are not covered by the gate block is in a first region, and the first region is related to I 575965 __tfu 91137753. _________ 6. The scope of patent application should be The long sides overlap to form a source and a drain relative to the source, and the source and the drain are located on opposite sides of the long sides of the gate base; and implanted A plurality of donor ions in a second region, and the second region is weighted with one end of the gate base To form a tunneling connection between a part of the N-well structure and a part of the gate block in the second region. 38. The P-type tunneling bias metal oxide semi-conductive as described in item 37 of the scope of patent application The method for manufacturing a crystal further includes forming a second insulating region in the N-type substrate and a distance from the top mask, wherein the second insulating region is formed under the first insulating region and is separated from the first insulating region. The insulation region is connected, and the N-well structure is located on the second insulation region. 39. The manufacturing method of the P-type tunneling bias metal oxide semi-conductive crystal described in item 37 of the scope of patent application, further comprising forming a floating The p-type deep well structure is in the N-type body, wherein the floating p-type deep well structure is formed in the volume isolated by the first insulation region, is connected to the first insulation region, and is located under the N-well structure. 40. For example, the method for manufacturing a semi-conductive crystal according to item 37 of the scope of application for a patent, the group consisting of silicon oxide, silicon nitride, and high-dielectric-based material. The aforementioned dielectric layer in the P-type tunneling bias metal oxidation described above may be selected from the group consisting of materials or other dielectrics that can be used as gate dielectrics. 575965 Emperor No. 911377W 6. Application for patent scope 41 Such as application for patent scope No. 37 The method for manufacturing a P-type tunneling bias metal oxide semi-conductive crystal according to the above item, wherein the thickness of the above-mentioned dielectric layer is between 100 & 42. The method for manufacturing a p-type tunneling bias metal oxide semiconducting crystal as described in item 37 of the scope of the patent application, wherein the thickness of the above-mentioned gate base is between 20000 A and 1 serving, and the gate The width of the seat is between 10000 microns and 0.005 microns. 43. As described in item 37 of the patent, a method for manufacturing a semi-conductive crystal, wherein the concentration of these acceptor ions is between 102 ions per cm. In the P-type tunneling bias metal oxidation described above, the implanted 1019 ions in the first region to the 44. As described in item 37 of the patent, a method for manufacturing a semi-conductive crystal, wherein the concentration of these donor ions is between 102 ions per cm. In the P-type tunneling bias metal oxidation described above, the implanted 1019 ions in the second region per square to Page 32