TW569657B - The structure of carrier and the structure of package - Google Patents
The structure of carrier and the structure of package Download PDFInfo
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- TW569657B TW569657B TW92107720A TW92107720A TW569657B TW 569657 B TW569657 B TW 569657B TW 92107720 A TW92107720 A TW 92107720A TW 92107720 A TW92107720 A TW 92107720A TW 569657 B TW569657 B TW 569657B
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- package substrate
- printed circuit
- package
- electrically connected
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
569657 五、發明說明(1) 發明所屬之技術領域 ’ 本發明是有關於一種承載器結構,且特別是有關於 一種封裝基板與可撓性印刷電路卷帶(F 1 e X i b 1 e P r i n t C i r c u i t F i 1 m )整合之承載器結構。 先前技術 近年來,隨著電子技術的日新月異,許多高科技電 子產業的相繼問世,使得更人性化、功能更佳的電子產 品不斷地推陳出新,且這些電子產品更不斷地朝向輕、-薄、短、小的趨勢設計發展。各種電子產品均具有至少 一主機板,其係由許多電子元件及電路板所構成,而電 路板之功能係在於搭載及電性連接各個電子元件,使得 這些電子元件能夠彼此電性連接,而目前最常見係為封 裝基板。 如上述,封裝基板主要由多個圖案化線路層及多個 絕緣層交替疊合所構成。其中,圖案化線路層例如由銅 箔層經過微影蝕刻定義形成,而絕緣層係配置於圖案化 線路層之間,用以保護並隔離圖案化線路層,並透過導 通孔(Plating Through Hole, PTH)或導電孔(Via)使得 各層圖案化線路層電性得以連接。此外,封裝基板的表 層會形成多個接點,用以做為封裝基板與外界電子元件 的接點。目前在半導體封裝結構中,封裝基板是經常使 用的封裝元件,其製作方式主要包括堆疊壓合式 (laminate)及積層式(build up)二大類型之製作方式。 由於封裝基板具有佈線細密、組裝緊湊以及性能良好等569657 V. Description of the invention (1) The technical field to which the invention belongs' The present invention relates to a carrier structure, and more particularly to a packaging substrate and a flexible printed circuit tape (F 1 e X ib 1 e Print C ircuit F i 1 m) integrated carrier structure. Previous technologies In recent years, with the rapid development of electronic technology, many high-tech electronic industries have come out one after another, making more humanized and better-functioning electronic products continue to be introduced, and these electronic products are more and more light, thin, short , Small trend design development. Various electronic products have at least one motherboard, which is composed of many electronic components and circuit boards, and the function of the circuit board is to carry and electrically connect various electronic components, so that these electronic components can be electrically connected to each other. At present, The most common is a package substrate. As described above, the package substrate is mainly composed of a plurality of patterned circuit layers and a plurality of insulation layers stacked alternately. The patterned circuit layer is defined by, for example, a copper foil layer and defined by lithographic etching, and an insulating layer is disposed between the patterned circuit layers to protect and isolate the patterned circuit layer and pass through a via (Plating Through Hole, PTH) or conductive holes (Via) enable the electrical connection of the patterned circuit layers. In addition, a plurality of contacts are formed on the surface of the package substrate to serve as contacts between the package substrate and external electronic components. At present, in a semiconductor package structure, a package substrate is a commonly used package component, and its manufacturing methods mainly include two types of manufacturing methods, namely, laminated and build-up. The package substrate has fine wiring, compact assembly, and good performance.
10794twf. ptd 第5頁 569657 五、發明說明(2) 優點,故封裝基板已成為晶片構裝之主流。 第1圖繪示習知之封裝基板的示意圖。請來照第1 圖,封裝基板1 0 0主要係由多個圖案化線路層1 1 〇、1 1 2以 及多個絕緣層1 0 2、1 0 4、1 〇 6、1 〇 8交替疊合所構成。其 中’絕緣層1 0 4為絕緣芯層’其材質例如為環氧基樹脂 等’而絕緣層1 0 2、1 0 6、1 〇 8之材質例如為環氧樹脂。另 外’圖案化線路層1 1 0、1 1 2、1 1 8例如由銅語經過微影蚀 刻製程定義形成,而圖案化線路層1丨〇、丨丨2、丨丨8之間係 透過配置於絕緣層中的導電孔1 1 4、1 2 0或導通孔1 1 6而形 成電性連接。 由上述之說明可知,不論是堆疊壓合式封裝基板或 積層式封裝基板’經過錢孔以及線路姓刻的方式以形成 圖案化線路層,並且經由鍍孔之孔壁以使各層圖案化線 路層之間能夠彼此電性連接。然而,此種利用導電孔或 導通孔以導通各層圖案化線路層的方式,會因為過多的 導電孔或導通孔,導致封裝基板在線路佈局時,線路必 須繞過導通孔,造成線路佈局的困難度。 此外’過多的導通孔會佔去大部分的封裝基板的面 積,,此若是要再增加其他電子元件於封裝基板上,必 須考量封裝基板有無足夠的面積將額外的電子元件(例如 被動元件等)配置於封裝基板上的問題。 發明内容 因此,本發明的目的在提出一種承載器結構,藉由 可撓性印刷電路卷帶以減少封裝基板上導通孔的數量,10794twf. Ptd Page 5 569657 V. Description of the invention (2) Advantages, so the package substrate has become the mainstream of wafer construction. FIG. 1 is a schematic diagram of a conventional package substrate. Please refer to the first figure. The package substrate 100 is mainly composed of a plurality of patterned circuit layers 1 1 0, 1 12 and a plurality of insulating layers 1 0 2, 1 0 4, 1 〇6, and 008. Composition. Among them, the "insulating layer 104 is an insulating core layer" whose material is, for example, an epoxy resin or the like, and the insulating layer 102, 106, 108 is, for example, an epoxy resin. In addition, the 'patterned circuit layer 1 1 0, 1 1 2, 1 1 8 is formed by, for example, copper language through a lithographic etching process definition, and the patterned circuit layer 1 丨 〇, 丨 丨 2, 丨 丨 8 is configured through transmission. Electrical connections are formed in the conductive holes 1 1 4, 1 2 0 or the through holes 1 1 6 in the insulating layer. From the above description, it can be known that, whether it is a stacked compression package substrate or a laminated package substrate, the patterned circuit layer is formed by engraving the money hole and the circuit name, and the hole wall of the plated hole is used to pattern each layer of the circuit layer Can be electrically connected to each other. However, this method of using conductive holes or vias to conduct patterning of the circuit layers will cause difficulties in circuit layout due to the excessive conductive holes or vias, which will cause the circuit to bypass the vias during the layout of the package substrate. degree. In addition, 'too many vias will occupy most of the area of the package substrate. If you want to add other electronic components to the package substrate, you must consider whether the package substrate has enough area to add additional electronic components (such as passive components). Problems with placement on a package substrate. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a carrier structure, which can reduce the number of via holes on a package substrate by using a flexible printed circuit tape.
10794twf. ptd10794twf. Ptd
IMI 第6頁 569657 五、 發明說明(3) 進 而 增 加 封 裝 基 板 上 線 路 佈 局 的 面 積 1 使 得 封 裝 基 板 上 可 以 有 更 多 的 電 子 元 件 電 性 連 接 〇 為 達 本 發 明 之 上 述 因 的 提 出 一 種 承 載 器 結 構 其 主 要 係 由 —一 封 裝 基 板 及 至 少 一 可 撓 性 印 刷 電 路 卷 帶 所 構 成 〇 其 中 封 裝 基 板 具 有 一 上 表 面 與 一 下 表 面 且 封 裝 基 板 具 有 多 數 圖 案 化 線 路 層 圖 案 化 線 路 層 的 其 中 二 層 係 分 別 配 置 於 上 表 面 與 下 表 面 上 〇 而 可 撓 性 印 刷 電 路 卷 帶 的 一 端 配 置 於 封 裝 基 板 的 上 表 面 上 J 且 可 撓 性 印 刷 電 路 卷 帶 的 另 一 端 配 置 於 封 裝 基 板 的 下 表 面 上 且 分 別 與 封 裝 基 板 之 圖 案 化 線 路 層 電 性 連 接 0 為 達 本 發 明 之 上 述 9 的 提 出 一 種 封 裝 結 構 ’ 其 主 要 係 由 一 承 載 器 至 少 一丨— 晶 片 一一 封 裝 材 料 及 多 數 個 銲 球 所 構 成 〇 其 中 上 述 之 承 載 器 主 要 係 由 一 封 裝 基 板 及 可 撓 性 印 刷 電 路 卷 帶 所 構 成 0 其 中 , 封 裝 基 板 具 有 —一 上 表 面 與 一 下 表 面 9 且 封 裝 基 板 具 有 多 數 個 圖 案 化 線 路 層 而 圖 案 化 線 路 層 的 其 中 二 層 係 分 別 配 置 於 上 表 面 上 與 下 表 面 上 〇 可 撓 性 印 刷 電 路 卷 帶 的 '―― 端 配 置 於 封 裝 基 板 的 上 表 面 上 而 其 另 一 端 配 置 於 封 裝 基 板 的 下 表 面 上 且 分 別 與 封 裝 基 板 之 圖 案 化 線 路 層 電 性 連 接 〇 此 外 晶 片 配 置 於 封 裝 基 板 之 上 表 面 上 而 且 晶 片 係 與 封 裝 基 板 電 性 連 接 , 其 中 晶 片 具 有 一 主 動 表 面 〇 另 外 藉 由 封 膠 材 料 用 以 包 覆 晶 片 及 部 分 之 封 裝 基 板 並 藉 由 銲 球 係 配 置 於 封 裝 基 板 的 下 表 面 上 J 使 得 銲 球 係 與 封 裝 基 板 電 性 連 接 〇IMI Page 6 569657 V. Description of the invention (3) Further increase the area of the circuit layout on the package substrate 1 so that more electronic components can be electrically connected on the package substrate. A carrier structure is proposed to achieve the above-mentioned reasons of the present invention. It is mainly composed of a package substrate and at least one flexible printed circuit tape. The package substrate has an upper surface and a lower surface and the package substrate has a plurality of patterned circuit layers. Two of the patterned circuit layers are respectively The flexible printed circuit tape is disposed on the upper surface and the lower surface. One end of the flexible printed circuit tape is disposed on the upper surface of the package substrate. The other end of the flexible printed circuit tape is disposed on the lower surface of the package substrate. The electrical connection of the patterned circuit layer of the package substrate is 0 to achieve the above 9 of the present invention. A packaging structure 'is mainly composed of a carrier, at least one of which is a wafer, a packaging material and a plurality of solder balls. The above-mentioned carrier is mainly composed of a packaging substrate and a flexible printed circuit tape. 0 Among them, the package substrate has an upper surface and a lower surface 9 and the package substrate has a plurality of patterned circuit layers, and two of the patterned circuit layers are disposed on the upper surface and the lower surface, respectively. Flexible printed circuits The '-' end of the tape is disposed on the upper surface of the packaging substrate and the other end thereof is disposed on the lower surface of the packaging substrate and is electrically connected to the patterned circuit layer of the packaging substrate. In addition, the chip is disposed on the upper surface of the packaging substrate And the chip is electrically connected to the package substrate, wherein the chip has an active surface. The material is used to cover the wafer and a part of the packaging substrate, and is arranged on the lower surface of the packaging substrate by a solder ball system, so that the solder ball system is electrically connected to the packaging substrate.
10794twf. ptd 第7頁 569657 五、發明說明(4) 依照本發明的較佳實施例所述,其中封裝基板具肴 多數個導電孔,導電孔係電性連接於圖案化線路層的其 中二層之間。此外,封裝基板具有多數個接點,其中這 些接點例如位於封裝基板的上表面與下表面上,且可撓 性印刷電路卷帶藉由這些接點電性連接至封裝基板上。 在本實施例中,封裝結構更包括多數個被動元件,而被 動元件例如配置於可撓性印刷電路卷帶上,且被動元件 係藉由可撓性印刷電路卷帶與封裝基板上之圖案化線路 層電性連接。其中,被動元件例如電容、電阻或電感 等。 依照本發明的較佳實施例所述,晶片與封裝基板之 間例如係藉由多條導線或是凸塊電性連接。 縱上所述,本發明之承載器結構中,藉由可撓性印 刷電路卷帶電性連接至封裝基板之上表面與下表面之圖 案化線路層,如此可減少封裝基板中導電孔或導通孔的 數量,進而提高封裝基板在線路佈局的使用面積。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂,下文特舉一較佳實施例,並配合所附圖式,作詳細 說明如下: 實施方式 第2圖繪示本發明之較佳實施例之封裝基板之剖面示 意圖。請參照第2圖,本發明之封裝基板2 0 0主要係由多 個圖案化線路層2 1 0、2 1 2、2 1 8、2 2 0 a、2 2 0 b以及多個絕 緣層2 0 2、2 0 4、2 0 6、2 0 8交替疊合所構成。其中,絕緣10794twf. Ptd Page 7 569657 V. Description of the invention (4) According to a preferred embodiment of the present invention, the packaging substrate includes a plurality of conductive holes, and the conductive holes are electrically connected to two of the patterned circuit layers. between. In addition, the package substrate has a plurality of contacts, wherein the contacts are located on the upper surface and the lower surface of the package substrate, for example, and the flexible printed circuit tape is electrically connected to the package substrate through the contacts. In this embodiment, the packaging structure further includes a plurality of passive components, and the passive components are disposed on a flexible printed circuit tape, for example, and the passive components are patterned by the flexible printed circuit tape and the package substrate. The line layer is electrically connected. Among them, passive components such as capacitors, resistors or inductors. According to a preferred embodiment of the present invention, the chip and the package substrate are electrically connected by, for example, a plurality of wires or bumps. As mentioned above, in the carrier structure of the present invention, the flexible printed circuit roll is electrically connected to the patterned circuit layer on the upper surface and the lower surface of the packaging substrate, so that the conductive holes or via holes in the packaging substrate can be reduced. The number of printed circuit boards can further increase the use area of the package substrate in the circuit layout. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to describe in detail as follows: Embodiment 2 FIG. 2 shows a comparison of the present invention. A schematic cross-sectional view of a package substrate of a preferred embodiment. Referring to FIG. 2, the package substrate 2 0 of the present invention is mainly composed of a plurality of patterned circuit layers 2 1 0, 2 1 2, 2 1 8, 2, 2 0 a, 2 2 0 b, and a plurality of insulating layers 2 0 2, 2 0 4, 2, 6 and 2 0 8 are alternately superimposed. Of which, insulation
10794twf.ptd 第8頁 56965710794twf.ptd Page 8 569657
五、發明說明(5) 層2 0 4為絕緣公層’其材λ例如為¥氧基樹脂或酸酿亞· a 等材質,而絕緣層2 0 2、2 0 6、2 0 8之材質例如為環氧樹= 荨材質。此外,封裝基板200具有一上表面207及一下夺 面2 0 9,且上述之圖案化線路層2 2 0 a係配置於封裝基才反 200之上表面207上,而且另一圖案化線路層22〇b係配置 於封裝基板2 0 0之下表面2 0 9上。值得注意的是,圖案化 線路層2 1 2、2 1 8、2 2 0 a、2 2 0 b之間係透過配置於絕緣芦 中2 0 2、2 0 6、2 0 8的導電孔214、2 2 0電性連接,或者亦曰可 以藉由導通孔2 1 6使得封裝基板2 0 0表層間的圖案化線路 層電性連接。 值得注意的是,絕緣層2 0 2、2 0 6、2 0 8係用以保護圖 案化線路層2 1 0、2 1 2,避免圖案化線路層2 1 0、2 1 2間產 生電性短路的情形。其中,絕緣層2 0 2、2 0 6、2 0 8之材質 例如是玻璃環氧基樹脂、雙順丁烯二酸醯亞胺或者環氧 樹脂(epoxy)等等材質。 第3圖繪示本發明之較佳實施例承載器之結構示意 圖。請參照第3圖,承載器結構5 0 0主要係由一封裝基板 2 0 0以及一可撓性印刷電路卷帶3 〇 〇所構成。其中,封裝 基板2 0 0上具有多數個接點2 〇 5,而接點2 0 5例如分別位於 封裝基板200之上表面207上及下表面209上,並與上述之 圖案化線路層220a、220b電性連接(見第2圖)。接著,下 文將以封裝基板2 0 0側緣之接點2 0 5為例來說明可撓性印 刷電路卷帶3 0 0與封裝基板2 0 〇的連接關係。 請同樣參照第2圖及第3圖,可撓性印刷電路卷帶3 0 0V. Description of the invention (5) The layer 2 0 4 is an insulating public layer. The material λ is, for example, a material such as ¥ oxy resin or acid brewer, and the material of the insulating layer 2 0 2, 2 0 6, 2 0 8 For example, epoxy tree = net material. In addition, the package substrate 200 has an upper surface 207 and a lower surface 209, and the above-mentioned patterned circuit layer 2 2 a is disposed on the upper surface 207 of the package substrate 200, and another patterned circuit layer 22b is disposed on the lower surface 209 of the package substrate 2000. It is worth noting that the patterned circuit layers 2 1 2, 2 1 8, 2, 2 0 a, 2 2 0 b pass through the conductive holes 214 arranged in the insulating reed 2 2 2, 2 0 6, 2 0 8 , 2 0 electrical connection, or the patterned circuit layer between the surface of the packaging substrate 200 can be electrically connected through the via 2 16. It is worth noting that the insulating layers 2 0, 2 0 6, 2 0 8 are used to protect the patterned circuit layers 2 1 0, 2 1 2 to avoid the electrical property between the patterned circuit layers 2 1 0, 2 1 2 Short circuit situation. Among them, the material of the insulating layer 20, 2, 06, and 2008 is, for example, glass epoxy resin, bismaleimide imide, or epoxy resin. Fig. 3 is a schematic diagram showing the structure of a carrier according to a preferred embodiment of the present invention. Referring to FIG. 3, the carrier structure 500 is mainly composed of a package substrate 200 and a flexible printed circuit tape 300. Among them, the package substrate 200 has a plurality of contacts 205, and the contacts 205 are respectively located on the upper surface 207 and the lower surface 209 of the package substrate 200, and are in contact with the patterned circuit layer 220a, 220b electrical connection (see Figure 2). Next, the connection relationship between the flexible printed circuit reel 3 0 0 and the packaging substrate 2 0 will be described below using the contact 2 05 on the side edge of the packaging substrate 2 0 as an example. Please also refer to Figures 2 and 3 for flexible printed circuit tape 3 0 0
569657 五、發明說明(6) 例如配置於封裝基板2 0 0之側緣上,其例如藉由表面黏·著 技術(surface mounting technology,SMT)的方式將可 撓性印刷電路卷帶3 0 0分別電性連接於封裝基板2 0 0之上 表面2 0 7上與下表面2 0 9上之接點2 0 5之間,換言之,封裝 基板200表層之圖案化線路層220a、220b電性連接可藉由 接點2 0 5與可撓性印刷電路卷帶3 0 0上的線路相連接。因 此,可撓性印刷電路卷帶3 0 0將可取代封裝基板2 〇 〇中部 份的圖案化線路層,也因此可以減少封裝基板2 〇 〇中導通 孔2 1 6的數目。此外,由於可撓性印刷電路卷帶3 〇 〇的配 置可以減少封裝基板2 0 0中導通孔2 1 6的數目,因此不但 可以使得承載器40 0中的封裝基板2 0 0具有較多的線路佈 局面積,而且在整體的線路佈局上將更具有彈性。 承上述,基於封裝集積度的考量,本實施例如可在 可撓性印刷電路卷帶3 〇 〇表面上配置多個被動元件3 〇 2或 是其他元件,這些被動元件3 0 2可以經由可撓性印刷電路 卷帶300中的線路與封裝基板2〇〇之圖案化線路層22〇a、 2 2 0,電性連接。值得注意的是,本實施例將被動元件3〇 2 或是其他元件設置於可撓性印刷電路卷帶3 〇 〇有別於習知 直接將被動元件3 0 2或其他元件直接設置於封裝基板2〇() ^的作法,其在佈局空間的利用上具有相當的優勢。此 外,上述之被動元件3〇2例如是電容、電阻、電感或是這 些元件的組合。 〜 =下將說明承載器結構5 0 0應用於封裝結 〇 式與其連接關係。569657 V. Description of the invention (6) For example, it is arranged on the side edge of the package substrate 2000, and it uses a surface mounting technology (SMT) to roll the flexible printed circuit tape 3 0 0 They are electrically connected between the upper surface 2 0 7 of the packaging substrate 2 0 and the contacts 2 0 5 on the lower surface 2 9 respectively. In other words, the patterned circuit layers 220 a and 220 b on the surface of the packaging substrate 200 are electrically connected. It can be connected to the line on the flexible printed circuit reel 300 by the contact 2 05. Therefore, the flexible printed circuit tape 300 will replace the patterned circuit layer in the middle of the packaging substrate 2000, and thus the number of vias 2 16 in the packaging substrate 2000 can be reduced. In addition, since the configuration of the flexible printed circuit tape 300 can reduce the number of via holes 2 16 in the package substrate 2000, not only can the package substrate 200 in the carrier 400 have more The layout area of the circuit will be more flexible in the overall circuit layout. Based on the above considerations, based on the consideration of the degree of package accumulation, for example, in this embodiment, a plurality of passive components 302 or other components can be arranged on the surface of the flexible printed circuit tape 300. These passive components 302 can be passed through the flexible The circuits in the flexible printed circuit tape 300 are electrically connected to the patterned circuit layers 22a, 220 of the package substrate 200. It is worth noting that, in this embodiment, the passive component 300 or other components are disposed on the flexible printed circuit tape 3, which is different from the conventional method of directly placing the passive component 320 or other components directly on the packaging substrate. The method of 20 () ^ has considerable advantages in the use of layout space. In addition, the aforementioned passive component 302 is, for example, a capacitor, a resistor, an inductor, or a combination of these components. ~ = The following will describe the carrier structure 5 0 0 applied to the packaging structure and its connection relationship.
569657 五、發明說明(7) -- 第4圖繪示本發明之承載器結構應用於打線球格陣列 封裝結構的不意圖。請參照第4圖,封裝結構4 〇 〇主 由一承載器結構5 0 0、一晶片6 0 0、一封膠材料(m〇if乐 compound ) 7 0 0及多數個銲球8〇〇所構成。其中,晶片6〇〇 係配置於封裝基板2 0 0之上表面2 〇 7上。此外,晶^ 6 〇 〇具 有一主動表面602及多數個銲墊6〇4,而銲墊604係位於^ 動表面6 0 2上。上述晶片6 0 0與封裝基板2 0 〇電性連接的方 式,例如藉由打線機(未繪示)將導線9 〇 〇由晶片5 〇 〇之主 動表面602上的銲墊6 04連接至封裝基板2 〇〇上之接合塾 230上,而導線900的材質例如是金等金屬。由於上述之 導線9 0 0很細而且密集度高,為了減少導線9 〇 〇或晶片6 〇 〇 受外力的碰撞,因此可藉由封膠材料7 〇 〇包覆整個晶片 6 0 0、導線9 0 0及部分的封裝基板2 0 0。接著,例如藉由植 球或網板印刷等方式,將銲球8 〇 〇係配置於封裝基板2 0 0 之下表面上2 0 9,使得銲球31 0與封裝基板2 0 0之電性連 接,因此,封裝基板2 0 0可藉由銲球31 0連接至下一層級 的電子裝置上,例如是印刷電路板等電子裝置。至於, 封裝基板2 0 0與可撓性印刷電路卷帶3 0 0的結構與其連接 關係,已在上文中有具體的說明,在此便不再贅述。 在本實施例中,承載器結構5 0 0除了可用於打線球格 陣列封裝結構外,亦可以運用於其他封裝結構,例如是 覆晶球格陣列封裝結構。第5圖繪示本發明之承載器結構 應用於覆晶球格陣列封裝結構的示意圖。請參照第5圖, 封裝結構1 〇 〇 〇例如具有多數個凸塊1 3 0 0,而凸塊1 3 0 0係569657 V. Description of the invention (7)-Figure 4 shows the intention of the carrier structure of the present invention applied to the ball grid array package structure. Please refer to FIG. 4. The package structure 400 is mainly composed of a carrier structure 500, a wafer 600, a plastic material (mfif compound) 700, and a plurality of solder balls 800. Make up. Among them, the wafer 600 is disposed on the upper surface 207 of the package substrate 2000. In addition, the crystal 602 has an active surface 602 and a plurality of pads 604, and the pad 604 is located on the moving surface 602. The aforementioned method of electrically connecting the chip 600 to the package substrate 2000 is to connect the wire 900 to the package with a bonding pad 6 04 on the active surface 602 of the chip 500 by a wire bonding machine (not shown). On the bonding substrate 230 on the substrate 2000, the material of the wire 900 is, for example, metal such as gold. Because the above-mentioned wire 900 is very thin and highly dense, in order to reduce the impact of the wire 900 or the wafer 600 on the external force, the entire wafer 600 and the wire 9 can be covered with a sealing material 700. 0 0 and part of the packaging substrate 2 0 0. Next, for example, by means of ball placement or screen printing, the solder ball 800 is arranged on the lower surface of the packaging substrate 2 0 2 to make the electrical properties of the solder ball 3 0 and the packaging substrate 2 0 0 Therefore, the package substrate 200 can be connected to the next-level electronic device, for example, an electronic device such as a printed circuit board, through the solder ball 3100. As for the structure and the connection relationship between the package substrate 200 and the flexible printed circuit tape 300, the specific relationship has been described above, and will not be repeated here. In this embodiment, in addition to the carrier structure 500, the carrier structure 500 can also be applied to other packaging structures, such as a flip-chip ball grid array packaging structure. FIG. 5 is a schematic diagram showing a carrier structure of the present invention applied to a flip-chip ball grid array packaging structure. Referring to FIG. 5, the package structure 1 〇 〇 〇 has a plurality of bumps 1 3 0 0, and the bumps 1 3 0 0
10794twf, ptd 第11頁 569657 五、發明說明(8) 位於晶片1 1 0 0與封裝基板1 2 0 0之間。其中,晶片1 1 0 0可 藉由凸塊1 3 0 0電性連接至封裝基板1 2 0 0上。此外,可在 晶片1 1 0 0與封裝基板1 2 〇 〇之間例如配置一填膠 (underfill)1400 ,用以緩衝封裝基板1200與晶片1100之 間在受熱時所產生的熱應變(thermal Strain)之不匹 配的現象。或者藉由封膠材料1 5 0 0包覆上述之晶片 1 1 0 0、凸塊1 3 0 0與部分之封膠材料1 5 0 0亦可以達成上述 填膠1400的目的。至於封裝結構1000之其他構件與連接 關係,如同第4圖中的説明’於此便不再贅述。 由上述之說明玎知,封裝基板上下表面上之圖案化 線路層可藉由可撓性印刷電路卷帶而彼此電性連接的關 係,使得封裝基板玎滅少使用導通孔來電性連接於圖案 化線路層,以減少封裝基板中導通孔的數量。此外,藉 由本發明之承載器結構設計’使封裝基板具有更多的線 路佈局面積,使得封裝基板上的線路設計上較有彈性, 因此封裝基板上可以容納更多1電子元件。 綜上所述,本發明之承載器結構至少具有下列優 點: 1.本發明各層圖案化線路層可藉由可撓性印刷電路 卷帶,使得封裝基板上之圖案化線路層彼此電性連接, 如此可避免使用導通孔’且減少封裝基板中導通孔的數 量,進而提高封裝基板設計佈局的面積。 2 ·本發明係藉由可換性印刷電路卷帶電性連接封裝 基板上下表面之圖案化線路層,使得封裝基板上的線路10794twf, ptd Page 11 569657 V. Description of the invention (8) It is located between the wafer 1 1 0 0 and the package substrate 1 2 0 0. The chip 1 1 0 can be electrically connected to the package substrate 1 2 0 through the bump 1 3 0. In addition, an underfill 1400 may be disposed between the wafer 1 100 and the package substrate 12 00, for example, to buffer thermal strain generated when the package substrate 1200 and the wafer 1100 are heated. ) Mismatch. Alternatively, the above-mentioned purpose of filling 1400 can also be achieved by encapsulating the above-mentioned wafer 1 1 0 0, bumps 1 3 0 0, and a part of the encapsulating material 15 0 0. As for the other components and connection relationships of the packaging structure 1000, like the description in FIG. 4, it will not be repeated here. From the above description, it is known that the patterned circuit layers on the upper and lower surfaces of the packaging substrate can be electrically connected to each other by flexible printed circuit tapes, so that the packaging substrate can be electrically connected to the patterning with fewer via holes. Circuit layer to reduce the number of vias in the package substrate. In addition, by using the carrier structure design of the present invention, the package substrate has more wiring layout area, so that the circuit design on the package substrate is more flexible, so the package substrate can accommodate more 1 electronic components. In summary, the carrier structure of the present invention has at least the following advantages: 1. Each layer of the patterned circuit layer of the present invention can be reeled by a flexible printed circuit, so that the patterned circuit layers on the packaging substrate are electrically connected to each other. In this way, the use of via holes can be avoided and the number of via holes in the package substrate can be reduced, thereby increasing the area of the package substrate design layout. 2 · The present invention electrically connects the patterned circuit layers on the upper and lower surfaces of the package substrate with a replaceable printed circuit roll, so that the circuits on the package substrate
10794twf. ptd 第12頁 569657 五、發明說明(9) 設計上較有彈性,因此封裝基板上可以容納更多的電子 元件。 雖然本發明已以一較佳實施例揭露如上,然其並非 用以限定本發明,任何熟習此技藝者,在不脫離本發明 之精神和範圍内,當可作各種之更動與潤飾,因此本發 明之保護範圍當視後附之申請專利範圍所界定者為準。10794twf. Ptd Page 12 569657 V. Description of the invention (9) The design is more flexible, so the package substrate can accommodate more electronic components. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.
10794twf. ptd 第13頁 569657 圖式簡單說明 圖式簡單說明 第1圖繪示習知之封裝基板的示意圖; 第2圖繪示本發明之較佳實施例之封裝基板之剖面示 意圖; 第3圖繪示本發明之較佳實施例承載器之結構示意 圖, 第4圖繪示本發明之承載器結構應用於打線球格陣列 封裝結構的不意圖,以及 第5圖繪示本發明之承載器結構應用於覆晶球格陣列 封裝結構的示意圖。 圖式標示說明 1 0 0 :封裝基板 1 0 2、1 0 4、1 0 6、1 0 8 :絕緣層 1 1 0、1 1 2、1 1 8 :圖案化線路層 1 1 4、1 2 0 :導電孔 1 1 6 :導通孔 2 0 0 :封裝基板 2 0 2、204 > 2 0 6 > 2 0 8 :絕緣層 2 0 5 :接點 2 0 7 ··上表面 2 0 9 :下表面 210、212、218、220a、220b ··圖案化線路層 2 1 4、2 2 0 :導電孔 2 3 0 :接合墊10794twf. Ptd Page 13 569657 Brief Description of Drawings Brief Description of Drawings Figure 1 shows a schematic diagram of a conventional package substrate; Figure 2 shows a cross-sectional diagram of a package substrate according to a preferred embodiment of the present invention; Figure 3 shows The schematic diagram of the structure of the carrier of the preferred embodiment of the present invention is shown in FIG. 4. FIG. 4 shows the intention of the carrier structure of the present invention applied to the ball grid array packaging structure, and FIG. 5 shows the application of the carrier structure of the present invention. Schematic diagram of a flip-chip ball grid array package structure. Graphical description: 1 0 0: package substrate 1 0 2, 1 0 4, 1 0 6, 1 0 8: insulation layer 1 1 0, 1 1 2, 1 1 8: patterned circuit layer 1 1 4, 1 2 0: conductive hole 1 1 6: via hole 2 0 0: package substrate 2 0 2, 204 > 2 0 6 > 2 0 8: insulating layer 2 0 5: contact 2 0 7 · upper surface 2 0 9 : Lower surface 210, 212, 218, 220a, 220b · patterned circuit layer 2 1 4, 2 2 0: conductive hole 2 3 0: bonding pad
10794twf. ptd 第14頁 56965710794twf.ptd p. 14 569657
圖式簡單說明 300 可撓性印刷電路卷帶 302 被動元件 400 封裝結構 500 承載器結構 600 晶片 602 主動表面 604 銲塾 700 封膠材料 800 鲜·球 900 導線 1000 封裝結構 1100 晶片 1200 封裝基板 1300 凸塊 1 4 0 0 : 填膠 1 5 0 0: 封膠材料 10794twf. ptd 第15頁Brief description of the drawing 300 Flexible printed circuit tape 302 Passive component 400 Package structure 500 Carrier structure 600 Wafer 602 Active surface 604 Solder pad 700 Sealant 800 Fresh ball 900 Wire 1000 Package structure 1100 Chip 1200 Package substrate 1300 Convex Block 1 4 0 0: Fill 1 5 0 0: Sealant 10794twf. Ptd Page 15
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TW92107720A TW569657B (en) | 2003-04-04 | 2003-04-04 | The structure of carrier and the structure of package |
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