TW569657B - The structure of carrier and the structure of package - Google Patents

Abstract

A structure of carrier comprises a substrate and at least a flexible print circuit film, wherein the substrate has a top surface and a bottom surface. The substrate has a plurality of patterned circuit layers which two of them are respectively disposed on the top surface and bottom surface. One end of the flexible print circuit film is disposed on the top surface and, another end of the flexible print circuit board is disposed on the bottom surface. The flexible circuit board is electrically connected to the patterned circuit layers.

Description

569657 V. Description of the invention (1) The technical field to which the invention belongs' The present invention relates to a carrier structure, and more particularly to a packaging substrate and a flexible printed circuit tape (F 1 e X ib 1 e Print C ircuit F i 1 m) integrated carrier structure. Previous technologies In recent years, with the rapid development of electronic technology, many high-tech electronic industries have come out one after another, making more humanized and better-functioning electronic products continue to be introduced, and these electronic products are more and more light, thin, short , Small trend design development. Various electronic products have at least one motherboard, which is composed of many electronic components and circuit boards, and the function of the circuit board is to carry and electrically connect various electronic components, so that these electronic components can be electrically connected to each other. At present, The most common is a package substrate. As described above, the package substrate is mainly composed of a plurality of patterned circuit layers and a plurality of insulation layers stacked alternately. The patterned circuit layer is defined by, for example, a copper foil layer and defined by lithographic etching, and an insulating layer is disposed between the patterned circuit layers to protect and isolate the patterned circuit layer and pass through a via (Plating Through Hole, PTH) or conductive holes (Via) enable the electrical connection of the patterned circuit layers. In addition, a plurality of contacts are formed on the surface of the package substrate to serve as contacts between the package substrate and external electronic components. At present, in a semiconductor package structure, a package substrate is a commonly used package component, and its manufacturing methods mainly include two types of manufacturing methods, namely, laminated and build-up. The package substrate has fine wiring, compact assembly, and good performance.

10794twf. Ptd Page 5 569657 V. Description of the invention (2) Advantages, so the package substrate has become the mainstream of wafer construction. FIG. 1 is a schematic diagram of a conventional package substrate. Please refer to the first figure. The package substrate 100 is mainly composed of a plurality of patterned circuit layers 1 1 0, 1 12 and a plurality of insulating layers 1 0 2, 1 0 4, 1 〇6, and 008. Composition. Among them, the "insulating layer 104 is an insulating core layer" whose material is, for example, an epoxy resin or the like, and the insulating layer 102, 106, 108 is, for example, an epoxy resin. In addition, the 'patterned circuit layer 1 1 0, 1 1 2, 1 1 8 is formed by, for example, copper language through a lithographic etching process definition, and the patterned circuit layer 1 丨 〇, 丨 丨 2, 丨 丨 8 is configured through transmission. Electrical connections are formed in the conductive holes 1 1 4, 1 2 0 or the through holes 1 1 6 in the insulating layer. From the above description, it can be known that, whether it is a stacked compression package substrate or a laminated package substrate, the patterned circuit layer is formed by engraving the money hole and the circuit name, and the hole wall of the plated hole is used to pattern each layer of the circuit layer Can be electrically connected to each other. However, this method of using conductive holes or vias to conduct patterning of the circuit layers will cause difficulties in circuit layout due to the excessive conductive holes or vias, which will cause the circuit to bypass the vias during the layout of the package substrate. degree. In addition, 'too many vias will occupy most of the area of the package substrate. If you want to add other electronic components to the package substrate, you must consider whether the package substrate has enough area to add additional electronic components (such as passive components). Problems with placement on a package substrate. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a carrier structure, which can reduce the number of via holes on a package substrate by using a flexible printed circuit tape.

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IMI Page 6 569657 V. Description of the invention (3) Further increase the area of the circuit layout on the package substrate 1 so that more electronic components can be electrically connected on the package substrate. A carrier structure is proposed to achieve the above-mentioned reasons of the present invention. It is mainly composed of a package substrate and at least one flexible printed circuit tape. The package substrate has an upper surface and a lower surface and the package substrate has a plurality of patterned circuit layers. Two of the patterned circuit layers are respectively The flexible printed circuit tape is disposed on the upper surface and the lower surface. One end of the flexible printed circuit tape is disposed on the upper surface of the package substrate. The other end of the flexible printed circuit tape is disposed on the lower surface of the package substrate. The electrical connection of the patterned circuit layer of the package substrate is 0 to achieve the above 9 of the present invention. A packaging structure 'is mainly composed of a carrier, at least one of which is a wafer, a packaging material and a plurality of solder balls. The above-mentioned carrier is mainly composed of a packaging substrate and a flexible printed circuit tape. 0 Among them, the package substrate has an upper surface and a lower surface 9 and the package substrate has a plurality of patterned circuit layers, and two of the patterned circuit layers are disposed on the upper surface and the lower surface, respectively. Flexible printed circuits The '-' end of the tape is disposed on the upper surface of the packaging substrate and the other end thereof is disposed on the lower surface of the packaging substrate and is electrically connected to the patterned circuit layer of the packaging substrate. In addition, the chip is disposed on the upper surface of the packaging substrate And the chip is electrically connected to the package substrate, wherein the chip has an active surface. The material is used to cover the wafer and a part of the packaging substrate, and is arranged on the lower surface of the packaging substrate by a solder ball system, so that the solder ball system is electrically connected to the packaging substrate.

10794twf. Ptd Page 7 569657 V. Description of the invention (4) According to a preferred embodiment of the present invention, the packaging substrate includes a plurality of conductive holes, and the conductive holes are electrically connected to two of the patterned circuit layers. between. In addition, the package substrate has a plurality of contacts, wherein the contacts are located on the upper surface and the lower surface of the package substrate, for example, and the flexible printed circuit tape is electrically connected to the package substrate through the contacts. In this embodiment, the packaging structure further includes a plurality of passive components, and the passive components are disposed on a flexible printed circuit tape, for example, and the passive components are patterned by the flexible printed circuit tape and the package substrate. The line layer is electrically connected. Among them, passive components such as capacitors, resistors or inductors. According to a preferred embodiment of the present invention, the chip and the package substrate are electrically connected by, for example, a plurality of wires or bumps. As mentioned above, in the carrier structure of the present invention, the flexible printed circuit roll is electrically connected to the patterned circuit layer on the upper surface and the lower surface of the packaging substrate, so that the conductive holes or via holes in the packaging substrate can be reduced. The number of printed circuit boards can further increase the use area of the package substrate in the circuit layout. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to describe in detail as follows: Embodiment 2 FIG. 2 shows a comparison of the present invention. A schematic cross-sectional view of a package substrate of a preferred embodiment. Referring to FIG. 2, the package substrate 2 0 of the present invention is mainly composed of a plurality of patterned circuit layers 2 1 0, 2 1 2, 2 1 8, 2, 2 0 a, 2 2 0 b, and a plurality of insulating layers 2 0 2, 2 0 4, 2, 6 and 2 0 8 are alternately superimposed. Of which, insulation

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V. Description of the invention (5) The layer 2 0 4 is an insulating public layer. The material λ is, for example, a material such as ¥ oxy resin or acid brewer, and the material of the insulating layer 2 0 2, 2 0 6, 2 0 8 For example, epoxy tree = net material. In addition, the package substrate 200 has an upper surface 207 and a lower surface 209, and the above-mentioned patterned circuit layer 2 2 a is disposed on the upper surface 207 of the package substrate 200, and another patterned circuit layer 22b is disposed on the lower surface 209 of the package substrate 2000. It is worth noting that the patterned circuit layers 2 1 2, 2 1 8, 2, 2 0 a, 2 2 0 b pass through the conductive holes 214 arranged in the insulating reed 2 2 2, 2 0 6, 2 0 8 , 2 0 electrical connection, or the patterned circuit layer between the surface of the packaging substrate 200 can be electrically connected through the via 2 16. It is worth noting that the insulating layers 2 0, 2 0 6, 2 0 8 are used to protect the patterned circuit layers 2 1 0, 2 1 2 to avoid the electrical property between the patterned circuit layers 2 1 0, 2 1 2 Short circuit situation. Among them, the material of the insulating layer 20, 2, 06, and 2008 is, for example, glass epoxy resin, bismaleimide imide, or epoxy resin. Fig. 3 is a schematic diagram showing the structure of a carrier according to a preferred embodiment of the present invention. Referring to FIG. 3, the carrier structure 500 is mainly composed of a package substrate 200 and a flexible printed circuit tape 300. Among them, the package substrate 200 has a plurality of contacts 205, and the contacts 205 are respectively located on the upper surface 207 and the lower surface 209 of the package substrate 200, and are in contact with the patterned circuit layer 220a, 220b electrical connection (see Figure 2). Next, the connection relationship between the flexible printed circuit reel 3 0 0 and the packaging substrate 2 0 will be described below using the contact 2 05 on the side edge of the packaging substrate 2 0 as an example. Please also refer to Figures 2 and 3 for flexible printed circuit tape 3 0 0

569657 V. Description of the invention (6) For example, it is arranged on the side edge of the package substrate 2000, and it uses a surface mounting technology (SMT) to roll the flexible printed circuit tape 3 0 0 They are electrically connected between the upper surface 2 0 7 of the packaging substrate 2 0 and the contacts 2 0 5 on the lower surface 2 9 respectively. In other words, the patterned circuit layers 220 a and 220 b on the surface of the packaging substrate 200 are electrically connected. It can be connected to the line on the flexible printed circuit reel 300 by the contact 2 05. Therefore, the flexible printed circuit tape 300 will replace the patterned circuit layer in the middle of the packaging substrate 2000, and thus the number of vias 2 16 in the packaging substrate 2000 can be reduced. In addition, since the configuration of the flexible printed circuit tape 300 can reduce the number of via holes 2 16 in the package substrate 2000, not only can the package substrate 200 in the carrier 400 have more The layout area of the circuit will be more flexible in the overall circuit layout. Based on the above considerations, based on the consideration of the degree of package accumulation, for example, in this embodiment, a plurality of passive components 302 or other components can be arranged on the surface of the flexible printed circuit tape 300. These passive components 302 can be passed through the flexible The circuits in the flexible printed circuit tape 300 are electrically connected to the patterned circuit layers 22a, 220 of the package substrate 200. It is worth noting that, in this embodiment, the passive component 300 or other components are disposed on the flexible printed circuit tape 3, which is different from the conventional method of directly placing the passive component 320 or other components directly on the packaging substrate. The method of 20 () ^ has considerable advantages in the use of layout space. In addition, the aforementioned passive component 302 is, for example, a capacitor, a resistor, an inductor, or a combination of these components. ~ = The following will describe the carrier structure 5 0 0 applied to the packaging structure and its connection relationship.

569657 V. Description of the invention (7)-Figure 4 shows the intention of the carrier structure of the present invention applied to the ball grid array package structure. Please refer to FIG. 4. The package structure 400 is mainly composed of a carrier structure 500, a wafer 600, a plastic material (mfif compound) 700, and a plurality of solder balls 800. Make up. Among them, the wafer 600 is disposed on the upper surface 207 of the package substrate 2000. In addition, the crystal 602 has an active surface 602 and a plurality of pads 604, and the pad 604 is located on the moving surface 602. The aforementioned method of electrically connecting the chip 600 to the package substrate 2000 is to connect the wire 900 to the package with a bonding pad 6 04 on the active surface 602 of the chip 500 by a wire bonding machine (not shown). On the bonding substrate 230 on the substrate 2000, the material of the wire 900 is, for example, metal such as gold. Because the above-mentioned wire 900 is very thin and highly dense, in order to reduce the impact of the wire 900 or the wafer 600 on the external force, the entire wafer 600 and the wire 9 can be covered with a sealing material 700. 0 0 and part of the packaging substrate 2 0 0. Next, for example, by means of ball placement or screen printing, the solder ball 800 is arranged on the lower surface of the packaging substrate 2 0 2 to make the electrical properties of the solder ball 3 0 and the packaging substrate 2 0 0 Therefore, the package substrate 200 can be connected to the next-level electronic device, for example, an electronic device such as a printed circuit board, through the solder ball 3100. As for the structure and the connection relationship between the package substrate 200 and the flexible printed circuit tape 300, the specific relationship has been described above, and will not be repeated here. In this embodiment, in addition to the carrier structure 500, the carrier structure 500 can also be applied to other packaging structures, such as a flip-chip ball grid array packaging structure. FIG. 5 is a schematic diagram showing a carrier structure of the present invention applied to a flip-chip ball grid array packaging structure. Referring to FIG. 5, the package structure 1 〇 〇 〇 has a plurality of bumps 1 3 0 0, and the bumps 1 3 0 0

10794twf, ptd Page 11 569657 V. Description of the invention (8) It is located between the wafer 1 1 0 0 and the package substrate 1 2 0 0. The chip 1 1 0 can be electrically connected to the package substrate 1 2 0 through the bump 1 3 0. In addition, an underfill 1400 may be disposed between the wafer 1 100 and the package substrate 12 00, for example, to buffer thermal strain generated when the package substrate 1200 and the wafer 1100 are heated. ) Mismatch. Alternatively, the above-mentioned purpose of filling 1400 can also be achieved by encapsulating the above-mentioned wafer 1 1 0 0, bumps 1 3 0 0, and a part of the encapsulating material 15 0 0. As for the other components and connection relationships of the packaging structure 1000, like the description in FIG. 4, it will not be repeated here. From the above description, it is known that the patterned circuit layers on the upper and lower surfaces of the packaging substrate can be electrically connected to each other by flexible printed circuit tapes, so that the packaging substrate can be electrically connected to the patterning with fewer via holes. Circuit layer to reduce the number of vias in the package substrate. In addition, by using the carrier structure design of the present invention, the package substrate has more wiring layout area, so that the circuit design on the package substrate is more flexible, so the package substrate can accommodate more 1 electronic components. In summary, the carrier structure of the present invention has at least the following advantages: 1. Each layer of the patterned circuit layer of the present invention can be reeled by a flexible printed circuit, so that the patterned circuit layers on the packaging substrate are electrically connected to each other. In this way, the use of via holes can be avoided and the number of via holes in the package substrate can be reduced, thereby increasing the area of the package substrate design layout. 2 · The present invention electrically connects the patterned circuit layers on the upper and lower surfaces of the package substrate with a replaceable printed circuit roll, so that the circuits on the package substrate

10794twf. Ptd Page 12 569657 V. Description of the invention (9) The design is more flexible, so the package substrate can accommodate more electronic components. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

10794twf. Ptd Page 13 569657 Brief Description of Drawings Brief Description of Drawings Figure 1 shows a schematic diagram of a conventional package substrate; Figure 2 shows a cross-sectional diagram of a package substrate according to a preferred embodiment of the present invention; Figure 3 shows The schematic diagram of the structure of the carrier of the preferred embodiment of the present invention is shown in FIG. 4. FIG. 4 shows the intention of the carrier structure of the present invention applied to the ball grid array packaging structure, and FIG. 5 shows the application of the carrier structure of the present invention. Schematic diagram of a flip-chip ball grid array package structure. Graphical description: 1 0 0: package substrate 1 0 2, 1 0 4, 1 0 6, 1 0 8: insulation layer 1 1 0, 1 1 2, 1 1 8: patterned circuit layer 1 1 4, 1 2 0: conductive hole 1 1 6: via hole 2 0 0: package substrate 2 0 2, 204 > 2 0 6 > 2 0 8: insulating layer 2 0 5: contact 2 0 7 · upper surface 2 0 9 : Lower surface 210, 212, 218, 220a, 220b · patterned circuit layer 2 1 4, 2 2 0: conductive hole 2 3 0: bonding pad

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Brief description of the drawing 300 Flexible printed circuit tape 302 Passive component 400 Package structure 500 Carrier structure 600 Wafer 602 Active surface 604 Solder pad 700 Sealant 800 Fresh ball 900 Wire 1000 Package structure 1100 Chip 1200 Package substrate 1300 Convex Block 1 4 0 0: Fill 1 5 0 0: Sealant 10794twf. Ptd Page 15

Claims (1)

569657 VI. Scope of patent application 1. A carrier structure including at least: a package substrate having an upper surface and a lower surface, and the package substrate having a plurality of patterned circuit layers, wherein The two layers are respectively disposed on the upper surface and the lower surface; and at least one flexible printed circuit tape, one end of the flexible printed circuit tape is disposed on the upper surface of the package substrate, and the The other end of the flexible printed circuit tape is disposed on the lower surface of the package substrate, and is electrically connected to the patterned circuit layers of the package substrate, respectively. 2. The carrier structure according to item 1 of the scope of patent application, wherein the package substrate has a plurality of conductive holes, and the conductive holes are electrically connected between two of the patterned circuit layers. 3. According to the carrier structure described in item 1 of the scope of patent application, the package substrate has a plurality of contacts, wherein the contacts are located on the upper surface and the lower surface of the package substrate, and the flexibility The printed circuit tape is electrically connected to the contacts. 4. The carrier structure described in item 1 of the scope of patent application, further comprising a plurality of passive components, wherein the passive components are arranged on the flexible printed circuit tape, and the passive components are provided by the The flexible printed circuit tape is electrically connected to the patterned circuit layers on the package substrate. 5. The carrier structure described in item 4 of the patent application scope, wherein the passive components include capacitors, resistors and inductors. 10794twf. Ptd Page 16 569657 6. Scope of patent application 6.-A package structure including at least: a carrier structure, wherein the carrier structure includes: a package substrate, the package substrate has an upper surface and a lower surface, and The package substrate has a plurality of patterned circuit layers, wherein two layers of the patterned circuit layers are respectively disposed on the upper surface and the lower surface; at least one flexible printed circuit tape, the flexible printed circuit One end of the tape is disposed on the upper surface of the packaging substrate, and the other end of the flexible printed circuit tape is disposed on the lower surface of the packaging substrate, and is separately connected to the patterned circuits of the packaging substrate. Layer electrical connection; at least one chip is disposed on the upper surface of the package substrate, the chip is electrically connected to the package substrate, wherein the chip has an active surface; an adhesive material covers the chip and part The package substrate; and a plurality of solder balls disposed on the lower surface of the package substrate, wherein the solder balls are electrically connected to the package substrate . 7. The package structure according to item 6 of the scope of the patent application, wherein the package substrate has a plurality of conductive holes, and the conductive holes are electrically connected between two of the patterned circuit layers. 8. The package structure described in item 6 of the scope of patent application, the package substrate has a plurality of contacts, wherein the contacts are located on the upper surface and the lower surface of the package substrate, and the flexibility Printed circuit tape system 10794twf. Ptd Page 17 569657 6. Scope of patent application Electrically connected to these contacts. 9. The package structure according to item 6 of the scope of patent application, further comprising a plurality of wires, each of which is electrically connected to the package substrate by the active surface of the chip, respectively. 10. The package structure described in item 6 of the scope of patent application, further includes a plurality of bumps, wherein the bumps are arranged between the wafer and the package substrate, and the wafer is connected by the bumps and The package substrate is electrically connected. 1 1. The package structure according to item 6 of the scope of patent application, wherein the carrier further includes a plurality of passive components, wherein the passive components are arranged on the flexible printed circuit tape, and the passive components The flexible printed circuit tape is electrically connected to the patterned circuit layers on the package substrate. 12 2. The package structure according to item 11 of the scope of patent application, wherein the passive components include capacitors, resistors and inductors. 10794twf ‘ptd page 18