TW569417B - Integrated circuit chip and protection method for preventing an NMOS of a core circuit from ESD damage - Google Patents

Abstract

The present invention relates to a protection method for preventing an NMOS of a core circuit from ESD damage, which includes the following steps: detecting all the NMOS elements directly connected to the thin gate with logical voltage level as 1; coupling the gates of all the detected NMOS with thin gates to the voltage with logical level as 1 through the PMOS with thick gates; and, grounding the gates of PMOS with thick gates. Thus, the method employs the higher gate oxide breakdown voltage of PMOS with thick gates to enhance the ESD protection of the whole chip.

Description

569417 V. Description of the invention (1) Background of the invention The present invention relates to a method for protecting against electrostatic discharge, in particular, to protect the N-type metal oxide semiconductor element (NM0s) in the internal circuit from damage caused by electrostatic discharge. Method, which uses an element with an isolation / buffering function to avoid the occurrence of failure of internal devices (core devices) from being damaged by excessive electrical stress. Electrostatic discharge can cause damage to complementary metal-oxide-semiconductor integrated circuits (CMOS 1C), leading to well-known reliability issues. As CMOS process technology shrinks to the sub-micron stage, advanced process technologies, such as thinner gate oxide layers, shorter channel lengths, shallower electrode / source junction depth, and low doping concentration drain ( LDD) structure and metal silicide (siliC1ded) diffusion layer, etc. These advanced processes have seriously reduced the electrostatic discharge protection of sub-micron CMOS ICs. " Figure 1 is a block diagram of a complementary metal rolled semiconductor (CMOS) circuit including a typical electrostatic discharge protection device. In Figure i, this circuit contains an input (out) pin or pad (input / 〇utput pins 〇r

PadS) 11, electrostatic discharge protection devices 13, 16 and a physical element (a CMO element in this example) 15 in the internal circuit, where the device 13 is connected to the component " Connected between the input operating voltage CoreVdd and CoreVss. As shown in Figure 丨, the design of a typical electrostatic discharge protection device is mostly configured on the input (out) pin or side and the internal operating voltage to separate (out, pin or pad and the internal circuit to avoid being directly affected. Or indirect: discharge damage. However, 'this protection method for the above-mentioned minor =

569417 V. Description of the invention (2) 1 is enough. For example, this type of integrated circuit is more and more conductive and the core voltage is smaller as t is the voltage. The p-type and n-type metal oxides (yak and yak) and N1 are gate thin oxide layers (gate). : The thinner the thickness is, the faster the operating speed of the internal circuit of cm〇s ic is 2: ". However, the thinner the gate oxide layer (gate 〇xide) becomes, the more the property is affected by the electrostatic discharge. Exceeding the power of the gate oxidation breakdown voltage causes product reliability issues. For example, in order to overcome the so-called hot carrier problem, the Mi-Tech technology often adds the above-mentioned low doping concentration in the CMOS process. (L is the structure. Du, the above-mentioned LDD structure is made at both ends of the metal oxide semiconductor ⑽S) element, the depth of the LDD is only about 0.02 microns (# „), this and so on: Wen Yu = The two ends of the drain electrode and the source electrode form two tips, so that the static discharge phenomenon easily occurs at the tip structure of LDD: When the device is used in the above-mentioned output stage 15, the thin interrogation electrode on the element N1 and the oxygen seeding D2 ' Example = The gate oxide layer under 0.25 CMOS process is only about 50 矣 (A), this thickness is directly connected to the gate For an NMOS structure with an internal positive voltage source, it is easy to be broken by electrostatic discharge through LDD components in the component charging mode ⑽㈧, for example, and contact with human hands to be broken by electrostatic discharge; two = ^ 疋 上:, set 16 _Including an NMOS device directly connected to the positive operating voltage, such as the dummy element shown in Figure 2, the test results can be found in the ESD test (Figure 3) This is because this type of electrostatic lightning is only used in strong tanks, 丄 PN, most of which have a division distance of 吩 from the component% in this example. Therefore, page 6 0503-8133TW; TSMC2002- 0142; Sue.ptd 569417 V. Description of the invention (3) Most of them only start to work when the voltage is above 4V, but the components, such as N2 in this example, collapse and turn on because of the use of the gate in the most favorable road to 4V, In this case, it will be discharged without electricity. The possible damage to the soil J represents an internal circuit of the electrostatic discharge protection device. The relationship between the current and the return current is different. = Cumulative failure rate vs. breakdown voltage. Comparison In the 04sb figure: the place indicated by ticket number A, where the symbol a shown in the head points to the starting point of the electrostatic discharge protection device and the NMOS element, which are about 4. 2 V ( (See Fig. 4a) and 3.9 V (see Fig. 4b). Therefore, although the static electricity in the autumn input and output part can be smoothly discharged through the device 13 (pASS), but ^ is at the core power pin (core power pins) test part, only PM0S elements with higher gate breakdown voltage will discharge static electricity through the device PN, that is, the above-mentioned element p2 can pass the discharge test s test, and another NMOStg part N2 'will After the connected voltage Vss is grounded and a positive electrostatic discharge voltage is applied for testing through the voltage line C 0 revdd, the thin gate of the component N 2 is damaged because the device pn has not begun to function, making the entire wafer unable to pass. Electrostatic discharge test (test position 7 in Figure 2). In view of this, an object of the present invention is to provide a protection method for preventing an n-type metal oxide semiconductor element (NM0s) in an internal circuit from being damaged by #electric discharge, which uses a buffering element (buffering device) to avoid the occurrence of internal devices (core devices) ^: to excessive electrical stress (electricai stress) failure and failure. Another object of the present invention is to provide an internal circuit (core

569417 V. Description of the invention (4) Damage 11) Type 1 metal oxide semiconductor device (off 0s) is subjected to the electrostatic method ', which requires no additional process (Wslng), ie T to strengthen the above-mentioned electrostatic discharge protection. # 开 m 系: A protection method for preventing an NMOS of a N-type metal oxide semiconductor element (NMOS) in an internal circuit from being damaged by electrostatic discharge

Cirult ir⑽ESD damage), which includes the following steps: Detect the internal circuit (coor circuit), all of which have a constant series: a thin gate_type metal oxide with a voltage of exactly 1: semi-entry 4 servants: :, Will detect all of the above-mentioned N-type thin gates with a gate electrode P-type metal oxide semiconducting metal oxide semiconductor ΠΓΡΠΠΟ 佑 s have the best wishes. Λ 卜Λ Λ The ground of the above-mentioned electrical level of the logic level is 1 '. Thus, the above-mentioned thick bipolar metal: the higher oxidative breakdown voltage of the conductor (PM0S) (⑽〇V.〇1 ^ / e ) ^ ^ ^ ^ t ^ t 〇 The detailed description of the example of the car 乂 贯 贯 5 系 series solid root / ^ invention shows that to prevent the electrostatic discharge components in the internal circuit and the closed pole of the observation component 不再 are no longer directly connected To: = to —CMOS inverter 51, and inverting it to the gates of the PM0S PU_S element N5 in 51 at the same time. As shown in Fig. 5, a circuit structure as described above can prevent the component from being subjected to a positive electrostatic discharge (zap) from the electrostatic discharge. Because the characteristics of ’MGU parts are determined by nm 0503-8133TW; TSMC2002-0142; Sue.ptd Page 8 1 569417 V. Description of the invention (5) The second electric f level of the second gate is used to determine whether it is conducting or not. If the input voltage level is 0 k, the PMOS element will be turned on. On the contrary, when the OFF element is at the input voltage level of 1. Therefore, 'grounding the closed pole of the CMOS can maintain the level of the two "voltage Va at 0, so that the device" always remains conductive :: ,, for example, when encountering a positive electrostatic discharge from a voltage source (coreVdd) Day: 'as shown by the arrow' first passes through element P5 to produce an isolation / buffering effect, and then flows to make element N2 conductive. Figures 6a and 6b show the operation of the ESD protection device of Figure 5 respectively. Figure 6a represents the cumulative failure of the p-well in the _s element; a graph of the relationship of the breakdown voltage vbd. The second graph represents a plot of the cumulative failure rate CF versus the breakdown voltage Vbd of the pM0s element well. , And point B in the figure 6b shows that at the same cumulative failure rate (. Delete ... under faUurOCF, the pM0s element shown in the figure below has a higher breakdown voltage Vbd (action point) than the NMOS device shown in the figure above, The difference is about 0V (about the operating voltage of a diode). With this higher breakdown voltage, the resistance of the entire component to electrostatic discharge can be improved, and electrical damage can be avoided. The above inverter can be The thin oxide layer can also be in the form of an oxide layer. In addition, 'in order to achieve the isolation / buffering effect to avoid electrostatic discharge ^ thin element oxide layer of _S element N2' can also use a pass gate device Fig. 7 shows another embodiment of the electrostatic discharge protection device in the internal circuit according to the present invention. In Fig. 7, the inverter in Fig. 5 is replaced by a PM0S switching element 71, and the gate of the combination 71 The pole is grounded, so that the above-mentioned PM0S on-gate element 71 is maintained in a conductive state of% ° 0〇3-8133TW; TSMC2002-0142; Sue.ptd page 9 569417 5. State of the invention (6). As shown in FIG. 7, Operating the PMOS element 71 has a higher breakdown. Use electrostatic discharge resistance to avoid # 1, temples, in order to improve the entire component to the virtual component in the circuit; X: Discharge money, especially to avoid the internal PMOS element 71 can be double ^ :, causing the entire element Damaged. The above formula. "The chemical form can also be in the form of a thick oxide film. In addition, the figure 8 shows an embodiment of the electrostatic discharge protection device according to the present invention. The chemical layer in the circuit can also be used- = The thin interlayer oxygen connected to the shock delete element is a positive voltage source and: Γ The variable resistor (not shown) is connected to the source: the gate operating voltage of the source and the internal circuit and the sound of the internal circuit. Μ ≫ —, 疋 are connected between the positive poles. As shown in Figure 8 虚拟 'virtual v SS grounding' operation ^ around the single voltage source commonly used (that is, the value is about 1K, electrical ^ 'the above resistor is the best The voltage drop of the resistor makes two == two easy to cause the problem of excessive lock distortion on the resistor; conversely, if the resistance value is too small, so that the voltage drop across the resistor can not effectively reduce the high electrostatic discharge. Voltage to avoid the t of the internal components. Therefore, the implementation of this example found The performance with a resistance value of about 1 κ = performance is the best. However, the above resistance value is only used for illustration purposes, and its value can be changed according to practical needs. It is not limited to about 1K resistors. No. 90 is based on the present invention, which shows a protection method for preventing an n-type metal oxide semiconductor element (NM0S) in an internal circuit from being damaged by electrostatic discharge. Page 10 0503-8133TW; TSMC2002-0142; Sue.ptd 569417 5. Invention Description (7) Flow chart. As shown in FIG. 9, the protection method used in the above-mentioned electrostatic discharge protection device includes detecting a core circuit. All N having a thin gate electrode directly connected to a voltage at a logic level Type metal oxide semiconductor (NMOS) element (S 1); each of the detected N-type metal oxide semiconductor (NM0s) gates having a thin gate is passed through a P-type metal having a thick gate, respectively An oxide semiconductor (pM〇s) is coupled to the above logic level! Voltage (S2); and the gate of the metal oxide semiconductor (PMOS) having a thick free pole is coupled to a logic level of 0 voltage (S3), so that the above-mentioned metal having a thick gate step type can be used The higher gate breakdown voltage of the oxide semiconductor (PMOS) enhances the full-chip ESD protection capability. Because the components used in the protection method of the present invention add an additional manufacturing process (Slng), it only needs to be manufactured in the integrated system; it must be processed in accordance with the above method to achieve positive operation. Electrostatic discharge protection capability of a metal-emulsion semiconductor device that is extremely likely to directly endure a positive electrostatic discharge shock. Youpen Yue The virtual component part of the internal circuit that has always been overlooked. Most of the virtual components in the circuit are used as switches / selections, and even put inside: protection. Therefore, whether the chip can function or not, it also accounts for discharge: nature. ”However, this part of the protection mechanism (Mans), omitted For this reason, using the method of the present invention, a full crystal local area can be obtained without increasing the cost of the surface area (layout area): to prevent the wafer from being damaged due to the thin closed-electrode layer being damaged; 11 pages 0503-8133TW; TSMC2002-0142; Sue.ptd 569417 V. Description of the invention (8) Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

0503-8133TW; TSMC2002-0142; Sue.ptd Page 12 569417 The diagram is briefly explained in order to make the above and the beans of the present invention easy to see. The following special #quilt and advantages can be more clearly explained as follows. Example 'and in conjunction with the attached drawings, detailing FIG. 1 is a block diagram of a typical static oxide semiconductor (CMOS) circuit. A complementary gold protects the static electricity containing virtual components. Discharge

Electrostatic discharge test result table for the circuit in Fig.

Power-down, the relationship between the claw and the flyback voltage; Figure Ub 4b—the relationship between the NM Ω S points and the birth of the human field; Figure 5 of the cumulative failure rate versus the breakdown voltage Vbd is based on this issue— Oxide semiconductor elements (NM () s; different types of N-type metal preventive circuits in internal circuits; components (NM0S) double to electrostatic discharge damage protection circuit. Figure 6a represents a NMΓκ-al breakdown voltage Vbd The graph of the relationship between the cumulative failure rate CF of well P and collapse in Fig. 6b represents the graph of the relationship between pMos element " " voltage Vbd; the cumulative failure rate CF of well 1 ^ of T versus collapse 7 The diagram is according to the present invention. The eighth diagram is according to the present invention: another embodiment of the protection circuit. The ninth diagram is according to the present invention: T: an embodiment of the protection circuit; the oxide semiconductor element (NM0) is different to prevent the internal N-type metal flow chart in the circuit. Laughing at the protection method of electrostatic discharge damage

0503-8133TW; TSMC2002-0142; Sue.ptd Page 13 569417 Brief description of the drawing [Symbol description] 11 ~ input pins or pads; 1 3, 1 6 ~ ESD protection device; 15 ~ Complementary in internal circuit Solid metal oxide semiconductor solid element; 2 complementary metal oxide semiconductor virtual elements in the internal circuit; 5 1 ~ inverter; 71, P1, P2, P5, PN ~ P type metal oxide semiconductor;

N1, N2, N5 ~ N type metal oxide semiconductors; R ~ resistors; C 0 r e V d d ~ positive operating voltage source;

CoreVdd ~ negative operating voltage source.

0503-8133TW; TSMC2002-0142; Sue.ptd p. 14

Claims (1)

569417 ——— 6. Scope of Patent Application1. A protection method to prevent the internal lightning a (NMOS) from being detected by the electrostatic discharge M-type metal oxide semiconductor element u ^ +, including the following steps: a direct connection to a logic bit! = core circuit), all N-type metal oxygen with thin gates with a voltage of "1" will be detected on the upper station; idler points of conductor elements = N-type metal with = pole An oxide semi-semiconductor device is connected to a voltage of ^^ having a thick gate electrode type metal oxide to the above-mentioned logic level; and a P-type metal oxide semiconductor device having a thick electrode The gate is connected to a voltage with a logic level of 0. In this way, the above == (pole: higher inter-electrode oxidation breakdown of a type metal oxide semiconductor device t ^ breakd〇Wn V〇1 tage) ^ ^ ^ ^ ^ ^ # 2 'Shi Shen ° The scope of the patent No. 1 in the internal circuit to prevent N-type metal :: semiconductor devices (NM0S) from electrostatic discharge damage protection method, in the above steps are in the package Executed before the internal circuit. ^ 3 · As stated in item 1 of the patent scope, a protection method for preventing N-type metals in internal circuits from being damaged by electrostatic discharge, such as p-type metal oxides with thick gate electrodes. The semiconductor device has a first terminal and a second terminal. The first terminal is connected to the gate of the N-type metal oxide semiconductor device with two gates and is coupled to the logic level at 1 with the second terminal. The voltage. 4. Protection method for preventing electrostatic discharge damage of n-type gold oxide semiconductor device (NMOS) in internal circuit as in item 1 of the scope of patent application, 0503-8133T1V; TSMC2002-0142; Sue.ptd page 15 569417 (dummy core circuit) between a thin gate N-type metal oxide semiconductor device and a voltage source with a logic level of i to prevent the thin gate ㈣ thin gate of the metal oxide semiconductor device from being subjected to power supply static electricity The destruction of the discharge, the electrostatic discharge protection device includes one? Type metal-oxide-semiconductor pass gate element, which is coupled between the thin gate of the thin-gate metal-oxide-semiconductor element and a voltage source with a logic level, and the gate is grounded . >, Π · The integrated circuit chip according to item 10 of the patent application scope, wherein the 5th gate (p a s s g a t e) element is a thick gate type. 1 2. The integrated circuit chip according to the scope of the patent application, wherein the pass gate element is a thin gate type. 1 3 · If the integrated circuit chip of item No. 0 of the patent application scope, the electrostatic discharge protection device further includes an N-type metal oxide semiconductor element coupled to the p-type metal oxide semiconductor pass gate ( Between the pass gate) element and the ground, there is a gate of the same type as the gate of the p-type metal-oxide-semiconductor pass-gate element and grounded at the same time, of which the 4P-type metal-oxide-semiconductor pass-gate (pass A gate) element and the N-type metal oxide semiconductor element form an inverter. 〃 14 · If the integrated circuit chip No. 10 of the scope of patent application, Douzhong, The electrostatic discharge protection device is a resistor connected between the thin gate of the thin gate metal-oxide semiconductor device and a voltage source with a logic level. 15 · The integrated circuit chip of item 10 in the scope of patent application, wherein the value of the resistor falls between 0.5 · 5 · 5K Ω.