TW565993B - Improved integrated oscillators and tuning circuits - Google Patents

Abstract

An integrated Voltage controlled oscillator (VCO) includes varactors and fixed capacitors formed in a ""stacked"" arrangement. Forming the VCO integrated circuit by ""stacking"" fixed capacitors upon underlying varactors frees up semiconductor surface area for use by other circuit components or permits the implementation of a smaller integrated circuit package. ""Stacking"" further permits a decrease in parasitic capacitance associated with interconnections between the fixed capacitors and other components of the VCO.

Description

565993 V. Description of the invention (1) Background The present invention belongs to a general integrated circuit, and more particularly to an integrated circuit including an active circuit and a fixed capacitor. Voltage tunable capacitors (varactors) and fixed capacitors are commonly used in different electrical circuits that interfere with fluctuations. The circuit includes, for example, a tunable circuit (i.e., a low-pass, high-pass, or band stop filter) or a voltage-controlled oscillator (VC 0 's). In this type of circuit, a variable capacitance diode is used in combination with a variable added voltage and one or more fixed capacitors to tune the output of the circuit. In the case of a filter circuit, the filter responds as a function of the frequency of the input signal, causing the voltage applied to the varactor to change and π to tune the output voltage. An example of a conventional variable-capacitance-tuned filter is disclosed in U.S. Patent No. 5,107,233. In the case of V C 0, the voltage applied to the varactor is changed and the output frequency of the π oscillator is tuned. An example of a conventional variable-capacitance diode oscillator is disclosed in U.S. Patent No. 5,694,092. The tunable filter circuit and VCO's have a wide range of applications in electrical settings, including settings that require the use of such integrated circuits due to limited circuit size. This limitation is most common in many commercially available settings, including, for example, the transceiver circuit of a mobile radiotelephone. The use of integrated circuits in such equipment allows the circuit to be placed in a smaller space, making the installation easier to carry. Therefore, the tunable filters and VCO's in many settings are generally manufactured as a semiconductor integrated circuit. An example of a single lithium accumulation VOC is disclosed in Huang's US Patent No. 4,458,215. Figures 1 and 2 show this patent, which is a typical example.

0 \ 63 \ 63253 ptd Page 5 565993 V. Description of the invention (2) Variable capacitance diode (52, 5 4, 5 6, 5 8) and fixed capacitor (1) manufactured on a specified area of the semiconductor substrate (20) 5, 1 6). Disadvantages of the integrated circuit of this conventional architecture include that, in any case, due to the deposition between the edges of the varactor diode (5 2, 5 4, 5 6, 5 8) and the fixed capacitor (15, 16) Relatively large surface area and relatively long interconnected parasitic capacitance combined with the use of VCO components. The total cost of an integrated circuit, for example, includes one of the VCO circuits disclosed by Huang as a function of the amount of semiconductor area spent on manufacturing the circuit. Moreover, the distance between the elements deposited between edges in the integrated circuit is increased due to the parasitic capacitance combined with the elements. This parasitic capacitance can reduce the tunable range of the VCO and is otherwise detrimental to the function of the VCO. Such capacitors, such as the yellow capacitors deposited on the edges and between the edges, and the conventional integrated circuit fixed capacitors, thus increase the parasitic capacitance combined with the integrated circuit and the relative cost of manufacturing with the integrated circuit. SUMMARY OF THE INVENTION This is a representative specific embodiment of the purpose of inventing a integrated circuit, including one for reducing the semiconductor surface area consumed by the deposition of integrated circuit elements and / or the combined parasitic capacitance between integrated circuits. Or more than one active circuit and one or more fixed capacitors. The invention is to achieve a representative specific embodiment of the above object and includes an integrated circuit including a first part of an integrated circuit having a first surface and one or more layers including semiconductor material. The integrated circuit of this representative embodiment further includes a capacitor including at least a conductive layer and a dielectric layer, wherein the capacitor is formed by a first surface of a first portion of the integrated circuit.

0 \ 63 \ 63253 ptd Page 6 565993 V. Description of the invention (3) This and other purposes and their characteristics can be better understood from the description and accompanying drawings. The foregoing is only a convenient summary. The invention is protected by the scope of patent applications and their equivalent limitations. The drawings illustrate the purpose and advantages of the invention and can be understood in conjunction with the drawings and the following detailed description. Among them, FIG. 1 is a layer structure of a representative specific embodiment of the present invention using a variable capacitance diode and fixed electricity. Figures; Figure 2 is a system diagram of a voltage controlled oscillator according to another representative embodiment of the invention; Figure 3 is a plan of a VCO element according to conventional technology; Figure 4 is a representative specific embodiment according to the present invention VCO planning; FIG. 5 is a structural diagram of a layer structure of a representative specific embodiment using an active circuit and a fixed capacitor of the present invention. DETAILED DESCRIPTION According to a representative specific embodiment of the present invention, an active circuit such as a variable capacitance diode and a fixed capacitor are dedicated to merging an active circuit with a fixed capacitor in accordance with such a method of being fabricated in a semiconductor integrated circuit and It is possible to reduce the parasitic capacitance and reduce the surface area of the semiconductor. Fig. 1 shows a representative layer structure 100 of a merged varactor diode 110 and a fixed capacitor 105 which is one of the inventions. In the representative embodiment shown, the fixed capacitor 105 includes two conductive layers 115 and 120, and has an intervening insulating layer 125 (such as silicon monoxide, silicon dioxide, arsenide). Gallium, zinc sulfide, magnesium difluoride). The conductive layer may be composed of materials such as titanium, titanium, crane, and copper. For being good at this

0 \ 63 \ 63253 ptd Page 7 565993 V. Description of Invention (4) A skilled person should understand that other appropriate conductive materials can also be used. The capacitor 105 is manufactured on the surface of the varactor diode 110 instead of being on the substrate 130, so that the varactor / capacitor combination is made so that the integrated circuit requires only a small surface area. Further, the deposition of capacitor 105 on the surface of a varactor diode 110 can reduce the length of any intermediate connection between the varactor and the capacitor or between the varactor and the capacitor and the peripheral circuit. In particular, where the circuit architecture requires a direct electrical connection between the varactor diode 110 and the capacitor 105 part of the integrated circuit, the amount of parasitic capacitance can be reduced. In this case, the deposition of the capacitor 105 on the surface of the varactor diode 110 can reduce the length of the intermediate connection between the two, and as a result, reduce the parasitic capacitance. It can be built using a CMOS semiconductor processing process, such as the layer architecture 100 shown in FIG. 1 as a representative embodiment. It should be understood by a person skilled in this art that, in any case, the manufacturing of the layer structure 100 can use other known processes, including, for example, BICMOS, SiGe, or GaAs processes. In a representative CMOS semiconductor process, an N + deposition layer 135 is formed in the P substrate 130 and an N-epitaxial layer 140. The dopant is further implanted in the epitaxial layer 140 to form an N + deposition region 1 4 5. A P conductive type doping material is also implanted into the epitaxial layer 140 to create a P + region 155. Insulating regions 150 (such as silicon monoxide, silicon dioxide, gallium arsenide, zinc sulfide, and magnesium fluoride) can be further formed between the N + deposition region 145 and the P + region 155. In forming the layers and regions described above, those skilled in this art will understand the use of materials and dopants for each layer / region to focus on a separate process. For example, in the process of silicon, boron, arsenic, phosphorus, gallium and dopants are used together.

0 \ 63 \ 63253 ptd Page 8 565993 V. Description of the invention (5) The range is from 1 016 to 10 02G. In order to obtain a low-ohmic connection, conductive layers Ml 160, M2 165, and M3 1 70 are formed on the N + deposition region 1 45 insulation region 15 0, and the P + region 15 5. The conductive layers 16 0, 16 5 and 1 70 may be composed of materials such as | Lu, titanium, tungsten or aluminum copper. Those skilled in the art know that other suitable conductive materials can also be used. Between each conductive layer, an insulating layer 175 (such as oxidic oxide, dioxide; 5th, gallium, zinc sulfide, difluoride) is formed and can be used to connect each conductive via 180 Layer to layer. The first portion of the conductive layers mi and M2 forms a first cathode electrode 185, and the first portion of the conductive layers M1 and M2 and the first portion of the first conductive layer M3 form a second cathode electrode 190. The third part of M1 and M2 and the second part of M3 form an anode electrode 197. To obtain a variable-capacitance diode high-Q, the cathode electrodes 185 and 190 are shorted together (not shown). An intermediate layer is formed between the varactor diode 110 and the capacitor 105, and another insulating layer 195 is formed on the conductive layer M3 1 70. In any case, if it is really necessary to directly connect between the conductive layers M4 120 and M3 170, the warp (not shown) can be used with any of the cathode electrode 1 0 0 or the anode electrode 1 9 7 One connected. The use of M4 120 and M3 170 layers connected to each other can ensure a low parasitic capacitance. Μ _ For manufacturing capacitors 105, the conductive layer M4 120 is formed on the insulating layer 195 with an electrical valley of 1 The lower layer of 0 5 'is then an insulating layer 1 2 5 is formed on the conductive layer μ 4 1 2 0 and the conductive layer M 5 1 1 5 is formed on the insulating layer 1 2 5 to form an upper layer of the electric valley device 105 . It is not difficult for a person who is skilled in this skill to understand °, the formation of the above-mentioned transformer valley and the formation of 105 layers of capacitors can use any customary

565993 V. Description of the invention (6) The technology suitable for layer establishment is implemented, but not limited to the growth and deposition technology. In a representative second embodiment, the combination of the capacitor 105 and the varactor diode 110 shown in FIG. 1 is shown. A representative voltage-controlled oscillator 200 may be used, as shown in Figure 2, and fabricated in a specific integrated circuit (ASIC) application. In the VCO of FIG. 2, each of C0 205 and C2 215 and C1 210 and C3 220 may be equivalent to a single varactor / capacitor combination shown in the layer structure of FIG. 1. Using a conventional integrated circuit architecture, the varactor diodes C0 205 and C1 215, and C1 210 are deposited on the edge and edge of the semiconductor surface. As a result, a surface plan as shown in FIG. 3 can be obtained. According to the present invention, in any case, the capacitor 105 stacked on the varactor diode 110 can be used for the capacitor / varactor combination to help reduce the required surface area and thus, it is a smaller The ASIC may have a larger surface area which can be used as other circuit components. This is shown in Fig. 4, where a capacitor C 2 2 1 5 is deposited on the varactor diode and a capacitor C 3 2 2 0 is deposited on the varactor diode C 1 2 1 0. A person skilled in this art will understand that, as shown in the representative V C 0 of FIG. 2, different numbers of A S I C can be used. This type of varactor / capacitor layer architecture shown in FIG. 1 can be used. The AS IC can include, for example, a tunable filter configuration such as a tunable low pass, a band pass, or a frequency stop filter used on both a varactor diode and a capacitor. Those skilled in this art can understand that the representative embodiments of the invention can be widely used in any active circuit including an integrated circuit and one or more capacitors. As shown in Figure 5, it is used to reduce the surface area of semiconductors and make ASIC stacks.

0 \ 63 \ 63253 ptd Page 10 565993 V. Description of the invention (7) For the purpose of increasing the stacking density, a capacitor layer structure 500 instead of being formed on the substrate 510 will be stacked on any active circuit 505. The active circuit 505 includes, for example, a mixer, an analog-to-digital or digital-to-analog converter, a demodulator, or a power or current controlled oscillator. Although several specific embodiments are described here for the purpose of display, such specific embodiments are not intended to be transferred here. Those skilled in the art will understand that the specific embodiments shown can be modified. Such modification is meant to be included in the spirit and scope of the scope of the attached patent application.

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Claims (1)

565993 _ Case No. 89105803 _ Month and Day __ VI. Patent Application Scope A mixer. 9. The integrated circuit of item 1 of the patent application scope, wherein the integrated circuit is an amplifier. 10. For the integrated circuit of item 1 of the patent application scope, the integrated circuit is an analog-to-digital converter. 11. For the integrated circuit of item 1 of the patent application scope, the integrated circuit is a digital-to-analog converter. 12. For the integrated circuit of item 1 of the patent application scope, the integrated circuit is a modulator. 13. For the integrated circuit of item 1 of the patent application scope, the integrated circuit is a demodulator. 14. For the integrated circuit of item 1 of the patent application scope, the integrated circuit is a wave transformer. 15. The integrated circuit of item 1 in the scope of patent application, wherein the integrated circuit is a tunable filter. 16. The integrated circuit of item 1 of the patent application scope, wherein the integrated circuit is formed using a CMOS semiconductor process. 1 7. The integrated circuit according to item 1 of the scope of patent application, wherein the integrated circuit is formed using a BICMOS semiconductor process. 18. The integrated circuit of item 1 in the scope of patent application, wherein the integrated circuit is formed using a S 1 G e process. 19. The integrated circuit according to item 1 of the patent application, wherein one or more layers include one or more layers of a semiconductor material. 2 〇 The integrated circuit of item 2 of the patent application scope, wherein the first layer package 0 \ 63 \ 63253-9il212 ptc Page 14 565993 _Case No. 89105803_Year_Month__ VI. Scope of patent application Contains an insulating material. 2 1. The integrated circuit of item 2 of the patent application, wherein at least a portion of the first layer includes a conductive material. 2 2. The integrated circuit according to item 3 of the scope of patent application, wherein one or more of the cathode electrodes includes at least two cathode electrodes. 2 3. According to the integrated circuit of item 22 of the patent application scope, at least two cathode electrodes are shorted together. 2 4. As for the integrated circuit of item 20 in the scope of patent application, the insulating material thereof includes monolithic oxide 'and monolithic oxide'. 25. The integrated circuit according to item 1 of the patent application scope, wherein at least one conductive layer is formed by selecting from the group consisting of aluminum, titanium, tungsten, and aluminum-copper. 2 6. According to the integrated circuit of item 3 of the scope of patent application, one or more conductive layers are formed by selecting from the group consisting of aluminum, titanium, tungsten, and aluminum-copper. 0 \ 63 \ 63253-911212 ptc Page 15