TW565885B - Method for growing gate dielectrics with a high dielectric constant by liquid phase anode oxidation technique - Google Patents
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565885 _案號91112489_年月 s 铬不 五、發明說明(1) 本發明係有關一種以液相陽極氧化技術成長高介電常 數閘極介電質之方法,尤指一種利用液相陽極氧化技術可 成長高品質、高介電常數、超薄等效氧化層厚度 (Equivalent Oxide Thickness ,E0T)的閘極介電層, 且可直接與互補式金氧半電晶體(CMOS )製程整合的θ方法 〇 目前的互補式金氧半電晶體C Μ 0 S製程技術已進人深次 微米元件時代,而更先進的奈米製程技術(< 1 〇 〇 nm )也 正快速研發中並已接近量產階段;隨著製程技術不斷進步 ,電晶體之閘極氧化層也愈來愈薄,傳統的二氧化矽雖然 具有其無可取代的優點,但在積聚區(accumulation region )之漏電流卻隨著厚度減少而呈現指數上升的趨勢 因此具有高介電常數(high-k )之材料需研究發展作為閘 極氧化層,在相同等效氧化層厚度之下,高介電常數之閘 極氧化層可具有較低之漏電流,並極有可能取代二氧化石夕 而成為下一世代電晶體中的閘極氧化層。 一般成長薄的高介電常數金屬氧化層的習知技術主要 有熱成長(thermal oxidation)、分子束蠢晶成長 (Molecular Beam Epitaxy,MBE)、化學氣相沉積 (Chemical Vapor Deposition,CVD)及原子層沉積法 (Atomic Layer Deposition,ALD)。其中熱成長須先沉 積一層金屬或含有金屬之化合物於基板(substrate)上 再以熱氧化方式成長金屬氧化層,此方法雖然傳統且簡單 方便,但須於高溫環境下進行;分子束磊晶成長、化學氣565885 _ Case No. 91112489 _ Chromium is not five. Description of the invention (1) The present invention relates to a method for growing a high dielectric constant gate dielectric by a liquid phase anodizing technology, especially a method using a liquid phase anodizing The technology can grow high-quality, high-dielectric constant, ultra-thin Equivalent Oxide Thickness (E0T) gate dielectric layers, and can be directly integrated with complementary metal-oxide-semiconductor (CMOS) process θ Method 〇 The current complementary metal-oxide-semiconductor C M 0 S process technology has entered the era of deep sub-micron devices, and the more advanced nano-technology (< 100 nm) is also being rapidly developed and is approaching Mass production stage; with the continuous progress of process technology, the gate oxide layer of transistors is becoming thinner and thinner. Although traditional silicon dioxide has its irreplaceable advantages, the leakage current in the accumulation region As the thickness decreases, it tends to increase exponentially. Therefore, materials with high dielectric constant (high-k) need to be researched and developed as the gate oxide layer. Under the same equivalent oxide thickness, the gate with high dielectric constant has a high dielectric constant. The oxide layer can have a lower leakage current, and it is very likely to replace the dioxide and become the gate oxide layer in the next generation transistor. Conventional techniques for growing thin, high-k metal oxides include thermal oxidation, molecular beam epitaxy (MBE), chemical vapor deposition (CVD), and atoms. Atomic Layer Deposition (ALD). Among them, thermal growth must first deposit a layer of metal or a metal-containing compound on a substrate and then thermally oxidize the metal oxide layer. Although this method is traditional and simple and convenient, it must be performed in a high temperature environment; molecular beam epitaxial growth Chemical gas
第5頁 565885 銮號91112489 年月日 絛正_ 五、發明說明(2) 相沉積及原子層沉積法可直接在基板上成長金屬氧化層, 但須要昂貴的設備使得在高溫環境中能達到高度的真空。 對現今已進入量產的〇 . 1 3微米(0 · 1 3 // m )製程技術 而言,其電晶體之閘極氧化層厚度約為2 4 Λ,而當氧化層 厚度小於30Α時’直接穿隧效應(Direct Tunneling Effect )便開始嚴重影響氧化層(g a t e o x i d e )之絕緣特 性,出現直接穿随電流(Direct Tunneling current), 使得氧化層漏電流(1 e a k a g e c u r r e n t )增加,造成電晶 體在關閉狀態時的靜態功率散逸(P 〇 w e r d i s s i p a t i ο η ),並可能造成電路之錯誤切換;而在元件極小化的同時 ,電晶體之電流驅動能力也不斷下降,由金氧半場效電晶 體(M0SFET )之電流公式,Page 5 565885 (No. 91112489) _ V. Description of the invention (2) Phase deposition and atomic layer deposition methods can directly grow metal oxide layers on substrates, but require expensive equipment to achieve high levels in high temperature environments Vacuum. For the 0.13 micron (0.13 // m) process technology that has entered mass production today, the thickness of the gate oxide layer of the transistor is about 2 4 Λ, and when the thickness of the oxide layer is less than 30Α ' The direct tunneling effect began to seriously affect the insulation characteristics of the gate oxide, and a direct tunneling current appeared, causing the oxide leakage current (1 eakagecurrent) to increase, causing the transistor to be turned off. Static power dissipation (P 〇werdissipati ο η) at the time, and may cause erroneous switching of the circuit; while the component is miniaturized, the current driving ability of the transistor is also declining continuously. Current formula,
Id = 1/2 · //Cox · W/L (Vgs -Vt ) 2 其中,Id :電流;// ··遷移率;cox :氧化層電容; W :channel 寬度;L :channel 長度;Id = 1/2 · // Cox · W / L (Vgs -Vt) 2 Where, Id: current; // · · mobility; cox: oxide layer capacitance; W: channel width; L: channel length;
Vgs :閘極對源極之電壓;Vt :臨界電壓 可知欲提高電晶體之電流,則須提高氧化層電容(c〇x ),以保持元件在尺寸縮小時仍然具有一定的電流驅動能 力。 為解決上述問題,增加物理厚度(p h y s i c a 1 thickness )及介電常數可同時降低氧化層漏電流及提高 氧化層電容,因此使用高介電常數材料取代二氧化矽作為Vgs: Gate-to-source voltage; Vt: Critical voltage It can be known that if the transistor current is to be increased, the oxide layer capacitance (c0x) must be increased to keep the current driving ability of the device even when the size is reduced. In order to solve the above problems, increasing the physical thickness (p h y s i c a 1 thickness) and the dielectric constant can simultaneously reduce the oxide layer leakage current and increase the oxide layer capacitance. Therefore, a high dielectric constant material is used instead of silicon dioxide as the
565885 _案號 9Π12489_年月日__ 五、發明說明(3) 閘極氧化層已是必然的趨勢,而此種高介電常數閘極氧化 層又稱為高k值閘極介電質(High-k gate dielectrics )° 有鑑於此,本發明人憑藉其從事相關研究之多年經驗 ,經過不斷實驗及嘗試,終有本發明之產生。因此,本發 明一種以液相陽極氧化技術成長局介電常數閘極介電質之 方法,係先於一乾淨的矽基板表面上成長金屬薄膜,接著 以液相陽極氧化法將該金屬薄膜氧化成金屬氧化物作為閘 極氧化層,然後經過一道熱退火處理以提升氧化層品質; 利用該技術可成長高品質、高介電常數、超薄等效氧化層 厚度(Equivalent Oxide Thickness,EOT)的閘極介電 層,且可直接與互補式金氧半電晶體(CMOS )製程整合。 本發明之主要目的係提供一種以液相陽極氧化技術成 長高介電常數閘極介電質之方法,係先於一乾淨的矽基板 表面上成長金屬薄膜,接著以液相陽極氧化法將該金屬薄 膜氧化成金屬氧化物作為問極氧化層,然後經過一道熱退 火處理以提升氧化層品質,利用該技術可成長南品質、局 介電常數、超薄等效氧化層厚度(Equivalent Oxide Thickness,EOT)的閘極介電層,且可直接與互補金氧半 導體(CMOS )製程整合。 本發明之另一目的係提供一種具高介電常數閘極介電 質之金氧半場效電晶體之製作方法,係先於一矽基板完成 P井及N井之製作,以及隔離用氧化物之填充,接著在乾淨 的矽基板表面成長金屬薄膜,並以液相陽極氧化法將金屬565885 _Case No. 9Π12489_ 年月 日 __ V. Description of the invention (3) Gate oxide layer is an inevitable trend, and this kind of high dielectric constant gate oxide layer is also called high-k gate dielectric. (High-k gate dielectrics) In view of this, the present inventor has relied on his many years of experience in related research, and through continuous experiments and attempts, the invention has finally emerged. Therefore, a method for growing a local dielectric constant dielectric using a liquid phase anodizing technique is to grow a metal thin film on a clean silicon substrate surface, and then oxidize the metal thin film by a liquid phase anodizing method. A metal oxide is used as the gate oxide layer, and then a thermal annealing process is performed to improve the quality of the oxide layer; using this technology, a high-quality, high dielectric constant, ultra-thin Equivalent Oxide Thickness (EOT) The gate dielectric layer can be directly integrated with a complementary metal-oxide-semiconductor (CMOS) process. The main purpose of the present invention is to provide a method for growing a high-dielectric-constant gate dielectric by a liquid-phase anodizing technique. A metal thin film is first grown on a clean silicon substrate surface, and then the liquid-phase anodizing method is used to The metal thin film is oxidized to a metal oxide as an interlayer oxide layer, and then undergoes a thermal annealing process to improve the quality of the oxide layer. Using this technology, the quality, the local dielectric constant, and the ultra-thin equivalent oxide thickness (Equivalent Oxide Thickness, EOT) gate dielectric layer, and can be directly integrated with complementary metal-oxide-semiconductor (CMOS) process. Another object of the present invention is to provide a method for fabricating a gold-oxygen half field-effect transistor with high dielectric constant gate dielectric. The fabrication of P wells and N wells on a silicon substrate and isolation oxides are completed first. Filling, and then growing a thin metal film on the surface of a clean silicon substrate,
565885 _案號91112489_年月曰 修正_ 五、發明說明(4) 薄膜氧化成為金屬氧化物用作閘極氧化層,經由一道熱退 火處理以提升氧化層品質,形成一閘極層在該閘極金屬氧 化層之上,然後定義閘極區域,再利用離子佈植形成電晶 體之閘極、汲極及源極,沉積一氧化物絕緣層在該閘極層 之上,於蝕刻出閘極、汲極及源極窗口後,沉積一接觸導 線,並利用熱退火降低界面陷阱濃度,而可製作一種具高 介電常數閘極介電質之金氧半場效電晶體。 為使 貴審查委員瞭解本發明之目的、特徵及功效, 茲藉由下述具體之實施例,並配合所附之圖式,對本發明 做一詳細說明,說明如后: 實施例1 請參照第1圖(a )〜(e ),為CMOS製程相容之高k值 閘極介電質(以A 1 2 03為例)製造流程圖,如圖所示,利用 液相陽極氧化技術將金屬氧化成為金屬氧化物,藉以成長 高k值閘極介電質。其製程步驟為先於一 P型矽基板1完成 P井2及N井3之製作,以及隔離用氧化物4之填充(如第 1圖(a )所示),接著在乾淨的P型矽基板1上以蒸鍍 (evaporation ) 或滅鍵 (sputtering ) 的方式沉積一層 超薄的金屬铭薄膜5 (如第1圖(b )所示),接著以液 相陽極氧化技術(見第1圖(c ),陽極6為P型矽基板1 ,陰極7為白金片,電解質溶液8為純水或其它有機、無 機之電解質溶液),將金屬氧化成為金屬氧化層,之後再 經由退火(anneal)以提高氧化層之品質(未於圖示),565885 _Case No. 91112489_ Revised Year of the Month _ V. Description of the Invention (4) The thin film is oxidized to become a metal oxide to be used as the gate oxide layer. A thermal annealing process is performed to improve the quality of the oxide layer, and a gate layer is formed on the gate Electrode metal oxide layer, then define the gate area, and then use ion implantation to form the gate, drain and source of the transistor, deposit an oxide insulating layer on the gate layer, and etch the gate After the drain and source windows, a contact wire is deposited, and the interface trap concentration is reduced by thermal annealing, so that a gold-oxygen half field effect transistor with high dielectric constant gate dielectric can be fabricated. In order for your reviewing committee to understand the purpose, characteristics and effects of the present invention, the following specific embodiments are given in conjunction with the accompanying drawings to make a detailed description of the present invention, which will be described later: Example 1 Figures 1 (a) ~ (e) are manufacturing flowcharts of high-k gate dielectrics compatible with the CMOS process (taking A 1 2 03 as an example). As shown in the figure, metal Oxidation becomes a metal oxide, thereby growing a high-k gate dielectric. The process steps are as follows: the production of P well 2 and N well 3 is completed before a P-type silicon substrate 1 and the isolation is filled with oxide 4 (as shown in FIG. 1 (a)); An ultra-thin metal film 5 is deposited on the substrate 1 by evaporation or sputtering (as shown in FIG. 1 (b)), followed by a liquid phase anodizing technique (see FIG. 1). (C), the anode 6 is a P-type silicon substrate 1, the cathode 7 is a platinum sheet, and the electrolyte solution 8 is pure water or other organic or inorganic electrolyte solution), the metal is oxidized to a metal oxide layer, and then annealed In order to improve the quality of the oxide layer (not shown),
565885 _案號91112489_年月曰 修正_ 五、發明說明(5) 形成一閘極氧化鋁9 ,接著再成長一複晶矽閘極9 1 ,即 完成高k值閘極介電質(如第1圖(c )〜(e )所示)。 實施例2 以純水8 1定電壓直流陽極氧化製造之金氧半二極體 (Μ 0 S D i 〇 d e )為例,其操作步驟如前所述,先蒸鍍1 5 A 之純鋁(9 9 · 9 9 9 9 % )於乾淨之矽基板上,再以純水8 1 (D I wa t e r )進行定電壓直流陽極氧化,使用之電場為7 . 1 4 3 V / c m,氧化時間為6 . 5分鐘,如第2圖所示;之後再以 爐管(furnace)於氮氣(N2)環境中進行高溫退火,使用 溫度為6 5 0 °C ,時間6 0秒,即完成氧化層之製作;閘極為 蒸鍍之金屬鋁(3 0 0 0 A ),以光學微影術 (Photolithography)定義出閘極面積(2. 25x10_4 cm2 ),最後再蒸鍍金屬鋁做為晶片之背面接觸(back contact ),即完成整個元件之製作。完成之氧化鋁薄膜 其等效氧化層厚度(EOT )為23 A。 製作金氧半場效電晶體(M0SFET )時,則需於閘極定 義完成後,以離子佈植(i ο n i m p 1 a n t )形成電晶體之閘 極、源極、沒極(Gate - Source ^ Drain ),再沉積一接 觸導線於閘極、源極及汲極處,以形成一金氧半場效電晶 體。 上述實施例的結果分析如下: 研究高溫退火對元件特性的重要,我們在金氧半導體 M0S元件閘極端注入-1 mA/cm2的定電流,觀察閘極電壓變化 情形,其結果可於第3圖中觀察得知,元件在未經高溫退565885 _Case No. 91112489_ Modification of the month and year_ 5. Description of the invention (5) Form a gate alumina 9 and then grow a polycrystalline silicon gate 9 1 to complete the high-k gate dielectric (such as Figures 1 (c) ~ (e)). Embodiment 2 A gold-oxygen semi-diode (M 0 SD i ode) manufactured by pure water 81 constant voltage direct current anodizing is taken as an example. The operation steps are as described above. First, a 15 A pure aluminum ( 9 9 · 9 9 9 9) on a clean silicon substrate, and then subjected to constant voltage DC anodization with pure water 8 1 (DI wa ter). The electric field used is 7. 1 4 3 V / cm, and the oxidation time is 6.5 minutes, as shown in Figure 2. After that, the furnace is annealed in a nitrogen (N2) environment at a high temperature. The temperature is 650 ° C and the time is 60 seconds. Fabrication; metal aluminum (3 0 0 A) deposited on the gate electrode, the gate area (2. 25x10_4 cm2) was defined by photolithography, and finally metal aluminum was evaporated as the back contact of the wafer ( back contact) to complete the production of the entire component. The finished alumina film has an equivalent oxide layer thickness (EOT) of 23 A. When making a metal oxide half field effect transistor (M0SFET), the gate, source, and electrode (Gate-Source ^ Drain) of the transistor must be formed by ion implantation (i ο nimp 1 ant) after the gate definition is completed. ), And then depositing a contact wire on the gate, source and drain to form a gold-oxygen half field effect transistor. The results of the above examples are analyzed as follows: To study the importance of high temperature annealing on the characteristics of the device, we injected a constant current of -1 mA / cm2 at the gate end of the metal oxide semiconductor M0S element, and observed the gate voltage change. The results can be seen in Figure 3. Observed in the
第9頁 565885 __案號91112489_年月曰 修正_ 五、發明說明(6) 火前氧化層中含有大量的電子電洞陷阱(electron and h ο 1 e t r a p s ),當電子與電洞在流經氧化層的過程中被捕 獲(t r a p ),導致於閘極電壓的大幅擺動。但是,在經過高 溫退火處理後可以看到閘極電壓的擺動變化有明顯的改善 。由此可以看出高溫退火對陽極氧化後介電層品質改善的 重要性。 元件電流-電壓(I -V )特性如第4圖所示,在積聚區 (accumulation region)可得到較二氧化石夕低1〇〇〜1〇〇〇 倍之漏電流,而在空乏區 (depletion region)及反轉區 (i n v e r s i ο n r e g i ο η )可得到完全飽合之電流,此完全飽 合之電流將使得通道遷移率(channel mobility)不會產 生嚴重之衰退。 第5圖為橢圓測厚儀量出之光學厚度與c — v量測出之 電厚度作圖,由以下關係式中: S 〇x/EOT = £ ai2〇^/Ta]2〇^ δεοτ/δτα^^ ε〇^/£λ^ 其中,ε〇χ :氧化層介電常數;Ε〇τ :等效氧化層厚度; 书!化鋁介電常數;下咖:氧化鋁光學厚度; 介電J求侍—介電常數£纖為9. 7之高介電常數氧化紹 第6圖為在各種等效氧化層厚度之下與二氧化石夕之漏Page 9 565885 __Case No. 91112489_ Revised Year of the Month _5. Description of the Invention (6) The oxide layer before the fire contains a large number of electron hole traps (electron and h ο 1 etraps). Being trapped during the oxidation process results in a large swing in the gate voltage. However, after high temperature annealing treatment, we can see that the swing of the gate voltage has significantly improved. From this we can see the importance of high temperature annealing to improve the quality of the dielectric layer after anodizing. The element current-voltage (I -V) characteristics are shown in Figure 4. In the accumulation region, a leakage current that is 100 to 100 times lower than that of the dioxide is obtained, and in the empty region ( Depletion region) and inverse region (inversi ο nregi ο η) can obtain a fully saturated current. This fully saturated current will not cause a serious decline in channel mobility. Figure 5 is a plot of the optical thickness measured by an elliptical thickness gauge and the electrical thickness measured by c — v from the following relationship: S 〇x / EOT = £ ai2〇 ^ / Ta] 2〇 ^ δεοτ / δτα ^^ ε〇 ^ / £ λ ^ where ε〇χ: the dielectric constant of the oxide layer; E〇τ: equivalent oxide layer thickness; book! The dielectric constant of aluminum oxide; the following: the optical thickness of alumina; the dielectric J seeks the high dielectric constant of the dielectric constant £ 9. 7 Figure 6 shows the thickness of various equivalent oxide layers and The Leak of the Dioxide Stone
565885 _案號91112489_年月曰 修正_ 五、發明說明(7) 電流比較,可看出本製程為可重覆製造之穩定製程,在不 同等效氧化層厚度之下均可得到較二氧化矽為小之漏電流 特性,而最薄之Ε Ο T可達1 4 A。 比較前述諸較佳實施例,可知本發明有多項特色; 一、 以液相陽極氧化技術成長之薄膜金屬氧化層可作為金 氧半場效電晶體(MOSFET )之閘極介電層。此液相陽 極氧化技術可在室溫下對金屬薄膜進行良好之氧化控 制,因而可成長高品質、高介電常數(dielectric constant,k)之金屬氧化層,其等效氧化層厚度 (Equivalent Oxide Thickness,EOT)可降低至 1 4 A且仍保有較佳之電特性。在未來先進之0 . 1 3微 米以上的製程技術中,等效氧化層厚度須降低至2 0 A 以下,因此本技術將可與最先進的製程相容,在閘極 氧化層的製造上扮演一重要的角色。 二、 本發明採用成本低且有效的液相陽極氧化法,先沉積 一層金屬於基板上,再以液相陽極氧化(L i q u i d565885 _Case No. 91112489_ Revised Year of the Month _5. Description of the invention (7) The current comparison shows that this process is a stable process that can be made repeatedly, and can be more oxidized under different equivalent oxide thicknesses. Silicon has a small leakage current characteristic, and the thinnest E 0 T can reach 14 A. Comparing the foregoing preferred embodiments, it can be seen that the present invention has a number of features; 1. The thin-film metal oxide layer grown by the liquid-phase anodizing technique can be used as the gate dielectric layer of a metal-oxide-semiconductor field-effect transistor (MOSFET). This liquid-phase anodic oxidation technology can perform good oxidation control of metal thin films at room temperature, so it can grow high-quality, high dielectric constant (k) metal oxide layers, and its equivalent oxide thickness (Equivalent Oxide Thickness (EOT) can be reduced to 1 4 A and still have better electrical characteristics. In the future advanced process technology of more than 1.3 microns, the equivalent oxide layer thickness must be reduced to less than 20 A. Therefore, this technology will be compatible with the most advanced process and play a role in the fabrication of gate oxide layers. An important role. 2. The present invention uses a low-cost and effective liquid-phase anodizing method. A layer of metal is first deposited on a substrate, and then liquid-phase anodizing (L i q u i d
Phase Anodic Oxidation,Anodization)技術在適 當氧化電壓及時間控制下,可讓所沉積之金屬有效氧 化為金屬氧化層。與其它習知技術比較,此種製程不 須昂貴之儀器且可於室溫環境下進行,並且不須要在 高度真空(<10_7 torr)的環境下成長,因此對於 生長環境之熱預算(thermal budget)及生產成本均 可有效降低,並可輕易相容於目前的設計條件與製程 設備。Phase Anodic Oxidation (Anodization) technology allows the deposited metal to be effectively oxidized into a metal oxide layer under the appropriate oxidation voltage and time control. Compared with other known technologies, this process does not require expensive equipment and can be performed at room temperature, and does not need to grow in a high vacuum (< 10_7 torr) environment, so the thermal budget for the growing environment (thermal budget) and production costs can be effectively reduced and easily compatible with current design conditions and process equipment.
565885 _案號91112489_年月曰 修正_ 五、發明說明(8) 三、 本發明運用了室溫液相陽極氧化技術於金屬層的氧化 ,可製造出超薄(EOT < 20 A )且高品質的閘極氧化 層,並且能直接與現今CMOS製程整合而不須修改製程 參數及步驟,以達到元件極小化(m i n i m i z e )的最終 目的。 四、 本發明所使用之液相陽極氧化方法,選擇性及適用性 極高,例如成長方式可為蒸鍍、濺鍍、分子束磊晶成 長或化學汽相沉積方式其中之一;成長金屬材料可為 其氧化物具有高介電常數之金屬,如鋁(A 1 )、钽 (Ta )、鈦(Ti )、鍅(Zr )、鑭(La )其中之一; 陽極為晶片,陰極可為白金片(Pt)或N型半導體, 電解質可為純水或其他有機、無機之電解質溶液;使 用之電源供應可為定電壓直流(D C )、交流(A C )或 直流加交流(D A C )陽極氧化,以及定電流陽極氧化 其中之一;而使用熱退火處理機台可為爐管或快速熱 退火機台其中之一;使用氣體可為氮氣、氧氣、氨氣 (NH3)、笑氣(N20)或組合氣體 Forming Gas (90% N2 + 1 0 % H2 )其中之一;使用爐管時,退火溫度約介 於5 0 0〜9 0 0 °C之間,退火時間約介於卜9 0分鐘之間, 使用快速熱退火機台時,退火溫度約介於8 0 0〜1 0 0 0 °C 之間,退火時間約介於0〜6 0秒之間。 綜前所述,本發明具有下述優點: (1 )有效降低生長環境之熱預算及生產成本。 (2 )能直接與現今的互補式金氧半電晶體(CMOS )製程565885 _Case No. 91112489_ Revised Year of the Month _5. Description of the Invention (8) 3. The present invention uses room-temperature liquid-phase anodizing technology to oxidize metal layers to produce ultra-thin (EOT < 20 A) and The high-quality gate oxide layer can be directly integrated with the current CMOS process without modifying the process parameters and steps, so as to achieve the ultimate goal of minimizing components. 4. The liquid-phase anodizing method used in the present invention has high selectivity and applicability. For example, the growth method can be one of evaporation, sputtering, molecular beam epitaxial growth, or chemical vapor deposition; growing metal materials. It can be a metal whose oxide has a high dielectric constant, such as one of aluminum (A 1), tantalum (Ta), titanium (Ti), hafnium (Zr), and lanthanum (La); the anode is a wafer, and the cathode can be Platinum (Pt) or N-type semiconductor, the electrolyte can be pure water or other organic or inorganic electrolyte solution; the power supply used can be constant voltage direct current (DC), alternating current (AC) or direct current plus alternating current (DAC) anodizing And constant current anodization; and the thermal annealing machine can be one of the furnace tube or the rapid thermal annealing machine; the gas can be nitrogen, oxygen, ammonia (NH3), laughing gas (N20) Or one of the forming gases (90% N2 + 10% H2); when the furnace tube is used, the annealing temperature is about 50 ~ 9 0 ° C, and the annealing time is about 90 minutes When using a rapid thermal annealing machine, the annealing temperature is about Between 8 0 0~1 0 0 0 ° C, the annealing time is between about 0 seconds 0~6. In summary, the present invention has the following advantages: (1) Effectively reduce the thermal budget and production cost of the growing environment. (2) Can directly and today's complementary metal-oxide-semiconductor (CMOS) process
第12頁 565885 _案號91Π2489_年月曰 修正_ 五、發明說明(9) 整合而不須修改製程參數及步驟。 (3 )成長高品質、高介電常數、超薄等效氧化層厚度( Equivalent Oxide Thickness , EOT)的閘極介電 層。 由是,本發明確係具有極佳產業應用性及進步性,符 合發明專利申請要件,惟依法提出發明專利申請,祈 貴 審查委員早曰准予專利為禱。 雖本發明以較佳實施例揭露如上,但並非用以限定本 發明實施之範圍;任何熟習此項技藝者,在不脫離本發明 之精神和範圍内,當可作些許之更動與潤飾,即凡依本發 明所做的均等變化與修飾,應為本發明專利範圍所涵蓋, 其界定應以申請專利範圍為準,合先陳明。Page 12 565885 _Case No. 91Π2489_ Year Month Amendment _ V. Description of the invention (9) Integration without modifying process parameters and steps. (3) Grow a gate dielectric layer of high quality, high dielectric constant, and ultra-thin equivalent oxide thickness (EOT). Therefore, the present invention does have excellent industrial applicability and progress, and meets the requirements for invention patent applications. However, the invention patent application is submitted in accordance with the law. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the scope of implementation of the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. All equal changes and modifications made in accordance with the present invention shall be covered by the patent scope of the present invention, and the definition shall be based on the scope of the patent application, which shall be first declared.
第13頁 565885 _案號91112489_年月曰 修正_ 圖式簡單說明 第1圖係為與CMOS製程相容之高k值閘極介電質(以A1203 為例)製造流程示意圖。 第2圖係為液相陽極氧化法結構示意圖。 第3圖係為八1 2 03以08元件閘極注入-111^/(:1112定電流,閘極 電壓隨時間變化情形示意圖。 第4圖係為等效氧化層厚度為2 3 A之氧化鋁的電流-電壓 (I - V )特性示意圖。 第 5 圖 係 為 光 學 厚 度 對 電 厚 度 作 圖 1 可 求 得 _ 一 介 電 係 數 9 .7 之 高 介 電 係 數 之 氧 化 鋁 介 電 層 示 意 圖 〇 第 6 圖 係 為 各 種 等 效 氧 化 層 厚 度 下 與 二 氧 化 矽 之 漏 電 流 較 示 意 圖 〇 圖 號 簡 單 說 明 ; 1 P 型 矽 基 板 2 • P 井 3 N 井 4 • • • • 隔 離 用 氧 化 物 5 金 屬 鋁 薄 膜 6 陽 極 7 陰 極 8 電 解 質 溶 液 8 1 純 水 9 閘 極 氧 化 鋁 9 1 • • • • 複 晶 矽 閘 極Page 13 565885 _Case No. 91112489 _ Modified _ Brief Description of Drawings Figure 1 is a schematic diagram of the manufacturing process of high-k gate dielectrics (taking A1203 as an example) compatible with the CMOS process. Figure 2 is a schematic diagram of the structure of the liquid phase anodizing method. Figure 3 is a schematic diagram of the gate element injection of -111 ^ / (: 1112 constant current, gate voltage with time, and the gate voltage change over time. Figure 4 shows the oxidation with an equivalent oxide layer thickness of 2 3 A. Schematic diagram of the current-voltage (I-V) characteristics of aluminum. Figure 5 shows the optical thickness vs. electrical thickness. Figure 1 can be obtained _ A schematic diagram of a high-dielectric constant alumina dielectric layer with a dielectric constant of 9.7. Figure 6 is a schematic diagram of the leakage current with silicon dioxide at various equivalent oxide thicknesses. The drawing number is a brief description; 1 P-type silicon substrate 2 • P well 3 N well 4 • • • • Isolation oxide 5 metal Aluminum film 6 Anode 7 Cathode 8 Electrolyte solution 8 1 Pure water 9 Gate alumina 9 1 • • • • Polycrystalline silicon gate
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