TW565848B - Low power supply voltage detector circuit - Google Patents

Low power supply voltage detector circuit Download PDF

Info

Publication number
TW565848B
TW565848B TW91118964A TW91118964A TW565848B TW 565848 B TW565848 B TW 565848B TW 91118964 A TW91118964 A TW 91118964A TW 91118964 A TW91118964 A TW 91118964A TW 565848 B TW565848 B TW 565848B
Authority
TW
Taiwan
Prior art keywords
voltage
supply voltage
low
power supply
comparison
Prior art date
Application number
TW91118964A
Other languages
Chinese (zh)
Inventor
Martin Wang
Justin Yang
Tina Zhu
Original Assignee
Macronix Int Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix Int Co Ltd filed Critical Macronix Int Co Ltd
Priority to TW91118964A priority Critical patent/TW565848B/en
Application granted granted Critical
Publication of TW565848B publication Critical patent/TW565848B/en

Links

Landscapes

  • Measurement Of Current Or Voltage (AREA)

Abstract

A supply-voltage detection circuit is commonly used for preventing the erasing and programming of a nonvolatile memory device during the supply voltage lower than detect point. A low voltage detector is coupled to the low voltage input and has circuitry to provide a first not-ready signal when the supply voltage on the supply voltage input falls below a predetermined low voltage threshold. The not-ready signal prevents erasing or programming operations to occur in the nonvolatile memory device. A low voltage detector according to the present invention can have the detection potential variation be controlled in 0.3V range despite of the manufacturing variation or temperature dependency of the devices.

Description

發明内容: 本f明係有關於一種電壓偵測裝置,特別是有關於一 不會X到裝置本身因操作溫度或是製造過程之不同而造 '野於臨限電壓值之變化所影響,因此具有穩定電壓偵測 知作之電壓偵測裝置。 快閃記憶體(Flash EPROM)係在非揮發性儲存積體電 中具有舉足輕重之角色。這些快閃記憶體在晶片中具有 可電性抹除(Electrically Erasing)、程式化 ogramming)或疋讀取記憶胞(Mem〇ry ceii)之能力。因 ,這些快閃記憶體可藉由施予電壓到這些裝置中,藉以程 式化或是抹除其所儲存之資料,因此,加入快閃記憶體之 糸統則必須提供這些快閃記憶體供應電壓(Vcc)與程式化 ,壓(jpp)。、對於目前逐漸採用低電壓作為操作電壓之系 j而曰’幸運地’大部份的快閃記憶體都可被設計為在低 電壓(約1·8伏特)到高電壓(約12伏特)電壓來源下,可順 利地完成程式化之操作。 、 然而,/仍有一點必須注意,當電腦系統例如個人數位 —理(PDA)系統使用快閃記憶體作為其儲存媒介時,會隨 :電池之電壓下降而可能影響到整個裝置之操作。而會發 t ^種情況呢?此時,控制信號以及在系統中的程式化或 疋電性抹除之操作過程,將無法保證有 用在:ί,,進行的程式化或是抹除:以 而產生,這些將會進而縮小晶片之壽命。平乍有了此曰因Summary of the Invention: The present invention relates to a voltage detection device, and in particular, it does not affect X to the device itself, which is affected by changes in the threshold voltage value due to different operating temperatures or different manufacturing processes. Voltage detection device with stable voltage detection. Flash EPROM plays a pivotal role in non-volatile storage ICs. These flash memories have the ability to be electrically erased, programmed gramming, or read memory cells in the chip. Because these flash memories can be programmed or erased by applying voltage to these devices, systems that add flash memory must provide these flash memory supplies. Voltage (Vcc) and stylized, voltage (jpp). For the current system that gradually adopts low voltage as the operating voltage, "fortunately" most flash memory can be designed from low voltage (about 1.8 volts) to high voltage (about 12 volts). Programmable operation can be completed smoothly under voltage source. However, it is still important to note that when a computer system such as a personal digital assistant (PDA) system uses flash memory as its storage medium, the voltage of the battery may affect the operation of the entire device. And what will happen? At this time, the control signal and the programming or erasing operation in the system will not be guaranteed to be useful: ί, the programming or erasing: generated, these will further reduce the chip Of life. Ping Cha has this reason

9578twf.pul 第5頁 565848 五、發明說明(2) — 供應電壓偵測電路也因此被設計作為監控電壓之變 化,一旦當電池的電壓低於一預定之範圍時,這些電路將 會產生一未準備信號(Not-Ready Signals),以通知系統 作為因應之據。例如第丨圖所示之電路圖,供應非揮發性 §己憶體記憶胞1 2之操作電壓Vcc除了耦接到此非揮發性記 憶體記憶胞12之外,還耦接到一低電壓偵測裝置14。去所 供應的操作電壓小於—低電壓值時,則此低電壓偵測^ 14將會輸出一低電壓偵初信號(L〇w v〇Hage9578twf.pul Page 5 565848 V. Description of the Invention (2) — The supply voltage detection circuit is also designed to monitor the change of the voltage. Once the battery voltage is lower than a predetermined range, these circuits will produce an undefined Not-Ready Signals to inform the system as a basis for response. For example, the circuit diagram shown in Figure 丨 supplies the non-volatile memory cell 12 with an operating voltage Vcc coupled to the non-volatile memory cell 12 and a low-voltage detector.装置 14。 Device 14. When the supplied operating voltage is lower than the low voltage value, this low voltage detection ^ 14 will output a low voltage detection initial signal (L〇w v〇Hage

Signal j LVcc)以,代表所供應之操作電壓之值已小於安全 值。但^:,大部份的偵測電路具有供應電壓約為3 · 3伏 ,。但是對於低電壓之偵測電路(例如丨· 8伏特)而言,電 壓減少之幅度將會使這些偵測電路相當難設計,除此之 外,降低功率之消耗與晶片所占之面積也是增加此偵測 路整體複雜性之因素。 · 第2圖係顯示傳統之功率偵測裝置2〇〇之電路方塊圖。 串列之電阻R1與R2在功率供應電壓Vdd以及接地電位之間 串接而電阻Μ與一 NM0S電晶體Ml也連接到功率供應電壓 VDD以及接地電位之間。而此NM〇s電晶體M1之閘極連接到 在電阻R1與R2之間的節點N1,而同時一電容器C1 一端連接 到此節點N1與接地電位之間。串列連接之一pM〇s電晶體M3 與NM0S電晶體M2係連接到此功率供應電壓VDD與接地電位 之間,其中,PM0S電晶體M3之另一源/汲極則連接到此功 率供應電壓VDD,而NM0S電晶體M2之另一源/汲極則連接至 接地電位。PM0S電晶體M3與NM0S電晶體M2之閘極則連接到Signal j LVcc) represents that the value of the supplied operating voltage is less than the safe value. But ^ :, most detection circuits have a supply voltage of about 3.3V. However, for low-voltage detection circuits (such as 丨 · 8 volts), the reduction in voltage will make these detection circuits quite difficult to design. In addition, reducing the power consumption and increasing the area occupied by the chip Factors in the overall complexity of this detection path. · Figure 2 is a block diagram of a conventional power detection device 200. The series resistors R1 and R2 are connected in series between the power supply voltage Vdd and the ground potential, and the resistor M and an NMOS transistor M1 are also connected between the power supply voltage VDD and the ground potential. The gate of the NMOS transistor M1 is connected to the node N1 between the resistors R1 and R2, and at the same time one end of a capacitor C1 is connected between the node N1 and the ground potential. One of the series connection pM0s transistor M3 and NM0S transistor M2 is connected between this power supply voltage VDD and the ground potential, and the other source / drain of PM0S transistor M3 is connected to this power supply voltage VDD, and the other source / drain of NMOS transistor M2 is connected to the ground potential. The gates of PM0S transistor M3 and NM0S transistor M2 are connected to

565848565848

節點N2,而此節點N2係位於電阻R3與⑽⑽電晶體M1之間 除此之外,一電容器C2亦連接到節點…與功率供應電壓 CMOS電晶體M4與M5具有與電晶體M2與…相同的結構。 電晶體M4與M5之閘極係連接到在電晶體M2與…之間的節點 N3而電曰曰體與M5之間的閘極係經由一電容器(;3連接到 接地電位。而節點N4係電晶體M4與M5所連接的節點。此 CMOS電晶體M2與M3之輸入端與輸出端係分別為節點N2與 N3。而CMOS電晶體M4與M5之輸入端與輸出端係分別為節點 當功率供應電壓VDD從接地電位(Ground,底下簡稱 GNDj之電位位準上升到一預定之電壓位準時,則將會輸出 一高電壓脈衝以代表低電壓偵測信號(L〇w v〇ltageNode N2, which is located between the resistor R3 and the transistor M1. In addition, a capacitor C2 is also connected to the node ... and the power supply voltage CMOS transistors M4 and M5 have the same as the transistors M2 and ... structure. The gates of the transistors M4 and M5 are connected to the node N3 between the transistors M2 and ... and the gates between the body and the M5 are connected to the ground potential via a capacitor (; 3 and the node N4 is The nodes connected to transistors M4 and M5. The input and output terminals of this CMOS transistor M2 and M3 are nodes N2 and N3 respectively. The input and output terminals of CMOS transistors M4 and M5 are the node equivalent power When the supply voltage VDD rises from a ground potential (Ground, GNDj for short below) to a predetermined voltage level, a high voltage pulse will be output to represent a low voltage detection signal (L0wv〇ltage

Detector Signal)LVCC。此功能可藉由一端連接到接地電 £位準之電谷器C1與c 3,以及一端連接到功率供應電壓 VDD之電容器C2所完成。當所供應之功率係為功率供應電 壓VDD之電位時,這些電容器Cl、C2與C3則將不會被^ 電’,因此,節點Nl、N2與N3將會具有相同之電壓位準,如 功率供應電壓VDD或是接地電位GND。而節點“首先會變成 高電位,而電容器Cl、C2、與C3將會依序充電,而在節點 N1 j 與N3之電壓位準將會是VX = VDD*R2/(R1+R2)、接地 電壓以及功率供應電壓VDD,因此,節點4的輸出將 低電壓位準。 x 如上所描述,當VX電壓高於電晶體Ml的臨限電壓 565848 五、發明說明(4) (Threshold vo 11age、性,雨曰祕 里^vy ^ ^ ^時電日日體卽點Ν4會變成低電壓位 準。低於電晶體M1的臨限電壓(Thresh〇id voltage)時,電晶體節點N4會變成高電壓位準。因此, 電路將可以偵測功率供應電壓VDD高於或是低於 VTH1*(R1+R2)/R2,VTH1係電晶體们之臨限 整電剛與R2之值以及電晶舰的閉極寬度/長度比疋调 (Width/Length),則可以調整偵測的電壓範圍。 一般而言,此電路可以告知低電池電壓位準,並進而 ,此低電池電壓位準毀壞整個系統前停止任何的操作。但 =此電路若是在兩速操作的系統時,將會使整個操作電 壓的範圍因而變的相當窄。因為如第2圖所示的傳統偵測 偵測電路所能偵測的電壓係決定於電晶體M1的臨限電壓 值。如此,將會使這個電路有相當大的製造變化差異 (Manufacturing Variation),以及溫度的影響因素、。除 此之外,(R1 + R 2 )/ R 2的斜率將會使整個情況更糟糕。由於 上述的考慮因素,可以知道所能偵測的電壓之最大值與最 小值將可能大於0· 5伏特,嚴重影響電路的表現與適用、 性。 上述之情況會發生的理由詳述如下。在第2圖中的電路 藉由電路模擬軟體PSPICE模擬其操作。首先,先假設在模 擬期間,溫度係固定,因此僅需要考慮製造過程之差異所 造成的影響。因為電晶體Ml的臨限電壓具有製造上的差異 值約± 0 · 1到± 〇 · 2伏特’(假設電阻R1的值等於電阻r 2的、 值)’偵測的電壓位準將會二倍於製造過程的差異值。如Detector Signal) LVCC. This function can be completed by one end connected to the valley level C1 and c3, and one end connected to the power supply voltage VDD capacitor C2. When the supplied power is the potential of the power supply voltage VDD, these capacitors Cl, C2, and C3 will not be charged. Therefore, nodes N1, N2, and N3 will have the same voltage level, such as power Supply voltage VDD or ground potential GND. The node "will first become a high potential, and the capacitors Cl, C2, and C3 will be sequentially charged, and the voltage levels at the nodes N1 j and N3 will be VX = VDD * R2 / (R1 + R2), the ground voltage And the power supply voltage VDD, therefore, the output of node 4 will be at a low voltage level. X As described above, when VX voltage is higher than the threshold voltage of transistor M1 565848 V. Description of the invention (4) (Threshold vo 11age, In the rainy season ^ vy ^ ^ ^, when the electric day and sun point N4 will become a low voltage level. Below the threshold voltage (Thresh〇id voltage) of transistor M1, transistor node N4 will become a high voltage level Therefore, the circuit will be able to detect that the power supply voltage VDD is higher or lower than VTH1 * (R1 + R2) / R2. The threshold value of the VTH1 series transistors is just the value of R2 and the shutdown of the transistor. Width / Length adjustment, you can adjust the detected voltage range. Generally speaking, this circuit can inform the low battery voltage level, and further, this low battery voltage level stops before destroying the entire system Any operation. But = if this circuit is in a two-speed system, it will make the whole The operating voltage range is therefore quite narrow. Because the voltage that can be detected by the traditional detection circuit shown in Figure 2 is determined by the threshold voltage of transistor M1. In this way, this circuit will have Considerable Manufacturing Variation, as well as the influence factors of temperature. In addition, the slope of (R1 + R 2) / R 2 will make the whole situation worse. Due to the above considerations, we can know The maximum and minimum voltages that can be detected will be greater than 0.5 volts, which will seriously affect the performance, applicability and performance of the circuit. The reasons for the above situation will be described in detail below. The circuit in Figure 2 uses The circuit simulation software PSPICE simulates its operation. First, it is assumed that during the simulation, the temperature is fixed, so only the effect caused by the differences in the manufacturing process needs to be considered. Because the threshold voltage of the transistor M1 has a manufacturing difference of about ± 0 · 1 to ± 0 · 2 volts '(assuming that the value of resistor R1 is equal to the value of resistor r 2)' The voltage level detected will be twice the difference in the manufacturing process.

565848 五、發明說明(5) 第3圖所示^功率供應電壓VDD係為一直流上升電壓,而節 的電左位準將會線性地跟著功率供應電壓VDD變化, ^節=N4的電壓位準也就是第2圖之偵測電路之輸出。在 此二擬:Ϊ在相同電阻值條件下’電阻R2的阻值減少將會 此杈擬的線條更加的平(Flatter),因此,將會有相合大 二^二壓位準差異。在此以參數让值代表(R1+R2)/R2, 1 的臨限值差異等於一,也就是最小的k值時, 债測電壓位準差異將會是k倍。 _1了^釋溫度依賴性所造成的影響,請參照第4圖。對 體與聰電晶體的傳統模式,其具有溫度的依 類似已解釋的内容’臨限值的差異將會 由參數k值大小影響偵測電壓位準差異,而k值係大於一的 值,因此,此差異將會造成如放大器般的結果。 考慮到製造上的差異與溫度的依賴性兩個因素,將不 =二低電壓娜置,其所偵測的電壓位準差異將 雖然傳統的電壓偵測裝置可在高電壓時運作的 (約大於3V),然而其不可避免地需要減少由於製造上的差 異與溫度上的依賴性所造成偵測範圍之 間的變化程度。 但〜敢小值之 由上述第2圖之傳統電壓债測裝置可知,要降低 到低於一很小的電壓變化量,例如〇· 4伏特,似乎不 能達成。因此,無法達到較高的偵測精確度。 本發明之目的係提供一種電壓偵測萝 只』我置,其可以較高565848 V. Description of the invention (5) ^ The power supply voltage VDD shown in Figure 3 is a direct current rising voltage, and the left level of the power will change linearly with the power supply voltage VDD. ^ V = N4 voltage level That is, the output of the detection circuit in FIG. 2. In these two scenarios: 减少 Reduction of the resistance value of the 'resistance R2 under the same resistance value condition will make the proposed line more flat (Flatter), and therefore, there will be a large difference in voltage level. Here, the value of the parameter is used to represent (R1 + R2) / R2, and the threshold difference between 1 is equal to one, that is, when the minimum k value is, the difference in debt voltage level will be k times. _1Explain the effect of temperature dependence, please refer to Figure 4. For the traditional mode of the body and the smart transistor, the temperature difference is similar to the explained content. The difference of the threshold value will be affected by the parameter k value, and the value of k is greater than one. Therefore, this difference will result in an amplifier-like result. Considering the manufacturing difference and temperature dependence, the difference between the two voltage levels will not be set, and the difference in the detected voltage level will be different even though the traditional voltage detection device can operate at high voltage (about (Greater than 3V), however, it is inevitable to reduce the degree of change between detection ranges due to manufacturing differences and temperature dependence. However, the value of dare to be small From the conventional voltage debt measuring device in the above figure 2, it can be seen that it is impossible to reduce it to a small voltage change amount, such as 0.4 volts. Therefore, higher detection accuracy cannot be achieved. The purpose of the present invention is to provide a voltage detection device.

565848565848

五、發明說明(6) 的準確性監控供應電壓之變化。除此之外,更能減少因為 製粒上的差異或是操作溫度的變化所造成對於電壓偵測^ 置之影,響。 ^5. Description of the invention (6) The accuracy of monitoring the change of the supply voltage. In addition, it can also reduce the impact on the voltage detection due to the difference in granulation or the change in operating temperature. ^

今達上述之目4的,本發明提供一種低功率供應電壓偵 測電路,用以接收一供應電壓,包括一比較電壓產生器、 參考電壓產生器與一差異放大器。上述之比較電壓產生 器根據供應電壓產生並輸出一比較電壓。參考電壓產生器 根據供應電壓用以一線丨生相依關係產生一參考電壓。差異 放大器耦接到比較電壓產生器與參考電壓產生器,用以接 收比較電壓與參考電壓並輸出一低電壓偵測信號,其中當 ^考電壓大於比較電壓時,低電壓偵測信號將為一第一電 壓,準,用以表示供應電壓低於一預定债測電壓值,當考 電壓小於比較電壓時,低電壓偵測信號將為一第二電壓位 準,用以表示供應電壓高於預定偵測電壓值。 上述之低功率供應電壓偵測電路,其中比較電壓產生 器係根據在供應電壓增加時,比較電壓亦同時增加,但當 該供應電壓超過一預定電壓值時,比較電壓將會趨近一固 .定電壓值。 。/上述之低功率供應電壓偵測電路,其中比較電壓產生 :ft括一分壓電路中分壓電路分為兩組據以分壓供 f f,#中第一組係包括一第一電阻所組成,第二組係 ^ ^ 一電阻與一電晶體所組成,其中當供應電壓增加 日守,比較電壓係為兩組隊供應電壓分壓中之第二組分壓 值仁田供應電壓超過第二組中的該電晶體之一臨限電壓To achieve the above item 4, the present invention provides a low-power supply voltage detection circuit for receiving a supply voltage, including a comparison voltage generator, a reference voltage generator, and a difference amplifier. The above comparison voltage generator generates and outputs a comparison voltage according to the supply voltage. The reference voltage generator generates a reference voltage in a line-dependent relationship according to the supply voltage. The difference amplifier is coupled to the comparison voltage generator and the reference voltage generator to receive the comparison voltage and the reference voltage and output a low voltage detection signal. When the test voltage is greater than the comparison voltage, the low voltage detection signal will be one. The first voltage, standard, is used to indicate that the supply voltage is lower than a predetermined debt test voltage value. When the test voltage is less than the comparison voltage, the low voltage detection signal will be a second voltage level, which is used to indicate that the supply voltage is higher than a predetermined voltage. Detection voltage value. The above-mentioned low-power supply voltage detection circuit, wherein the comparison voltage generator is also increased when the supply voltage is increased, but when the supply voltage exceeds a predetermined voltage value, the comparison voltage will approach a solid. Fixed voltage value. . / The above-mentioned low power supply voltage detection circuit, wherein the comparison voltage is generated: ft includes a voltage divider circuit. The voltage divider circuit is divided into two groups based on the voltage divider for ff. The first group in # includes a first resistor. The second group is composed of a resistor and a transistor. When the supply voltage increases, the comparison voltage is the second component voltage in the partial voltage divided by the two groups. Threshold voltage of one of the transistors in the two groups

第10頁 565848 五、發明說明(7) 值後’比較電壓將會趨近臨限電壓值。 上述之低功率供應電壓偵測電路,其中參考電壓產生 器係根據供應電壓之值,線性地輸出參考電壓,其中當供 應電壓減少時,參考電壓亦線性地減少,當供應電壓增加 時’參考電壓亦線性地增加。而此參考電壓產生器係對供 應電壓經由一分壓電路作分壓後線性地輸出參考電壓值, 其中分壓電路分為兩組據以分壓供應電壓。第一組係包括 一電晶體所組成,第二組係包括一電阻所組成,而參考電 壓即為第二組之分壓。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉較佳實施例,並配合所附圖式,作詳細 說明如下: 圖號說明 非揮發性記憶體記憶胞1 2 低電壓偵測裝置1 4 功率偵測裂置2 〇 〇 電阻Rl、R2、R3 NMOS 電晶體Ml、m2、MVT、M12 PMOS 電晶體M3、MPL、Ml 1 節點Nl、N2、N3、N4 電容器Cl、C2 CMOS電晶體M4與M5 電阻R3Page 10 565848 V. Description of the invention (7) After the value, the comparison voltage will approach the threshold voltage value. In the above low-power supply voltage detection circuit, the reference voltage generator linearly outputs the reference voltage according to the value of the supply voltage. When the supply voltage decreases, the reference voltage also decreases linearly. When the supply voltage increases, the 'reference voltage' It also increases linearly. The reference voltage generator linearly outputs the reference voltage value after the supply voltage is divided by a voltage dividing circuit. The voltage dividing circuit is divided into two groups to divide the supply voltage according to the voltage. The first group consists of a transistor, the second group consists of a resistor, and the reference voltage is the partial voltage of the second group. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes a preferred embodiment in conjunction with the accompanying drawings, which are described in detail as follows: Figure numbers illustrate non-volatile memory cells. 1 2 Low voltage detection device 1 4 Power detection split 2 〇Resistor R1, R2, R3 NMOS transistor M1, m2, MVT, M12 PMOS transistor M3, MPL, Ml 1 Node Nl, N2, N3, N4 Capacitors Cl, C2 CMOS transistors M4 and M5 Resistors R3

9578twf.ptd 第11頁 565848 五、發明說明(8)9578twf.ptd Page 11 565848 V. Description of Invention (8)

NMOS電晶體MVT 節點N2 輸出電壓偵測電路5 00 比較電壓產生器510、610、910 差異放大器520、620、920 參考電壓產生器530、630、930 反相器940 實施例說明 請參照第5圖,係一種電壓偵測電路。而其電路方塊 圖,則如第6圖所示之内容。首先,先參照第6圖之電壓偵 測電路60 0,在中間部分係一差異放大器(Different Amplifier) 620,而左邊部分係一比較電壓產生器610,右 邊為一參考電壓產生器630。比較電壓產生器610與參考電 壓產生器630係分別輸出一比較電壓(Comparative Voltage)與一參考電壓(Reference Voltage)給差異放大 器6 2 0。而此差異放大器6 2 0具有相當好的功能,能在比較 電壓之位準(Comparative Voltage Potential)高於來考 電壓時,將會輸出接近功率供應電壓VDD電壓位準之一高 電壓值,而相反地,若是比較電壓之位準低於參考電壓"" 時,將會輸出一低電壓值。 " 而其詳細之電路圖請參照第5圖,並描述如下。 圖中,一由電阻R3與NM0S電晶體MVT串接之電路係 功率供應電壓VDD與接地電位之間,其中電卩且R3之,,=NMOS transistor MVT node N2 output voltage detection circuit 5 00 Comparison voltage generator 510, 610, 910 Difference amplifier 520, 620, 920 Reference voltage generator 530, 630, 930 Inverter 940 For an explanation of the embodiment, please refer to FIG. 5 , Is a voltage detection circuit. The circuit block diagram is as shown in Figure 6. First, referring to the voltage detection circuit 60 0 in FIG. 6, a differential amplifier 620 is connected in the middle part, a comparison voltage generator 610 is located on the left part, and a reference voltage generator 630 is located on the right side. The comparison voltage generator 610 and the reference voltage generator 630 respectively output a comparison voltage (Comparative Voltage) and a reference voltage (Reference Voltage) to the difference amplifier 6 2 0. The difference amplifier 6 2 0 has a very good function. When the comparison voltage level (Comparative Voltage Potential) is higher than the test voltage, it will output a high voltage value close to one of the power supply voltage VDD voltage levels. Conversely, if the level of the comparison voltage is lower than the reference voltage " ", a low voltage value will be output. " For the detailed circuit diagram, please refer to Figure 5 and describe it as follows. In the figure, a circuit in which a resistor R3 and a NMOS transistor MVT are connected in series is between the power supply voltage VDD and the ground potential, where the voltage between R3 and R3, =

9578twf.ptd 第12頁 565848 五、發明說明(9) 接到功率供應電壓VDD,而NMOS電晶體MVT之一源/沒極端 則接地。NMOS電晶體MVT之閘極及與電阻R3連接的源/沒極 端則同時連接到節點N 2。而這些元件則組成一比較電壓產 生器510,如同第6圖中所示的比較電壓產生器61〇,以便 產生比較電壓之位準。 而第6圖中的差異放大器620則與第5圖中所示的差異放 大器520相同,係由電晶體M1到心所組成。電晶體们與^ 係類似之NMOS電晶體,也就是具有相同的閘極寬唐/县声 ,b(Gate Width/Gate Length ^ 一起。電晶體Μ1的閘極係連接到在比較電壓產生器$ 1 〇中 的節點Ν2,而電晶體M2的閘極係連接到參考電壓^生器 530之節點Ν1,此如同第6圖中所示的參考電壓產生器° 630。電晶體Ml的汲極係連接到PM〇s電晶體Μ3的閘極與汲 極,也就是圖示中的節點⑽。電晶體Μ3與…係類似iPM〇s 電晶體,也就是具有相同的閘極寬度/長度比(Gate9578twf.ptd Page 12 565848 V. Description of the invention (9) It is connected to the power supply voltage VDD, and one source / non-pole of the NMOS transistor MVT is grounded. The gate of the NMOS transistor MVT and the source / non-terminal connected to the resistor R3 are simultaneously connected to the node N2. These components constitute a comparison voltage generator 510, like the comparison voltage generator 61 shown in Fig. 6, in order to generate the comparison voltage level. The difference amplifier 620 in FIG. 6 is the same as the difference amplifier 520 in FIG. 5 and is composed of the transistor M1 to the core. Transistors are similar to NMOS transistors, that is, they have the same gate width / counter sound, b (Gate Width / Gate Length ^ together. The gate of transistor M1 is connected to the comparison voltage generator $ 10 is the node N2, and the gate of the transistor M2 is connected to the node N1 of the reference voltage generator 530, which is like the reference voltage generator ° 630 shown in Fig. 6. The drain of the transistor M1 is The gate and drain connected to the PM0s transistor M3, which is the node 中 in the figure. Transistor M3 and ... are similar to iPM0s transistors, that is, they have the same gate width / length ratio (Gate

Width/Gate Length ratio),而其源極係連接在一起(節 點N3),而其源極則同樣接到功率供應電壓VDD。電晶體们 與M4的;及極則連接到節點N4,此節點“即為輸出電壓偵測 電路5 0 0之輸出。 參考電壓產生器530係由兩個電阻R1與“所組成,此串 接之電阻R1與R2係連接於功率供應電壓VDD與接地電位之 fΪ 與1^連接點係節點N1,此節點N1係當成此參 考電二壓產生裔530對差異放大器52〇之輸入端。 纪些電路之#作方法係詳述如下。第5圖中所描述的整 9578twf.ptd 第13頁 565848 五、發明說明(ίο) 個電路係用以作為低功率偵測之電路。參考電壓產生器 5 3 0係使用非常簡單的電路設計,在節點N丨的電壓位準可 輕易地獲付’即VN1=R2/(R1+R2)*VDD。相同地,在比較電 壓產生器5 1 0中,節點N 2的電壓位準可依照底下之公式獲 得: &Width / Gate Length ratio), and their sources are connected together (node N3), and their sources are also connected to the power supply voltage VDD. The transistors and M4 are connected to the node N4. This node "is the output of the output voltage detection circuit 50 0. The reference voltage generator 530 is composed of two resistors R1 and", this is connected in series The resistors R1 and R2 are connected to the fΪ and 1 ^ connection points of the power supply voltage VDD and the ground potential. The node N1 is used as the input terminal of the reference voltage two-voltage generator 530 pair difference amplifier 52. The methods of making these circuits are detailed below. The whole picture described in Figure 5 is 9578twf.ptd Page 13 565848 5. Description of the Invention (ίο) This circuit is used as a low power detection circuit. The reference voltage generator 5 3 0 uses a very simple circuit design, and the voltage level at the node N 丨 can be easily paid ', that is, VN1 = R2 / (R1 + R2) * VDD. Similarly, in the comparison voltage generator 5 10, the voltage level of the node N 2 can be obtained according to the following formula: &

VN2=RMVT/(RMVT+R3),當VN2<VTH ; VN2=VTH ,當VN2>=VTH 在此VTH代表NMOS電晶體MVT的臨限電壓,而rMVT則代 表NM0S電晶體MVT的電阻值。當考慮到節點…與!^2的電壓 位準時,也就疋VN1與VN2時,因為這兩個電壓值有不同之 電壓變化,所以,會如第7圖所示在某一點有交會處。因 此,功率供應電壓VDD的偵測電壓位準係為當節點N1與… 的電壓位準相等時,也就是VN1=VN2時。 因為NM0S電晶體MVT的臨限電壓會因為製造上的差異有 、、、勺± 0 ·。1到± 0 · 2伏特之變化,或是對於溫度的依賴性約 -2mV/°C,因此,當操作之溫度從_45t:到95t:時,最大的 臨限電壓值與最小的臨限電壓值之差異將會非常的大。也 ,為如上所述相同的理由,雖然節點N1之電壓會線性地跟 :功率供應電壓VDD之值,然而因為臨限值得差異變化將 _由一參數k之大小值而影響到所偵測電壓位準之, 此參數k係大於一之值,因此,低功率偵測之電路 的結果將會是此差異變化值得放大值。 置可在高電壓時運作的非常好 (、·々大於3V),然而其不可避免地需要減少由於製造上的差VN2 = RMVT / (RMVT + R3), when VN2 <VTH; VN2 = VTH, when VN2 > = VTH where VTH represents the threshold voltage of NMOS transistor MVT, and rMVT represents the resistance value of NMV transistor MVT. When considering the voltage levels of the nodes ... and! ^ 2, that is, VN1 and VN2, because these two voltage values have different voltage changes, there will be an intersection at a certain point as shown in Figure 7. Therefore, the detection voltage level of the power supply voltage VDD is when the voltage levels of the nodes N1 and ... are equal, that is, when VN1 = VN2. Because the threshold voltage of NMTOS transistor MVT will be due to manufacturing differences, there are ±, 0, and 0. 1 to ± 0 · 2 volts, or a temperature dependence of about -2mV / ° C, so when the operating temperature is from _45t: to 95t :, the maximum threshold voltage value and the minimum threshold The difference in voltage values will be very large. Also, for the same reason as above, although the voltage of node N1 will linearly follow the value of the power supply voltage VDD, but because the threshold value is different, the detected voltage will be affected by the value of a parameter k. At the level, this parameter k is a value greater than one. Therefore, the result of the low-power detection circuit will be that this difference changes is worth amplifying. The device can work very well at high voltage (, 々 is greater than 3V), but it inevitably needs to be reduced due to manufacturing differences.

565848 五、發明說明(11) 異與溫度上的依賴性所造成偵測範圍之最大值與最小i之 間的變化程度。 在第5圖中,比較電壓(VN2)之位準係由比較電壓產生 器5 1 0所產生,而其值最主要係由電晶體MVT之臨限值所決 定。而參考電壓(VN1)係由參考電壓產生器530所產生。如 果比較電壓產生器510所能產生的比較電壓VN2可如同第8 圖所示產生理想的比較電壓VN2值,則電壓偵測電路5〇〇由 於製成上的差異與操作溫度之差異所造成的偵測錯誤情形 將會非常明顯的減少。因此,此問題端視如何產生如第8 圖所示之理想的比較電壓VN2值。 本發明所提供一較佳實施例之電壓偵測電路,如第9圖 所示之一實施例之電壓偵測電路詳細電路圖,將可具有相 當接近此理想的比較電壓輸出之功能。在第9圖中,包含 在中間部分係一差異放大器(Different Amplifier)920, 而左邊部分係一比較電壓產生器910,右邊為一參考電壓 產生器930。比較電壓產生器91〇與參考電壓產生器930係 为別輸出一比較電壓(Comparative Voltage)與一參考電 壓(Reference Voltage)給差異放大器920。而差異放大器 的輸出則經由一反相器(lnverter)940輸出一低電壓偵 測4吕號(Low Voltage Detector Signal ,底下簡稱 LVCC)。此lvcc信號若是在節點N4的電位為邏輯低電位 時’則輸出接近功率供應電壓VDD之值,若是在節點N4的 電位為邏輯高電位時,則輸出零電位。上述的LVCC電壓位 準用以代表功率供應電壓VDD是否低於一預定之偵測電壓565848 V. Description of the invention (11) The degree of change between the maximum and minimum i of the detection range caused by the dependence on the difference between temperature and temperature. In Figure 5, the level of the comparison voltage (VN2) is generated by the comparison voltage generator 5 10, and its value is mainly determined by the threshold value of the transistor MVT. The reference voltage (VN1) is generated by the reference voltage generator 530. If the comparison voltage VN2 generated by the comparison voltage generator 510 can generate an ideal comparison voltage VN2 value as shown in FIG. 8, the voltage detection circuit 500 is caused by a difference in manufacturing and a difference in operating temperature. Detecting error conditions will be significantly reduced. Therefore, this problem depends on how to generate the ideal comparison voltage VN2 value as shown in FIG. 8. The voltage detection circuit of a preferred embodiment provided by the present invention, such as the detailed circuit diagram of the voltage detection circuit of one embodiment shown in FIG. 9, will have a function that is relatively close to this ideal comparison voltage output. In FIG. 9, the middle part is a differential amplifier (Different Amplifier) 920, the left part is a comparison voltage generator 910, and the right is a reference voltage generator 930. The comparison voltage generator 91 and the reference voltage generator 930 respectively output a comparison voltage (Comparative Voltage) and a reference voltage (Reference Voltage) to the difference amplifier 920. The output of the difference amplifier outputs an Low Voltage Detector Signal (LVCC) via an Inverter 940. This lvcc signal outputs a value close to the power supply voltage VDD if the potential of the node N4 is a logic low potential, and outputs a zero potential if the potential of the node N4 is a logic high potential. The above LVCC voltage level is used to represent whether the power supply voltage VDD is lower than a predetermined detection voltage.

9578twf.ptd 第15頁 565848 五、發明說明(12) '-- 位準,若低於此偵測電壓位準,則LVCC電壓位準將為高電 位,若高於此偵測電壓位準,則LVCC電壓位準將為低電 位。 上述的比較電壓產生器9 1 0可由兩分壓部分串接所組 成,利用此分壓部分輸出比較電壓。而此第一部份之分壓 可由例如一電阻R2所組成,而此第二部分之分壓可由例如 一NMOS電晶體MVT與電阻R1串接之電路所組成。因此,如 圖所示,電阻R2 、NMOS·電晶體MVT與電阻R1串接在功率供 應電壓VDD與接地電位之間,其中電阻R3之一端連接到功 率供應電壓V D D ’而Ν Μ 0 S電晶體Μ V T之一源/沒極端則接到 電阻R1 ’並由電阻R1之另外一端接地。NMOS電晶體MVT之 閘極及與電阻R3連接的源/汲極端則同時連接到節點!^2。 而這些元件則組成一比較電壓產生器9丨〇,以便產生比較 電壓之位準。 而第9圖中所示的差異放大器92 0係由電晶體Ml到Μ5所 組成。電晶體Ml與M2係類似之NM〇s電晶體,也就是具有相 同的閘極寬度/長度比(Gate Width/Gate Length ratio),而其源極係連接在一起。電晶體…的閘極係連接 到在比較電壓產生器910中的節點N2,而電晶體M2的閘極 係連接到參考電壓產生器930之節點N1。電晶體Ml的汲極 係連接到PM0S電晶體M3的閘極與汲極,也就是圖示中的節 點N3。電晶體M3與M4係類似之PM0S電晶體,也就是具有相 同的閘極寬度/長度比(Gate Width/Gate Length ratio),而其源極係連接在一起(節點N3),而其源極則同9578twf.ptd Page 15 565848 V. Description of the invention (12) '-If the level is lower than the detection voltage level, the LVCC voltage level will be high. If it is higher than the detection voltage level, then The LVCC voltage level will be low. The above-mentioned comparison voltage generator 910 may be composed of two voltage division parts connected in series, and the comparison voltage is outputted by using this voltage division part. The voltage division of the first part may be composed of, for example, a resistor R2, and the voltage division of the second part may be composed of, for example, a circuit in which an NMOS transistor MVT is connected in series with the resistor R1. Therefore, as shown in the figure, the resistor R2, the NMOS transistor MVT, and the resistor R1 are connected in series between the power supply voltage VDD and the ground potential. One end of the resistor R3 is connected to the power supply voltage VDD 'and the NM 0 S transistor. One source / non-pole of VT is connected to resistor R1 'and grounded at the other end of resistor R1. The gate of the NMOS transistor MVT and the source / drain terminal connected to the resistor R3 are connected to the node at the same time! ^ 2. These components constitute a comparison voltage generator 910 to generate a comparison voltage level. The difference amplifier 920 shown in Fig. 9 is composed of transistors M1 to M5. Transistors M1 and M2 are similar NMOS transistors, that is, they have the same Gate Width / Gate Length ratio, and their sources are connected together. The gate of the transistor ... is connected to the node N2 in the comparison voltage generator 910, and the gate of the transistor M2 is connected to the node N1 of the reference voltage generator 930. The drain of the transistor M1 is connected to the gate and the drain of the PMOS transistor M3, that is, the node N3 in the figure. Transistors M3 and M4 are similar PM0S transistors, that is, they have the same Gate Width / Gate Length ratio, and their sources are connected together (node N3), while their sources are with

9578twf.ptd 第16頁 565848 五、發明說明(13) ---- 功率供應電壓VDD。電晶體M2觸的汲極則連接到 參考電壓產生器930係由兩分壓部分所组成,利用對功 率供應電壓VDD之分壓以便產生參考電壓。而參考電壓係 與功率供應電壓VDD線性地相依(Unearly Dependent), 也就是說,當功率供應電壓VDD減少時,參考電壓會線性 地減少,當功率供應電壓VDD增加時,參考電壓會線性地 增加。至於線性地增加之比率,則必須視兩分壓部分之功 能而定。而本發明之一特點,即利用分壓之調整而進而穩 定地控制並輸出此參考電壓。 此兩分壓部分之第一部份例如是由一 pM〇s電晶體Mp]L所 組成,此PMOS電晶體MPL之閘極接地,使此電晶體保持在 開啟(Turn ON)之狀態。而第二分壓部分則可由例如一電 阻R2所組成,g然,本發明亦不限制在具有固定電阻值之 電阻或是電晶體所組成,亦可由可調整阻值得可變電阻所 組成’此係根據設計上之需要而定。此串接之pM〇s電晶體 MPL與電阻RL係連接於功率供應電壓VDD與接地電位之間。 而PM0S電晶體MPL與電阻RL連接點係節點N1,此節點…係 當成此參考電壓產生器930對差異放大器92〇之輸入端。藉 由調整PM0S電晶體MPL的閘極寬度/閘極長度比(Rat i〇 Gate Width/Gate Length),即可控制參考電壓產生器mo 所輸出的參考電壓。 而第9圖之實施例電路圖,與第5圖所描述的電壓偵測 電路非常接近’除了有部分之差異。這些差異包括,首9578twf.ptd Page 16 565848 V. Description of the invention (13) ---- Power supply voltage VDD. The drain electrode of the transistor M2 is connected to the reference voltage generator 930, which is composed of two voltage-dividing parts, and uses the voltage divided by the power supply voltage VDD to generate the reference voltage. The reference voltage is linearly dependent on the power supply voltage VDD. That is, when the power supply voltage VDD decreases, the reference voltage decreases linearly. When the power supply voltage VDD increases, the reference voltage linearly increases. . As for the linearly increasing ratio, it must depend on the function of the two-part voltage division. A feature of the present invention is that the reference voltage is stably controlled and output by utilizing the adjustment of the divided voltage. The first part of the two voltage divisions is, for example, composed of a pM0s transistor Mp] L. The gate of the PMOS transistor MPL is grounded to keep the transistor in the ON state. The second voltage dividing part may be composed of, for example, a resistor R2. However, the present invention is not limited to a resistor or a transistor having a fixed resistance value, and may be composed of an adjustable resistor and a variable resistor. This is based on design needs. The pM0s transistor MPL and the resistor RL connected in series are connected between the power supply voltage VDD and the ground potential. The connection point between the PM0S transistor MPL and the resistor RL is node N1, and this node ... serves as the input terminal of the reference voltage generator 930 to the difference amplifier 92. By adjusting the gate width / gate length ratio of the PM0S transistor MPL, the reference voltage output by the reference voltage generator mo can be controlled. The circuit diagram of the embodiment in FIG. 9 is very close to the voltage detection circuit described in FIG. 5 except for some differences. These differences include, first

9578twf.ptd 第17頁 565848 五、發明說明(14) 先,一PMOS電晶體MPL取代第5圖中所示的參考電壓產生器 530中的電阻ri,其次是,電容與^^"?加到此電 路中。其中電容器CCPA1包括一端接地,而另外一端則接 到節點N1,以便穩定參考電壓產生器930所輸出之參考電 壓。而電容器CCPA2包括一端接地,而另外一端則接到電 晶體MVT的源極端(節點N2),以便穩定比較電壓產生器910 所輸出之比較電壓。在第9圖中,pM〇S電晶體MpL與一電阻 RL係串接在一起,一端遠接到功率供應電壓VDD,而另外 一端則接地。當功率供應電壓VDD之電壓位準高於電晶體 MPL的臨限電壓值時,電晶體MpL將會關閉,而節點^的電 壓位準將會很快地降到接地位準。 明參照第1 〇圖,係理想之參考電壓值,與根據本發明 圖較佳實施例之電壓偵測裝置所產生之實際參考電壓 ==較圖。其顯示使用一pM〇s電晶體MpL以取代原有的 電阻將會是非常實際且有其特殊之功效。 點曰如上/斤解釋’在節點N1與~2的電壓值VN1與·2的交叉 非常4要的點’從此點以上’當功率供應電壓 ㈣Γ/置所i!N屮2將大於VN1 ’因此第9圖較佳實施例之電壓 近零”壓偵測信號_將會輸出-接 V- ^ A VN; : ; ^ ^ ^ ^ ^ Μ 功率供應電壓VDD之高電壓值因:,LVCC將會輸出-接近 的功率相當的重要。^V因Λ,在此交又點所供應 偵測點在例如丨.2伏特,路設計之規格要求 吁仁谷弄邊化值從1 · 1伏特到i · 3伏9578twf.ptd Page 17 565848 V. Description of the invention (14) First, a PMOS transistor MPL replaces the resistor ri in the reference voltage generator 530 shown in Figure 5. Second, the capacitance and ^^ "? Into this circuit. The capacitor CCPA1 includes one end connected to the ground and the other end connected to the node N1 to stabilize the reference voltage output by the reference voltage generator 930. The capacitor CCPA2 includes one end connected to the ground and the other end connected to the source terminal (node N2) of the transistor MVT in order to stabilize the comparison voltage output by the comparison voltage generator 910. In Fig. 9, the pMOS transistor MpL is connected in series with a resistor RL, one end is remotely connected to the power supply voltage VDD, and the other end is grounded. When the voltage level of the power supply voltage VDD is higher than the threshold voltage of the transistor MPL, the transistor MpL will be turned off, and the voltage level of the node ^ will soon drop to the ground level. The reference to Figure 10 is the ideal reference voltage value and the actual reference voltage generated by the voltage detection device according to the preferred embodiment of the present invention. It shows that using a pM0s transistor MpL to replace the original resistor will be very practical and has its special effect. The point is as above / jin explained 'at the intersection of the voltage values VN1 and · 2 of the nodes N1 and ~ 2 is very important.' From this point onwards ', when the power supply voltage ㈣Γ / position i! N 屮 2 will be greater than VN1' Therefore In the preferred embodiment of FIG. 9, the voltage near zero voltage detection signal will be output-connected to V- ^ A VN;: ^ ^ ^ ^ ^ Μ The high voltage value of the power supply voltage VDD is: LVCC will The output-close power is very important. ^ V is due to Λ, and the detection point supplied at this junction is, for example, 丨 2 volts. The specifications of the road design require that the marginal value of Hurengu is from 1.1 volts to i 3 volts

第18頁 565848 五、發明說明(15) U ί次::個目的可以達成,首先,係如何控制此偵 八%疋、如何控制差異以符合此規袼的要求。 以—此規格為例,此要求將很容易達成。在如^圖中的 ▲ k擇係維持所有的參數在此電路中都不改變,唯一 的J電阻R1的電阻值。t對電阻從零開始加入電阻 後,即點N2的電壓位準VN2將會上升,進而影響交叉點 =位置並最後影響偵測點。第二個選擇即維持在此電路中 集$有參數都不變,除了PMOS電晶體MPL的間極寬度/閘極 度比(Rat10 of Gate Width/Gate Length)。調整電晶 ,mpl的閘極寬度/閘極長度比可改變電晶體MPL的電流, 、、’且因而影響在節點N1的電壓位準。因為VN1與VN2的交叉 〒係最、關鍵的點,此調整電晶體MPL的閘極寬度/閘極長度 t將可達成調整控制偵測點的目的。 、 〜關於上述之第二項選擇,為了達到偵測點控制在一預 範圍内,如上述之0.3伏特之規格為例,將會非常不 谷i從第8圖中所示的理想的參考電壓位準波形可知, =車又電壓產生器之掣程差異與溫度的依賴性將不會影響偵 ’貝之差異。而在第9圖中的較佳實施例之電壓偵測裝置中 可知,若電阻R1之值固定,節點N1的電壓VN1將會固定, 在此電路中唯一會影響债測點差異的因素則為電晶 二。冑然電晶體MPL本身亦有製程上的差異與溫度的依 ,但是若小心地選擇電阻RL的電阻值,其特性將會使 k度的依賴性所造成的影響變得相對地非常小。而此設計 !1 9578twf.ptd 第19頁 565848 五、發明説明(16) 將會使偵測點的變動範圍可控制在上述的預定範圍内,而 不需考慮製程差異與溫度之變化。 ^ =然本發明已以一較佳實施例揭露如上,然其並非用 =限^本發明,任何熟習此技藝者,在不脫離本發明之精 1»範圍内,s可作各種之更動與潤飾,因此本發明之伴 遵範圍當視後附之申請專利範圍所界定者為準。之保Page 18 565848 V. Description of the invention (15) U ί times: The purpose can be achieved. First, how to control the detection rate and how to control the difference to meet the requirements of this regulation. Take this specification as an example, this requirement will be easily met. The selection of ▲ k in the figure ^ keeps all parameters unchanged in this circuit, the only resistance value of J resistor R1. After adding the resistance to the resistor from zero, the voltage level VN2 at point N2 will rise, which will affect the intersection point = position and finally the detection point. The second option is to keep the parameters in this circuit unchanged, except for the PMOS transistor MPL's pole width / gate ratio (Rat10 of Gate Width / Gate Length). Adjusting the transistor, the gate width / gate length ratio of mpl can change the current of the transistor MPL,, and 'and thus affect the voltage level at node N1. Because the intersection of VN1 and VN2 is the most critical point, adjusting the gate width / gate length t of the transistor MPL will achieve the purpose of adjusting the control detection point. With regard to the second option mentioned above, in order to achieve detection point control within a predetermined range, such as the above-mentioned 0.3 volt specification as an example, the ideal reference voltage shown in Figure 8 will be very low. The level waveform shows that the dependence of the vehicle and voltage generator on the difference in temperature and temperature will not affect the difference in detection. In the voltage detection device of the preferred embodiment in FIG. 9, it can be known that if the value of the resistor R1 is fixed, the voltage VN1 of the node N1 will be fixed. In this circuit, the only factor that affects the difference in debt measurement points is Transistor II. It seems that the transistor MPL itself has process differences and temperature dependence, but if the resistance value of the resistor RL is carefully selected, its characteristics will make the effect of k-degree dependence relatively small. And this design! 1 9578twf.ptd Page 19 565848 V. Description of the Invention (16) The range of the detection point can be controlled within the above-mentioned predetermined range, regardless of process differences and temperature changes. ^ = The present invention has been disclosed as above with a preferred embodiment, but it is not intended to be limited to the present invention. Anyone skilled in the art can make various changes and modifications without departing from the scope of the present invention. Retouching, therefore, the scope of companion compliance of the present invention shall be determined by the scope of the appended patent application. Guarantee

第20頁 565848 圖式簡單說明 圖式之簡單說明: 第1圖係說明一種傳統的電壓偵測裝置方塊圖; 第2圖係說明第1圖中的傳統電壓偵測裝置詳細電路圖; 第3圖係說明第2圖中的傳統電壓偵測裝置之電路模擬結 果; 第4圖係說明第2圖中的傳統電壓偵測裝置,考慮操作溫度 之變化所得之電路模擬結果; 第5圖係說明一種電壓偵測裝置詳細電路圖; 第6圖係說明第5圖中之電壓偵測裝置之方塊圖; 第7圖係說明第5圖中之電壓偵測裝置之節點N1與N2之電壓 變化圖; 第8圖係說明第5圖中之電壓偵測裝置之節點N1與N2之另一 個電壓變化圖; 第9圖係說明本發明一較佳實施例之電壓偵測裝置之詳細 電路圖;以及 第1 0圖係理想之參考電壓值,與根據本發明第9圖較佳實 施例之電壓偵測裝置所產生之實際參考電壓值之比較圖。Page 565848 Simple illustration of the diagram Simple illustration of the diagram: Figure 1 illustrates a block diagram of a conventional voltage detection device; Figure 2 illustrates a detailed circuit diagram of the conventional voltage detection device in Figure 1; Figure 3 FIG. 4 illustrates a circuit simulation result of the conventional voltage detection device in FIG. 2; FIG. 4 illustrates a circuit simulation result of the conventional voltage detection device in FIG. 2 considering a change in operating temperature; and FIG. 5 illustrates a kind of Detailed circuit diagram of the voltage detection device; FIG. 6 is a block diagram illustrating the voltage detection device in FIG. 5; FIG. 7 is a diagram illustrating the voltage changes of the nodes N1 and N2 of the voltage detection device in FIG. 5; FIG. 8 is another voltage change diagram illustrating nodes N1 and N2 of the voltage detection device in FIG. 5; FIG. 9 is a detailed circuit diagram illustrating the voltage detection device of a preferred embodiment of the present invention; and FIG. The figure is a comparison diagram of the ideal reference voltage value and the actual reference voltage value generated by the voltage detection device according to the preferred embodiment of FIG. 9 of the present invention.

*-)578^ί. ptd 第21頁*-) 578 ^ ί. Ptd p. 21

Claims (1)

565848 六、申請專利範圍 1 · 一種低功率供應電壓偵測電路,用以接收一供應電 壓,包括 一比較電 壓產生器’根據該供應電壓產生並輸出一比較電 壓; 參考電壓產生 器,根據該供應電壓用以根據一線性相依 關係產生一參考電壓;以及 耦接到該比較電壓產生器與該參考電壓產 該比較電壓與該參考電壓並輸出一低電壓 一差異放大器, 以接收 ,其中 當該參考電壓大 一第一電壓位準 壓值, 當該考電 第二電壓 值。 2 ·如申 路,其中 該比較電 值時,該 3.如申 路,其中 生器,用 偵測信號 壓電路分 括一第一 組 壓小於 位準, 請專利 該比較 壓亦同 比較電 請專利 該比較 為兩組 電阻所 成,其 於該比較電壓時,該低電壓偵測信號將為 ,用以表示該供應電壓低於一預定偵測電 該比較電壓時,該低電壓偵測信號將為一 用以表示該供應電壓高於該預定偵測電壓 範圍第1項所述之低功率供應電壓偵測電 電壓產生器係根據在該供應電壓增加時, 時增加,但當該供應電壓超過一預定電壓 壓將會趨近一固定電壓值。 範圍第2項所述之低功率供應電壓偵測電 電壓產生器係包括一分壓電路,其中該分 據以分壓該供應電壓’其中該第一組係包 組成,該第二組係包括一皇、三i阻齊―一雷 中565848 6. Scope of patent application 1 · A low-power supply voltage detection circuit for receiving a supply voltage, including a comparison voltage generator 'to generate and output a comparison voltage according to the supply voltage; a reference voltage generator according to the supply The voltage is used to generate a reference voltage according to a linear dependency relationship; and the reference voltage generator and the reference voltage are coupled to generate the comparison voltage and the reference voltage and output a low voltage-difference amplifier to receive, wherein when the reference The voltage is greater than the first voltage level voltage value, and the second voltage value when the test is performed. 2 · Rushen Road, where the electrical value is compared, the 3. Rushen Road, where the generator, uses the detection signal voltage circuit to include a first set of voltages less than the level, please patent the comparison pressure and compare Please call for patent. The comparison is made by two sets of resistors. When the comparison voltage is used, the low voltage detection signal will be used to indicate that the supply voltage is lower than a predetermined detection voltage. The test signal will be a low-power supply voltage detection electric voltage generator used to indicate that the supply voltage is higher than the predetermined detection voltage range described in item 1 according to when the supply voltage increases, but when the A supply voltage exceeding a predetermined voltage will approach a fixed voltage value. The low-power supply voltage detection electric voltage generator described in the second item of the scope includes a voltage dividing circuit, wherein the data is divided by the supply voltage, wherein the first group is composed of a package and the second group is Including one emperor and three i-Qi 9578twf.ptd 第22頁 565848 六、申請專利範圍 當該供應電壓增加時,該比較電壓係為該兩組隊供應電壓 分壓中之該第二組分壓值, 但當該供應電壓超過該第二組中的該電晶體之一臨限電壓 值後,該比較電壓將會趨近該臨限電壓值。 4 ·如申請專利範圍第1項所述之低功率供應電壓偵測電 路,其中該參考電壓產生器係根據該供應電壓之值,線性 地輸出該參考電壓,其中當該供應電壓減少時,該參考電 壓亦線性地減少,當該供應電壓增加時,該參考電壓亦線 性地增加。 5 ·如申請專利範圍第4項所述之低功率供應電壓偵測電 路,其中該參考電壓產生器係對該供應電壓經由一分壓電 路作分壓後線性地輸出該參考電壓值,其中該分壓電路分 為兩組據以分壓該供應電壓,其中該第一組係包括一電晶 體所組成’該第二組係包括一電阻所組成,而該參考電壓 即為該第二組之分壓。 6 ·如申請專利範圍第5項所述之低功率供應電壓债測電 路’其中該參考電壓可根據該第一組中的該電晶體之一閘 極寬度/閘極長度比調整大小,據以調整該電晶體之一臨 限電壓值而控制該低電壓偵測信號之電壓位準。 7 ·如申請專利範圍第1項所述之低功率供應電壓偵測電 路’其中在該比較電壓產生器之輸出端更包括一電容器, 用以保持該比較電壓之電位。 8 ·如申請專利範圍第1項所述之低功率供應電壓偵測電 路’其中在該參考電壓產生器之輪出端更包括一電容器,9578twf.ptd Page 22 565848 6. Scope of patent application When the supply voltage increases, the comparison voltage is the second component voltage value of the partial voltage of the two groups of supply voltage, but when the supply voltage exceeds the After one threshold voltage value of the transistor in the two groups, the comparison voltage will approach the threshold voltage value. 4 · The low-power supply voltage detection circuit as described in item 1 of the patent application range, wherein the reference voltage generator linearly outputs the reference voltage according to the value of the supply voltage, and when the supply voltage decreases, the The reference voltage also decreases linearly. When the supply voltage increases, the reference voltage also increases linearly. 5. The low-power supply voltage detection circuit according to item 4 of the scope of the patent application, wherein the reference voltage generator linearly outputs the reference voltage value after dividing the supply voltage through a voltage dividing circuit, where The voltage dividing circuit is divided into two groups to divide the supply voltage, wherein the first group includes a transistor, the second group includes a resistor, and the reference voltage is the second voltage. Partial pressure of the group. 6 · The low-power supply voltage debt test circuit described in item 5 of the scope of the patent application, wherein the reference voltage can be adjusted according to a gate width / gate length ratio of one of the transistors in the first group. Adjust a threshold voltage value of the transistor to control the voltage level of the low voltage detection signal. 7. The low power supply voltage detection circuit according to item 1 of the scope of the patent application, wherein a capacitor is further included at the output end of the comparison voltage generator to maintain the potential of the comparison voltage. 8 · The low-power supply voltage detection circuit described in item 1 of the scope of the patent application, wherein a capacitor is further included at the wheel output end of the reference voltage generator, ^578twf .ptci 第23頁 565848 六、申請專利範圍 用以保持該參考電壓之電位。 9.如申請專利範圍第1項所述之低功率供應電壓偵測電 路,其中更包括一反相裝置,用以接收該差異放大器之輸 出,並將該輸出反相後據以輸出該低電壓偵測信號。^ 578twf .ptci Page 23 565848 6. Scope of patent application Used to maintain the potential of the reference voltage. 9. The low-power supply voltage detection circuit according to item 1 of the patent application scope, further comprising an inverting device for receiving the output of the difference amplifier and inverting the output to output the low voltage according to the inversion Detection signal. 9578twf.ptd 第24頁9578twf.ptd Page 24
TW91118964A 2002-08-22 2002-08-22 Low power supply voltage detector circuit TW565848B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW91118964A TW565848B (en) 2002-08-22 2002-08-22 Low power supply voltage detector circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW91118964A TW565848B (en) 2002-08-22 2002-08-22 Low power supply voltage detector circuit

Publications (1)

Publication Number Publication Date
TW565848B true TW565848B (en) 2003-12-11

Family

ID=32502616

Family Applications (1)

Application Number Title Priority Date Filing Date
TW91118964A TW565848B (en) 2002-08-22 2002-08-22 Low power supply voltage detector circuit

Country Status (1)

Country Link
TW (1) TW565848B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI560565B (en) * 2015-11-30 2016-12-01 Ind Tech Res Inst Thermal simulation device and method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI560565B (en) * 2015-11-30 2016-12-01 Ind Tech Res Inst Thermal simulation device and method
US9773080B2 (en) 2015-11-30 2017-09-26 Industrial Technology Research Institute Thermal simulation device and method

Similar Documents

Publication Publication Date Title
KR100471330B1 (en) Semiconductor device having a voltage regulator
TW408477B (en) Voltage boost circuit and semiconductor memory
TW409395B (en) Potential generation circuit
US6937088B2 (en) Potential generating circuit capable of correctly controlling output potential
JP3759758B2 (en) Semiconductor memory device
US7859322B2 (en) Internal power-supply circuit
US8902678B2 (en) Voltage regulator
JP3362873B2 (en) Semiconductor device
KR980006526A (en) Intermediate voltage generator circuit and nonvolatile semiconductor memory having the same
US7193920B2 (en) Semiconductor memory device
US8588021B2 (en) Sense amplifier apparatus and methods
TWI737290B (en) Voltage generating circuit and semiconductor device
US7619464B2 (en) Current comparison based voltage bias generator for electronic data storage devices
US7414459B2 (en) Architecture for implementing an integrated capacitance
US20080266996A1 (en) Memory power supply circuit
WO2012050604A1 (en) Fast and accurate current driver with zero standby current & features for boost and temperature compensation for mram write circuit
JP2011034658A (en) Semiconductor memory device, boosting method of word line, and system
JP3186034B2 (en) Reference voltage generation circuit
KR100803363B1 (en) Circuit for generating voltage of semiconductor memory apparatus
US8203891B2 (en) Voltage sensing circuit capable of controlling a pump voltage stably generated in a low voltage environment
US7859135B2 (en) Internal power supply circuit having a cascode current mirror circuit
US6480421B2 (en) Circuit for reading non-volatile memories
TW565848B (en) Low power supply voltage detector circuit
US11262783B2 (en) Systems and methods for initializing bandgap circuits
JP2002042496A (en) Ferroelectric memory

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent