TW565104U - Detecting apparatus for lamination of multi-layered circuit board - Google Patents

Detecting apparatus for lamination of multi-layered circuit board

Info

Publication number
TW565104U
TW565104U TW91217185U TW91217185U TW565104U TW 565104 U TW565104 U TW 565104U TW 91217185 U TW91217185 U TW 91217185U TW 91217185 U TW91217185 U TW 91217185U TW 565104 U TW565104 U TW 565104U
Authority
TW
Taiwan
Prior art keywords
lamination
circuit board
detecting apparatus
layered circuit
layered
Prior art date
Application number
TW91217185U
Other languages
Chinese (zh)
Inventor
Chiu-Feng Huang
Original Assignee
Usun Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Usun Technology Co Ltd filed Critical Usun Technology Co Ltd
Priority to TW91217185U priority Critical patent/TW565104U/en
Publication of TW565104U publication Critical patent/TW565104U/en

Links

TW91217185U 2002-10-25 2002-10-25 Detecting apparatus for lamination of multi-layered circuit board TW565104U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW91217185U TW565104U (en) 2002-10-25 2002-10-25 Detecting apparatus for lamination of multi-layered circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW91217185U TW565104U (en) 2002-10-25 2002-10-25 Detecting apparatus for lamination of multi-layered circuit board

Publications (1)

Publication Number Publication Date
TW565104U true TW565104U (en) 2003-12-01

Family

ID=32503490

Family Applications (1)

Application Number Title Priority Date Filing Date
TW91217185U TW565104U (en) 2002-10-25 2002-10-25 Detecting apparatus for lamination of multi-layered circuit board

Country Status (1)

Country Link
TW (1) TW565104U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100490603C (en) * 2005-09-30 2009-05-20 环隆电气股份有限公司 Circuit board with verified laminated layer sequence

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100490603C (en) * 2005-09-30 2009-05-20 环隆电气股份有限公司 Circuit board with verified laminated layer sequence

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Legal Events

Date Code Title Description
GD4K Issue of patent certificate for granted utility model filed before june 30, 2004
MM4K Annulment or lapse of a utility model due to non-payment of fees