TW561131B - Micro-electromechanical system and its fabricating method - Google Patents

Micro-electromechanical system and its fabricating method Download PDF

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TW561131B
TW561131B TW92106406A TW92106406A TW561131B TW 561131 B TW561131 B TW 561131B TW 92106406 A TW92106406 A TW 92106406A TW 92106406 A TW92106406 A TW 92106406A TW 561131 B TW561131 B TW 561131B
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layer
dielectric layer
scope
dielectric
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TW92106406A
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TW200418714A (en
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Anchor Chen
Gary Hong
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United Microelectronics Corp
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Abstract

A cantilever beam type micro-electromechanical system (MEMS) is formed on a substrate. Two first electrodes are formed in a first dielectric layer on the substrate and a waveguide line is formed between the first electrodes. A patterned sacrificial layer and an arm layer are formed on the substrate. Two second electrodes and a second dielectric layer are formed in the arm layer, and an optical grating is formed in the second dielectric layer. Finally, a cap layer is formed on the substrate, and the patterned sacrificial layer is removed.

Description

561131 五、發明說明α) 發明所屬之技術領域 本發明係提供一種微機電系統 (Micro-Electromechanical System,MEMS)的製作方法, 尤指一種應用於光纖通訊領域中之懸臂樑(cant i lever be am)式微機電系統的製作方法。 先前技術 在網際網路日益普及和高傳輸容量快速成長下,為了 解決網路呈現壅塞的狀況,已陸續提出纜線數據機(cabl( modem)、非同步數位用戶迴路(ADSL)和時間多工與波長多 工相結合的高密度波長多工通訊系統(d e n s e wavelength-division multiplexing, DWDM)等解決方 法。其中由於DWDM系統具有可在單一條光纖中同時使用多 個波長的光信號,使得光纖網路容量大幅增加之優點,故 已成為目前最重要的光纖通訊架構之一。 一個完整的DWDM光纖系統包括有光發射/接收器、波 長多工器/解多工器、光纖放大器(EDFA)、波長擷取多工 器、色散補償裝置、濾波器、光開關路由器及其他光通訊 元件、處理電路與架構光學系統的機構等。在光纖通訊領 域中,製作高密度波長多工器的技術可分為光學濾片式、 光纖光柵式、光纖耦合器以及光波導型等。其中,光學滤561131 V. Description of the invention α) Technical field to which the invention belongs The present invention provides a method for manufacturing a micro-electromechanical system (MEMS), especially a cantilever beam (cant i lever be am) used in the field of optical fiber communication ) Type micro-electro-mechanical system manufacturing method. In the past, with the increasing popularity of the Internet and the rapid growth of high transmission capacity, in order to solve the network congestion situation, cable modems (cabl (modem), asynchronous digital subscriber loop (ADSL), and time multiplexing have been proposed successively. Solutions such as dense wavelength-division multiplexing (DWDM) combined with wavelength multiplexing. Among them, the DWDM system has the ability to use multiple wavelengths of optical signals in a single fiber at the same time, making the fiber network The advantage of a large increase in channel capacity has become one of the most important optical fiber communication architectures at present. A complete DWDM optical fiber system includes optical transmitter / receiver, wavelength multiplexer / demultiplexer, fiber amplifier (EDFA), Wavelength acquisition multiplexers, dispersion compensation devices, filters, optical switch routers and other optical communication components, processing circuits and structures of optical systems, etc. In the field of optical fiber communications, the technology for making high-density wavelength multiplexers can be divided Optical filter type, fiber grating type, fiber coupler and optical waveguide type etc. Among them, optical filter

561131 五、發明說明(2) 片式主要是利用稜鏡(prism)或薄膜干涉濾鏡(thin film filter, TFF),光纖光栅是主要是利用各種光栅, 例如布拉格光纖光栅(Fiber Bragg Grating, FBG)或陣列 波導光柵(arrayed waveguide grating,AWG)等,而光纖 搞合器主要是利用各種干涉儀(如Fabry-Perot Interferometer、Mach-Zehnder)等物理機制來達到光學 上多通道之濾波、分光的目的。 從實際應 做到8個波長 到6 4個波長以 約在32個波長 前雖以薄膜干 為嚴格,因此 現行以濾片為 波導光柵技術 贫:,在因應於 可能取代濾片 用的觀點而言, ,適合區域網路 上’適合長途的 内。此外,由製 涉濾鏡最具熱穩 良率不高且成本 主流的分波技術 ’其主要利用平 未來對高通道數 成為市場主流。 成本低廉的光纖耦合器只能 ,光纖光柵及光波導型可達 通訊網路,而光學濾片式則 程技術的前瞻性來評估,目 定性,但由於其光學需求極 昂貴,所以仍無法完全取代 ’但類似半導體製程的陣列 面光波導法耦合出所需的波 需求日增的趨勢下,便極有 這種結合了光、機和電 造出來的微機電系統,將可 持在光的形式,亦即光一光 層的架構’而且由於微機電 ;教結構’使仔微機電系統在 的特性並利用半導體製程所製 使得資料傳遞過程中,一直保 傳輸’不需要轉換至電子資訊 技術亦可製造出可調變控制的 光纖通訊暨無線射頻通訊方面561131 V. Description of the invention (2) The chip mainly uses prism or thin film filter (TFF), and the fiber grating mainly uses various gratings, such as Fiber Bragg Grating (FBG) ) Or arrayed waveguide grating (AWG), etc., and the optical fiber coupler mainly uses various interferometers (such as Fabry-Perot Interferometer, Mach-Zehnder) and other physical mechanisms to achieve optical multi-channel filtering and beam splitting purpose. It should be from 8 wavelengths to 64 wavelengths. Actually, the thickness of the thin film is strict before about 32 wavelengths. Therefore, the current technology of using filters as waveguide gratings is poor: in view of the possibility of replacing filters In other words, it is suitable for long-distance calls on a local network. In addition, the filter that is manufactured by the most popular thermal splitter technology, which has the lowest thermal stability and low cost, is mainly used in the future, and it has become the mainstream in the market. Low-cost fiber couplers can only reach fiber optic gratings and optical waveguides to reach communication networks, while optical filter technology is evaluated prospectively and objectively, but because its optical requirements are extremely expensive, it still cannot be completely replaced. 'However, the array surface optical waveguide method similar to the semiconductor process has a growing demand for coupling the required waves, and this micro-electro-mechanical system combining optical, mechanical and electrical manufacturing will be extremely light. That is, the structure of the light-optical layer 'and because of the micro-electromechanical and electrical structure, the structure allows the characteristics of the micro-electro-mechanical system and the use of semiconductor processes to ensure the transmission during the data transfer process. It is not necessary to switch to electronic information technology. Manufacturing adjustable optical fiber communication and wireless RF communication

561131 五、發明說明(3) 業已受到廣泛的重視。因此,隨著光纖通訊的急速成長, 利用微機電製程技術已成功地切入光通訊元件的市場,同 時在DWDM系統上逐漸取代光-電-光轉換程序中延遲整個寬 頻通訊系統的光電開關元件。 容 内 明 發 統 機 微 式 樑 臂 懸 •ft 種 一 供 提 於 在 的 因 要 主 之。 明法 發方 本作 製 的 低 具 且 化 簡 驟。 步法 程方 製作 種製 一的 供統 提系 ^,^ 在機 的微 目式 要樑 次臂 之懸 明之 發本 本成 造 製 域元 領關 訊開 通電 纖光 光作。 於當統 用一 系 應造電 種製機 一來微 供用的 提,光 於法分 在方或 的作波 目製濾 1的之 另統道 之系通 明電多 發機行 本微進 之以 中件 本發明之最佳實施例係揭露了一種懸臂樑 (cantilever beam)式微機電系統 (Micro-Electromechanical System, MEMS)的製作方法, 該懸臂樑式微機電系統係製作於一半導體基底上,且該半 導體基底表面包含有一重摻雜層以及一第一介電層 (dielectric layer)。首先於該第一介電層中形成至少二 通達該重摻雜層表面之第一導體(conductor),接著於該561131 V. Description of invention (3) It has been paid much attention. Therefore, with the rapid growth of optical fiber communication, the use of micro-electro-mechanical process technology has successfully cut into the market of optical communication components, and at the same time, DWDM systems have gradually replaced the optical-electrical-optical switching components of the optical-electrical-optical conversion process that delay the entire broadband communication system. Rong Neiming ’s micro-beam arm suspension of the machine • ft is a mainstay of supply and supply. The Mingfa issuer's original system is simple and simplified. In the footwork, the method is to produce a system of supply and system. ^, ^ The micro-mechanism of the machine is the main beam of the secondary arm. Yu Dangtong uses a series of electric power generation machines to make micro-supply for use. The only way to do it is to use the same method as the wave filter system 1. The Tongming electric multi-function machine is based on micro-advance The preferred embodiment of the present invention discloses a method for manufacturing a cantilever beam type micro-electromechanical system (MEMS). The cantilever type micro-electromechanical system is fabricated on a semiconductor substrate, and the The surface of the semiconductor substrate includes a heavily doped layer and a first dielectric layer. First, at least two first conductors are formed in the first dielectric layer to reach the surface of the heavily doped layer, and then in the first dielectric layer,

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561131 五、發明說明(4) 等第一導體間之該第一介電層中形成一 介電層 第二介電層不接觸該重摻雜層表面,然後於該半導 上形成-圖案化犧牲層’並覆蓋於該第二介電 J底 介電層以及各該第-導體之上,冑後於該半導體基底卜 成一第二介電層來覆蓋該圖案化犧牲層,再於該第 % 層中=-第四介電層,且該第四介電層不接觸該電 犧牲層表面,之後於該第三介電層表面形成至少二^案化 體,且各該第二導體係分別位於該第二介電層兩側^導 第一導體的上方,最後蝕刻該第四介電層,以於誃^該等 電層中形成複數個開口,並在該半導體基底上形^第四介 (cap)層以覆蓋各該第二導體、該第四介電層以 頂蓋 介電層之後,再去除該圖案化犧牲層。 邊第三 度其不機不 密且故微, 高,,於作 之用作由運 式功製,可 柵之來外即 光光術此量 纖分技。能 光與與本少 合波備成極 結濾設品要 係之程產需 統道製低僅。 系通體降此短 電多導作因較 機行半製,間 微進般量小時 之以一大寸應 明用用可尺反 發,利且積且 本器係單體少 於工法簡之較 由多方程統能 長作製系耗 波製僅電但 實施方式561131 V. Description of the invention (4) A dielectric layer is formed in the first dielectric layer between the first conductors and the like. The second dielectric layer does not contact the surface of the heavily doped layer, and then is formed on the semiconductor-patterning. The sacrificial layer 'covers the second dielectric J-bottom dielectric layer and each of the first conductors, and then forms a second dielectric layer on the semiconductor substrate to cover the patterned sacrificial layer, and then the first sacrificial layer. % Layer = -the fourth dielectric layer, and the fourth dielectric layer does not contact the surface of the electric sacrificial layer, and then at least two crystalline materials are formed on the surface of the third dielectric layer, and each of the second conductive systems They are respectively located above the first conductor on both sides of the second dielectric layer, and finally the fourth dielectric layer is etched to form a plurality of openings in the electric layers, and form a first on the semiconductor substrate. After the four cap layers cover each of the second conductors, the fourth dielectric layer covers the dielectric layer, and then the patterned sacrificial layer is removed. The third time, it is not confidential and it is so small and high that it is used as an operational power system. It can be used outside the light beam to split the light. The production process of light and the combination of this and a small junction to produce a pole junction filter system requires a low level of system control. The short circuit and multi-conductor operation of the whole body is more semi-systematic than the machine. If the amount of time is small, it should be reversed with a large inch when the amount is small. It is beneficial and the product is less than the simple method. Compared with the multi-equipment system, which can produce a long-term system, the wave-consumption system only uses electricity, but the implementation mode

561131 五、發明說明(5) 可應用於一 P型半導體基底、磊晶矽基底或矽複絕緣基底 上。請參考圖一至圖十三,圖一至圖十三為製作本發明之 懸臂樑式微機電系統1 0之方法示意圖,其中圖二為圖一沿 線I - I ’之剖面結構示意圖,圖四與圖五為圖三沿線丨丨—丨J, 之剖面結構示意圖,且圖八為圖七沿線III - I I I,之剖面結 構示意圖。561131 V. Description of the invention (5) It can be applied to a P-type semiconductor substrate, an epitaxial silicon substrate or a silicon composite insulating substrate. Please refer to FIG. 1 to FIG. 13. FIG. 1 to FIG. 13 are schematic diagrams of a method for manufacturing the cantilever beam type micro-electromechanical system 10 of the present invention, in which FIG. 2 is a schematic cross-sectional structure diagram along line I-I 'in FIG. 1, FIG. 4 and FIG. It is a schematic diagram of the cross-sectional structure along the line 丨 丨 --J, in FIG. 3, and FIG. 8 is a schematic cross-sectional structure along the line III-III, in FIG.

如圖一與圖二所示,首先進行一離子佈植製程,將構 (^11〇3 0〇5 6 1')離子植入一觀半導體基底12中,以於半導體 基底1 2表面形成一 N型重摻雜層1 4,並進行一快速加熱回 火(rapid thermal anneal, RTA)製程,以修補半導體基 底12之表面結構。接著於重摻雜層丨4上沉積一厚度較厚的 氧化層1 6,再於氧化層1 6上塗佈一光阻層(未顯示於圖一 與圖二中),並利用一微影暨蝕刻製程(ph〇t〇1丨th〇graphy etching process,PEP),來去除未被光阻層所覆蓋之氧 化層1 6 ’以於氧化層1 6中形成至少二通達重摻雜層丨4表面 之開口 1 8。然後去除光阻層,再於半導體基底丨2上沉積一 N型重摻雜多晶矽層(未顯示於圖一與圖二中),並使得該 多晶矽層填入開口 18中,隨後進行一化學機械研磨 访As shown in FIG. 1 and FIG. 2, an ion implantation process is first performed, and a conformation (^ 1103 0 05 6 1 ′) ion is implanted into a meso-semiconductor substrate 12 to form a surface on the surface of the semiconductor substrate 12. The N-type heavily doped layer 14 is subjected to a rapid thermal annealing (RTA) process to repair the surface structure of the semiconductor substrate 12. Next, a thicker oxide layer 16 is deposited on the heavily doped layer 4 and then a photoresist layer (not shown in FIGS. 1 and 2) is coated on the oxide layer 16 and a lithography is used. And etch process (ph〇t〇1 丨 th〇graphy etching process (PEP)) to remove the oxide layer 16 'that is not covered by the photoresist layer to form at least two heavily-doped layers in the oxide layer 丨4 的 面 口 1 8. Then, the photoresist layer is removed, and an N-type heavily doped polycrystalline silicon layer (not shown in FIGS. 1 and 2) is deposited on the semiconductor substrate 2 and the polycrystalline silicon layer is filled into the opening 18, and then a chemical mechanical process is performed. Grinding Interview

(chemical mechanical polishing,CMp)製程或一回蝕刻 (etching back)製程,去除氧化層16上之該多晶矽層,以 於氧化層16中形至少二電極2〇。接著於半導體基底12上形 成另一光阻層(未顯示於圖一與圖二中),並再利用一微影 暨蝕刻製程,去除未被光阻層所覆蓋部分之氧化層丨6,以A chemical mechanical polishing (CMp) process or an etching back process removes the polycrystalline silicon layer on the oxide layer 16 so that at least two electrodes 20 are formed in the oxide layer 16. Next, another photoresist layer (not shown in FIGS. 1 and 2) is formed on the semiconductor substrate 12, and a photolithography and etching process is used to remove the oxide layer that is not covered by the photoresist layer.

561131 五、發明說明(6) |於電極2 0間之氧化層1 6中形成一未通達重摻雜層丨4表面之 溝渠(trench)22。去除光阻層之後,再於半導體基底12上 沉積一氧化層(未顯不於圖一與圖二中)並填滿溝渠22,隨 後進行一化學機械研磨製程,去除電極2〇與氧化層16上之 |該氧化層,以於氧化層丨6中形成一光波導線 (waVegUide)24。其中,氧化層16與光波導線以具有不同 =射率:且形,電極2〇之材料可包含有金(g〇id,Au)、 )、銅(C〇PPer,Cu)、銘(al ㈣ hum,561131 V. Description of the invention (6) | A trench 22 is formed in the oxide layer 16 between the electrodes 20 and does not reach the surface of the heavily doped layer. After removing the photoresist layer, an oxide layer (not shown in FIGS. 1 and 2) is deposited on the semiconductor substrate 12 and the trench 22 is filled. Then, a chemical mechanical polishing process is performed to remove the electrode 20 and the oxide layer 16 The above | this oxide layer forms an optical waveguide line (waVegUide) 24 in the oxide layer 丨 6. Among them, the oxide layer 16 and the optical waveguide line have different emissivity: and shape. The material of the electrode 20 may include gold (goid, Au), copper (copper, Cu), and alumina (al ㈣). hum,

Al)、鋁銅a金(A卜Cu alloy)或其他導電材質。 丨以於Πίΐϋΐ ’進行一化學氣相沉積(CVD)製程, I 二ίϊί ί,?積一厚度約為 3微 * (micr_ter, 顯示於圖三中),再於犧牲層上塗佈-光 ^ 以形成-圖案化犧牲層 與氧化層U之上。:去除光二分f光波導線電極2〇 12上沉積-厚度大St:層之後’然後於半導體基底 化層28進行叫= =牲層26之氧化層以,並對氧 與圖案化犧牲層&之i表约$,使得氧化層28之上表面 U與氧化層28上形成一齊’再於圖案化犧牲層 中,形成犧牲層的二料米之氧化層3〇。其Al), aluminum copper (Ab Cu alloy) or other conductive materials.丨 In order to perform a chemical vapor deposition (CVD) process in I, the thickness is about 3 micrometers * (micr_ter, shown in Fig. 3), and then coated on the sacrificial layer-light ^ To form-pattern the sacrificial layer and the oxide layer U. : Remove the optical bifurcated f optical waveguide line electrode 012-deposited after a large thickness of St: layer, and then perform an oxidation layer on the semiconductor base layer 28 = = = layer 26, and the oxygen and patterned sacrificial layer & I represents about $, so that the upper surface U of the oxide layer 28 and the oxide layer 28 are formed together, and then the patterned sacrificial layer is formed to form a two-meter oxide layer 30 of the sacrificial layer. its

Ho:) I:、有機聚合物或多孔石夕(—_ )而氣化層28係用來當作本發明之懸臂樑式微機 第10頁 561131 五、發明說明(7) 2 ί ίί 固疋柱(anCh〇r)結構,主要是將後續形成的微 二ΐ Ιί半導體基底i£上,防止微結構在後續圖案化犧 牲層2 6去除的過程中受到影響。Ho :) I :, organic polymer or porous stone (—_) and the gasification layer 28 is used as the cantilever type microcomputer of the present invention. Page 10 561131 V. Description of the invention (7) 2 ί ί 疋The pillar (anChor) structure is mainly formed on a semiconductor substrate formed subsequently to prevent the microstructure from being affected during the subsequent removal of the patterned sacrificial layer 26.

如圖四所示,接著於氧化層3〇上塗佈一光阻層(未顯 不於圖四令),並進行一微影暨蝕刻製程,去除未被光阻 層所覆蓋部分之氧化層3〇,以於氧化層3〇中形成一未通達 圖案化犧牲層26表面之溝渠36,隨後再利用一沉積製程以 及一,學機械研磨製程,以於氧化層3 〇中形成一填入溝渠 36之氧化層38,且氧化層38之上表面與氧化層30之上表面 約略切齊。然後再於氧化層30上形成一厚度約為〜〇· 8微米 之金屬層與一光阻層(未顯示於圖四中),並進行一微影暨 #刻製程’先去除未被光阻層所覆蓋之金屬層,以形成至 少二電極40,且電極40係分別位於光波導線24兩側之電極 20的相對上方,接著再去除光阻層。其中,氧化層3〇與氧 化層38具有不同之折射率,且形成電極4〇的材料可包含有 金(gold, Au)、鎢(tungsten, ff)、銅(copper, Cu)、鋁 (aluminum, Al)、I呂銅合金(ai—Cu alloy)、多晶石夕戋其 他導電材質。 < 、 然一後如圖五所示,於半導體基底丨2上形成另一光阻層橹 (未顯示於圖五中),並進行一微影暨蝕刻製程,去除未被 光阻層所覆蓋之氧化層3 8,以於氧化層3 8中形成複數個具 有等間距、4寬度以及等深度之開口 4 2,用來於氧化層3 8 561131 五、發明說明(8) 令構成光栅(optical grating),接著再於半導體基底12 上形成一頂蓋(cap)層44,且頂蓋層44覆蓋於開口 42、電 極4 0、氧化層3 8與氧化層3 0之上。其中,開口 4 2之深度約 為1. 5微米,且頂蓋層44為一氧化層。 如圖六與圖七所示,於半導體基底丨2上形成一圓案化 光阻層(未顯示於圖六與圖七中),並進行一乾蝕刻製程, 去除未被圖案化光阻層所覆蓋之頂蓋層44與氧化層3〇 ,以As shown in Figure 4, a photoresist layer is then coated on the oxide layer 30 (not shown in Figure 4), and a lithography and etching process is performed to remove the oxide layer that is not covered by the photoresist layer. 30, in order to form a trench 36 on the surface of the unpatterned patterned sacrificial layer 26 in the oxide layer 30, and then use a deposition process and a mechanical polishing process to form a filled trench in the oxide layer 30 The oxide layer 38 of 36, and the upper surface of the oxide layer 38 is approximately aligned with the upper surface of the oxide layer 30. Then, a metal layer and a photoresist layer (not shown in FIG. 4) with a thickness of ~ 0.8 μm are formed on the oxide layer 30, and a photolithography and #etching process is performed to remove the unresisted photoresist. A metal layer covered by the layer to form at least two electrodes 40, and the electrodes 40 are respectively located above the electrodes 20 on both sides of the optical waveguide line 24, and then the photoresist layer is removed. The oxide layer 30 and the oxide layer 38 have different refractive indices, and the material forming the electrode 40 may include gold (Au), tungsten (Tungsten (FF)), copper (Copper, Cu), and aluminum (aluminum). , Al), I-Cu alloy (ai-Cu alloy), polycrystalline stone 戋 other conductive materials. < Then, as shown in FIG. 5, another photoresist layer 橹 (not shown in FIG. 5) is formed on the semiconductor substrate 2 and a lithography and etching process is performed to remove the photoresist layer. The covered oxide layer 38 is used to form a plurality of openings 4 2 having equal pitch, 4 width and equal depth in the oxide layer 3 8 for the oxide layer 3 8 561131 V. Description of the invention (8) Let the grating be formed ( optical grating), and then a cap layer 44 is formed on the semiconductor substrate 12, and the cap layer 44 covers the opening 42, the electrode 40, the oxide layer 38, and the oxide layer 30. The depth of the opening 42 is about 1.5 micrometers, and the cap layer 44 is an oxide layer. As shown in FIGS. 6 and 7, a circular photoresist layer (not shown in FIGS. 6 and 7) is formed on the semiconductor substrate 2 and a dry etching process is performed to remove the uncovered photoresist layer. The capping layer 44 and the oxide layer 30.

於氧化層30中形成至少一蝕刻窗(etch h〇ie)46,蝕刻窗 4 6=數里依微機電系統之尺寸大小與後續蝕刻速率有關, 接f進行一結構釋放(structure releasing)製程,例如 二ίηϊ t liS〇tr〇PiC)濕姓刻製程,將懸臂樑式微機電系 ί 蝕刻液t,使蝕刻液得以經由蝕刻窗46均勻ϋ 快速^侧向蝕刻其下方之圖案化犧 間’進而降低結構層在去除圖案 的過紅中可靶受到蝕刻或腐蝕,以於形一 rislng)與乾燥製程’又為了 =二 2At least one etch window 46 is formed in the oxide layer 30. The etch window 46 = several miles depends on the size of the micro-electromechanical system and the subsequent etching rate. Then a structure releasing process is performed. For example, the process of engraving the wet surname with the two ϊηϊ t liS trOPiC), cantilever type micro-electro-mechanical system 蚀刻 etching solution t, so that the etching solution can be uniformly etched through the etching window 46 quickly and laterally etch the patterned sacrificial layer below it 'further The reduced structure layer can be etched or corroded during the removal of the over-red pattern, so that the shape is a rislng) and the drying process is performed in order to = 2 2

離子鍵等作用力大於微結構的回;表&靜電力或 結構與半導體基底12之間如彈力時’而使微 致微機電系統10益法操作,太i^^stlctlon)的現象,導 Τ ^ (burap)(A ;V ^ ^ ^ ^ 30^ 低微結構與半導體Λ i 2 ^不於圖/、至圖八中),以降 千等體基底12之接觸面積,改善沾黏狀況。 561131 五、發明說明(9) 值得注意的是,如圖九所示之本發明第二實施例,本 發,之懸臂,式微機電系統丨〇亦可於形成圖案化犧牲層2 6 之前:先於氧化層16上另形成一黏著(glue:^ 32 ,且黏著 層32係覆蓋於氧化層16、電極2〇與光波導線24之上,用來 =加圖案化犧牲層2 6與氧化層16之黏合度,或是於形成圖 ^化犧牲層26之後,再於氧化層16上形成一阻擋(M〇ck) ς 3 4 ’用來覆蓋住圖案化犧牲層2 6 ,以避免後續製程對圖 :^犧牲層26造成影響。其中,黏著層32與阻擋層34可視 ^程之實,需要,僅形成其中一層或兩層都製備,而且所 形成之黏著層3 2與阻擋層3 4亦可選擇性地於去除圖案化犧 牲層26時一併去除,如圖十與圖十一所示。 此外,如圖十二所示,本發明之懸臂樑式微機電系絶 ^0,電極40亦可於形成氧化層38之前,先形成於氧化層3〇 中:其形成的方法係先於氧化層3 〇中形成至少二開口(未 ^不於-圖十二中),接著於半導體基底12上沉積一導電層 顯示於圖十二中),並使得該導電層填入該二開口中, 最,再利用一化學機械研磨製程,以使該導電層之上表面 與乳化層30之上表面約略切齊,構成二電極40。 、本發明之懸臂樑式微機電系統1 0主要應用於光纖通訊 =域中,用來當作一光開關元件,以進行濾波或分光的動 4 ’因此在光波導線2 4之最前端有製作光波之輸入或輸出The ionic bond and other forces are greater than the microstructure's back; the table & electrostatic force or the structure and the semiconductor substrate 12 such as when the spring force ', so that the micro-electro-mechanical system 10 operating efficiently, too i ^^ stlctlon) phenomenon, Τ ^ (burap) (A; V ^ ^ ^ ^ 30 ^ Low microstructure and semiconductor Λ i 2 ^ are not shown in the figure /, to figure 8), to reduce the contact area of the isomorphic substrate 12 to improve the adhesion. 561131 V. Description of the invention (9) It is worth noting that the second embodiment of the present invention shown in FIG. 9 is a cantilever-type micro-electro-mechanical system according to the present invention. Before forming the patterned sacrificial layer 2 6: An additional adhesive (glue: ^ 32) is formed on the oxide layer 16, and the adhesive layer 32 covers the oxide layer 16, the electrode 20, and the optical waveguide 24, and is used to add a patterned sacrificial layer 26 and the oxide layer 16 After forming the patterned sacrificial layer 26, a barrier (Mock) on the oxide layer 16 is formed. 3 ′ 3 ′ is used to cover the patterned sacrificial layer 2 6 to avoid subsequent process damage. Figure: ^ sacrificial layer 26 affects. Among them, the adhesive layer 32 and the barrier layer 34 can be seen, and it is necessary to prepare only one or two layers, and the formed adhesive layer 32 and the barrier layer 34 can also be selected. When the patterned sacrificial layer 26 is removed, it is removed together, as shown in Fig. 10 and Fig. 11. In addition, as shown in Fig. 12, the cantilevered micro-electromechanical system of the present invention is absolutely zero. Before the oxide layer 38 is formed, it is first formed in the oxide layer 30: its formation method is prior to the oxidation 30, at least two openings are formed (not shown in FIG. 12), and then a conductive layer is deposited on the semiconductor substrate 12 (shown in FIG. 12), and the conductive layer is filled into the two openings. Then, a chemical mechanical polishing process is used to make the upper surface of the conductive layer and the upper surface of the emulsified layer 30 approximately aligned to form the two electrodes 40. 3. The cantilevered micro-electromechanical system 10 of the present invention is mainly used in the optical fiber communication field, and is used as an optical switching element to perform filtering or light splitting. Therefore, there is a light wave at the forefront of the optical waveguide line 24. Input or output

第13頁 561131 五、發明說明(ίο) 端的夾具(未顯示於圖中) 線2 4之光纖輸入端時,並外加 會產生靜電力以拉近上下電極 改變孔穴48的高度,如圖十三 電系統1 0之可調變的功能,此 與周圍氧化層16具有不同折射 遞,當光波到達分光用之光栅 口 4 2中進行反射以耦合出所需 光波會再經由光波導線24返回 之所需波長的光波可另外輸出 多波長予以分開輸出之功能。 當 多波長訊 以一電壓 20、 40間 所示,而 時,多波 率之光波 區時,光 波長的光 輸出端^ ,以達到 號被 ,例 的距 達到 長之 導線 波會 波, 而經 將原 導入一 如1 2伏 離,亦 懸臂樑 光波會 24中往 在光柵 之後多 過光柵 先混合 光波導 特,則 即同時 式微機 侷限在 前傳 區的開 波長之 區分光 輸入之 簡而言之’本發明應用於光學上之懸臂樑式微機電系 統具有下列優點:(1 )由於光本身不具質量,因此只需很 小的能量即可驅動微機電系統,(2 )對光而言,微小位移 (接近波長的距離)即可對光波的物理現象及其特性(波 長、光強、相位等)有顯著的作用,(3 )尺寸微小之微機電 系統具有迅速反應與快速運動的特性,(4 )若不需與環境 作直接的接觸,則具有容易封裝的特性,(5 )大量運用既 有之半導體製程設備及技術,便可大量製造出品質穩定之 微機電系統,不僅使其具有整體成本降低的潛力,也具有 高度商業化之可行性。 以上所述僅為本發明之較佳實施例,凡依本發明申請Page 13 561131 V. Fixture of the invention (ίο) end (not shown in the figure) When the optical fiber input end of line 2 4 is applied, an electrostatic force will be generated to close the upper and lower electrodes to change the height of the hole 48, as shown in Figure 13. The tunable function of the electrical system 10 is different from that of the surrounding oxide layer 16. When the light wave reaches the grating port 42 for beam splitting and is reflected to couple out the required light wave, it will return to the place via the optical waveguide line 24 The function that requires a wavelength of light can output multiple wavelengths separately. When the multi-wavelength signal is shown by a voltage between 20 and 40, and when the multi-wavelength light wave region, the light output end of the light wavelength ^, to reach the signal, for example, the distance reaches the long wire wave, and After introducing the original as 12 volts away, the cantilever beam wave 24 will be mixed with the optical waveguide characteristics after the grating, and then the grating will be mixed with the optical waveguide first. In other words, the invention cantilever beam type micro-electro-mechanical system applied to optics has the following advantages: (1) because the light itself has no mass, only a small amount of energy can be used to drive the micro-electro-mechanical system; (2) for light, A small displacement (distance close to the wavelength) can have a significant effect on the physical phenomena of light waves and their characteristics (wavelength, light intensity, phase, etc.). (3) Micro-electromechanical systems with small dimensions have the characteristics of rapid response and rapid movement. (4) If it is not necessary to make direct contact with the environment, it has the characteristics of easy packaging. (5) Extensive use of existing semiconductor process equipment and technology can produce a large number of stable quality products. Micro-electro-mechanical systems not only have the potential to reduce overall costs, but also have high commercial feasibility. The above are only the preferred embodiments of the present invention.

第14頁 561131 五、發明說明(11) 專利範圍所作之均等變化與修飾,皆應屬本發明專利之涵 蓋範圍。 第15頁 561131 圖式簡單說明 圖式之簡單說明 圖一至圖十三為本發明最佳實施例製作懸臂樑式微機 電系統之方法示意圖。 圖式之符號說明 10 懸臂樑式微機電系統 12 半導體基底 14 重摻雜層 16 氧化層 18 開口 20 電極 22 溝渠 24 光波導線 26 圖案化犧牲層 28 氧化層 30 氧化層 32 黏著層 34 阻擋層 36 溝渠 38 氧化層 40 電極 42 開口 44 頂蓋層 46 蝕刻窗Page 14 561131 V. Description of the invention (11) Equal changes and modifications made to the scope of the patent shall all fall within the scope of the invention patent. Page 15 561131 Brief description of the drawings Brief description of the drawings Figures 1 to 13 are schematic diagrams of a method for manufacturing a cantilever type microcomputer electrical system according to the preferred embodiment of the present invention. Description of Symbols 10 Cantilever MEMS 12 Semiconductor substrate 14 Heavyly doped layer 16 Oxidation layer 18 Opening 20 Electrode 22 Trench 24 Optical waveguide 26 Patterned sacrificial layer 28 Oxidation layer 30 Oxidation layer 32 Adhesive layer 34 Barrier layer 36 trench 38 oxide layer 40 electrode 42 opening 44 cap layer 46 etching window

第16頁Page 16

Claims (1)

561131 六'申請專利範圍 1· 一種懸臂樑(cantilever beam)式微機電系統 (Micro-Electromechanical System, MEMS)的製作方 該製作方法包含有下列步驟·· + ’ 提供一半導體基底,且該半導體基底表面包含有_^ 摻雜層以及一第一介電層(dielectric layer); 第 於該第一介電層中形成至少二通達該重摻雜層表面之 導體(conductor); 於該等第一導體間之該第一介電層中形成一第二介 層,且該第二介電層不接觸該重掺雜層表面; 於該半導體基底上形成一圖案化犧牲層,並覆蓋於該 第二介電層、該第一介電層以及各該第一導體之上;“ 於該半導體基底上形成一第三介電層,並覆蓋該 化犧牲層; 且該第四介電 於該第三介電層中形成一第四介電層 層不接觸該圖案化犧牲層表面·, 各該第 於該第三介電層表面形成至少二第二^#你矛 二導體係分別位於該第二介電層兩側之該$ g 一 $ & = 1 方; 蝕刻該第四介電層,以於該第四介電層中形成複數個 開口 ; 亥半導體基底上形成一頂蓋(c ), 第二該第四介電層以及該第三介電曰層主以覆及蓋各 去除δ亥圖案化犧牲層。561131 Six 'application patent scope 1. A method for manufacturing a cantilever beam type micro-electromechanical system (MEMS) The manufacturing method includes the following steps: +' Provide a semiconductor substrate, and the surface of the semiconductor substrate Including a doped layer and a first dielectric layer; forming at least two conductors in the first dielectric layer that reach the surface of the heavily doped layer; in the first conductors A second dielectric layer is formed in the first dielectric layer, and the second dielectric layer does not contact the surface of the heavily doped layer. A patterned sacrificial layer is formed on the semiconductor substrate and covers the second dielectric layer. A dielectric layer, the first dielectric layer, and each of the first conductors; "a third dielectric layer is formed on the semiconductor substrate and covers the sacrificial layer; and the fourth dielectric is on the third A fourth dielectric layer is formed in the dielectric layer without contacting the surface of the patterned sacrificial layer. Each of the second dielectric layers is formed on the surface of the third dielectric layer. At least two second conductive systems are located on the second. $ On both sides of the dielectric layer g a $ & 1 square; etching the fourth dielectric layer to form a plurality of openings in the fourth dielectric layer; forming a cap (c) on the semiconductor substrate, and secondly the fourth dielectric layer The layer and the third dielectric layer cover and cover each to remove the delta patterned sacrificial layer. 561131 六、申請專利範圍 ___ t^ Γ請專利範圍第1項之製作方法,其中於形成兮® ^成兮^層之前,另包含有一黏著(glUe)層形成步驟"圖 黏著層於該第-介電層、,第二介電層以及:蓉: 一導體之上。 曰乂久该等第 案化i ί ί i,圍ί2項之製作方法’其中於去除該圖 '、攝牲層時,亦同時去除該點著層。 4·如申請專利範圍第1項之製作方法,直中於报占:同 ίλ ^ ^ ^ ^ t 另匕3有一阻擋(bl〇ck)層形成步驟, ^ί阻擒層於該圖案化犧牲層、$第-介電層、該第 一介電層以及該等第一導體之上。 步 ι·化t m利圍第4項之製作方法,其中於去除該圖 案化犧牲層時,亦同時去除該阻擋層。 ί.包ΪΠΠΓΓ項之製作方法…該第三介電 上表面約略與該圖宰:υ二氧化層,㈣-氧化層之 ,、圃茶化犧牲層之上表面相切齊。 7. 如申請專利範圍第1項之製作方法,Α中去呤兮圖茔 化犧牲層的方法係為—等^ 纟中去除该圖案 q 寻句性濕蝕刻製程。 8. 如申請專利範圍7項之製作方法,其中於去除該圖案561131 6. Scope of patent application ___ t ^ Γ Please make the method of the first scope of the patent, which includes a glUe layer formation step before the formation of the Xi ® ^ Cheng Xi ^ layer. The first dielectric layer, the second dielectric layer and: Rong: on a conductor. Said Jiu Jiu's production method of the first case i ί ί i, encircling ί 2 items ′ Wherein when removing the picture and the animal layer, the point landing layer is also removed at the same time. 4. The production method of item 1 in the scope of patent application, straight in the report: with the same ^ ^ ^ ^ ^ t Another 3 has a bloc layer formation step, ^ blind layer in the patterned sacrifice Layer, $ -dielectric layer, the first dielectric layer, and the first conductors. The manufacturing method of step 4 of the method of item 4 in which the barrier layer is also removed when the patterned sacrificial layer is removed. ί. The method of making ΪΠΠΓΓ term ... The third dielectric upper surface is approximately tangent to the figure: υ dioxide layer, υ-oxide layer, and the upper surface of the saponification sacrificial layer. 7. For the production method of item 1 of the scope of the patent application, the method for removing the sacrificial layer in A is to remove the pattern in the ^ 纟 q sentence-seeking wet etching process. 8. If the method of applying for 7 items of patent scope, in which the pattern is removed 561131 六、申請專利範圍 化犧牲層之刖,另包含有一蝕刻步驟,用來於該第三介電 廣中#刻出複數個#刻窗(etch hole),以均勻並快速地 進行該濕#刻而去除該圖案化犧牲層。 9 ·如申請專利範圍第1項之製作方法,其中該第一介電 廣與δ亥第一介電層具有不同之折射率,且該第三介電層與 該第四介電層亦具有不同之折射率。 1 0.如申請專利範圍第1項之製作方法,其中該第一導體 與該第一導體包含有金(gold, Au)、鎢(tungsten, W)、 銅(copper,Cu)、鋁(aluminum, A1)、鋁銅合金(A1 -Cu al l〇y)、多晶矽或其他導電材質。 1 1 ·如申請專利範圍第1項之製作方法,其中形成該圖案 化犧牲層的材料包含有鎢(tungsten,W)金屬、氮化>5夕、 二氧化石夕、有機聚合物或多孔石夕(p0rous silicon)。 1 2 ·如申請專利範圍第1項之製作方法,其中該頂蓋層係 為一氧化層。 1 3 ·如申請專利範圍第1項之製作方法,其中形成於該第 四’丨電層令之該等開口係為複數個具有等間距、等寬度以 及等深度之開口。561131 6. The scope of the patent application for the sacrifice layer includes an etching step for #etching a plurality of #etch holes in the third dielectric film to uniformly and quickly perform the wet # The patterned sacrificial layer is removed by etching. 9 · The manufacturing method of item 1 in the scope of patent application, wherein the first dielectric layer and the first dielectric layer have a different refractive index, and the third dielectric layer and the fourth dielectric layer also have Different refractive indices. 10. The manufacturing method according to item 1 of the scope of patent application, wherein the first conductor and the first conductor include gold (Au), tungsten (Tungsten, W), copper (Cu), and aluminum (aluminum). , A1), aluminum-copper alloy (A1-Cu al l0y), polycrystalline silicon or other conductive materials. 1 1 · The manufacturing method according to item 1 of the scope of patent application, wherein the material for forming the patterned sacrificial layer includes tungsten (tungsten, W) metal, nitridation> oxidized silica, organic polymer, or porous Shi Xi (p0rous silicon). 1 2 · The manufacturing method according to item 1 of the scope of patent application, wherein the capping layer is an oxide layer. 1 3 · The manufacturing method of item 1 in the scope of the patent application, wherein the openings formed in the fourth layer are a plurality of openings having an equal pitch, an equal width, and an equal depth. 第19頁 561131 六、申請專利範圍 14· 一種懸臂樑(cantiiever beam)式微機電系統 (Micro-Electromechanical System, MEMS)的製作方法’ 該製作方法包含有下列步驟: 提供一半導體基底,該半導體基底表面包含有一重摻 雜層以及一第一介電層; 於該第一介電層中形成至少二通達該重掺雜層表面之 第一電極(electrode); 於緣等第一電極間之該第一介電層中形成一光波導 (waveguide)線,且該光波導線不接觸該重摻雜層表面; 於該半導體基底上形成一圖案化犧牲層,並覆蓋於該 光波導線、該第一介電層以及各該第一電極之上; 於該半導體基底上形成一臂狀物(arm)層,並覆蓋該 圖案化犧牲層; ^ 於該臂狀物層中形成至少二未通達該圖案化犧牲層 面之第二電極,且各該第二電極係分別位於該光波二 侧之該等第一電極的上方; 守線兩 於該臂狀物層中形成一第二介電層,且該第二介 不接觸該圖案化犧牲層表面; 層 蝕刻該第二介電層,以於該第二介電層中形成— (optical grating); 冊 於該半導體基底上形成一頂蓋(cap)層,並覆蓋各兮 第二電極、該第二介電層以及該光柵;以及 μ 餘刻該圖案化犧牲層,以於該臂狀物層下方形成一 穴(cavity)。 —孔Page 19 561131 VI. Scope of patent application 14. A method for fabricating a cantilever beam (Micro-Electromechanical System, MEMS) 'The method includes the following steps: Provide a semiconductor substrate, and the surface of the semiconductor substrate It includes a heavily doped layer and a first dielectric layer; forming at least two first electrodes in the first dielectric layer that reach the surface of the heavily doped layer; the first electrodes between edges and the first electrodes; An optical waveguide line is formed in a dielectric layer, and the optical waveguide line does not contact the surface of the heavily doped layer. A patterned sacrificial layer is formed on the semiconductor substrate and covers the optical waveguide line and the first dielectric layer. An electrical layer and each of the first electrodes; forming an arm layer on the semiconductor substrate and covering the patterned sacrificial layer; forming at least two unpatterned patterned layers in the arm layer Sacrificial layer second electrodes, and each of the second electrodes is respectively located above the first electrodes on the two sides of the light wave; the line-guard two forms a second dielectric in the arm layer And the second dielectric does not contact the surface of the patterned sacrificial layer; the second dielectric layer is etched to form an optical grating in the second dielectric layer; a cover is formed on the semiconductor substrate (Cap) layer, and covering the second electrodes, the second dielectric layer, and the grating; and μ, the patterned sacrificial layer is etched to form a cavity under the arm layer. -hole 561131 六、申請專利範圍 1 5·如申請專利範圍第1 4項之製作方法,其中於 案化犧牲層之前另包含有一黏著(glue)層形成步 成該黏著層於該第一介電層、該光波導線以及該 極之上。 形成該圖 驟,以形 等第一電 1 6 ·如申請專利範圍第1 5項之製作方法,其中於 案化犧牲層時,亦同時去除該黏著層。 1 7 ·如申請專利範圍第1 4項之製作方法,其中於 案化犧牲層之後另包含有一阻擋(bl〇ck)層形成^ 形成該阻擋層於該圖案化犧牲層、該第一介電層 導線以及該等第一電極之上。 1 8·如申請專利範圍第1 7項之製作方法,其中於 案化犧牲層時,亦同時去除該阻擋層。 1 9 ·如申請專利範圍第1 4項之製作方法,其中該 =含有二固定柱(anchor)層與—氧化層,又苴° 層之上表面約略與該圖案化犧牲 〃 化層係覆蓋於該圖案化犧牲層與該固定 20·如申請專利範圍第14項之製 線、該臂狀物層以及該頂蓋層 ^法,其中該 -係為由氧化物所 去除該圖 形成該圖 卜驟,以 、該光波 去除該圖 臂狀物係 該固定柱 齊,該氧 光波導構成。 561131 六、申請專利範圍 2 1 · f申請專利範圍第1 4項之製作方法,其中該第一介電 層與该光波導線具有不同之折射率,且該臂狀物層與該第 二介電層亦具有不同之折射率。 2 2二如申請專利範圍第丨4項之製作方法,其中該第一電極 與該第二電極包含有金(g〇ld,AU)、鎢(tungsten,w)、 銅〈copper, Cu)、紹(aiuminum,Ai)、銘銅合金(Al-Cu a 1 1 oy )、多晶矽或其他導電材質。 ϋ ί I ί專利範圍第1 4項之製作方法,其中形成該圖案 的材料包含有鎢(tungsten,W)金屬、氮化矽、 一乳石、有機聚合物或多孔矽(porous Si i lc〇n)。 含口 包開 栅等 光該 該且 1^— , 其口 ,開 法之 方度 作深 製等 之及。 ㈣以觸 14度接 第寬相 圍等層 範、牲 利距犧 專間化 請等案 申個圖 如數該 •複與 4 2有不561131 VI. Application scope of patent 15. The manufacturing method of item 14 of the scope of patent application, wherein before the sacrifice layer is applied, a glue layer is formed to form the glue layer on the first dielectric layer, The optical waveguide line and above the pole. This step is formed to shape the first electrical 16. The manufacturing method of item 15 in the scope of patent application, wherein the adhesive layer is also removed when the sacrificial layer is applied. 1 7 · The manufacturing method according to item 14 of the scope of patent application, further comprising forming a blocking layer after the sacrificial layer is formed ^ forming the blocking layer on the patterned sacrificial layer, the first dielectric Layer wires and the first electrodes. 18 · The method for manufacturing item 17 in the scope of patent application, wherein the barrier layer is also removed when the sacrificial layer is applied. 19 · The production method according to item 14 of the scope of patent application, wherein the = contains two anchor layers and an oxide layer, and the upper surface of the 苴 ° layer is approximately covered with the patterned sacrificial tritium layer. The patterned sacrificial layer and the fixing method, such as the line 14 of the patent application scope, the arm layer, and the capping layer method, wherein the-is formed by removing the figure by the oxide to form the figure In this step, the arms are aligned with the fixed column by the light wave, and the oxygen optical waveguide is formed. 561131 VI. Application method for patent application range 2 1 · f Patent application range item 14 Production method, wherein the first dielectric layer and the optical waveguide have different refractive indices, and the arm layer and the second dielectric The layers also have different refractive indices. The manufacturing method of item 4 in the scope of the patent application, wherein the first electrode and the second electrode include gold (AU), tungsten (tungsten, w), copper (copper, Cu), Shao (aiuminum, Ai), Ming copper alloy (Al-Cu a 1 1 oy), polycrystalline silicon or other conductive materials. ϋ I ί The manufacturing method of item 14 in the patent scope, wherein the material forming the pattern includes tungsten (tungsten, W) metal, silicon nitride, a lactite, organic polymer, or porous Si i lc. n). Including the mouth, opening the grid, etc. The light should be 1 ^ —, the mouth, the opening method should be the sum of the deep system. To touch the 14th level and the wide range, the distance between the sacrifice and the sacrifice of specialization, please wait for the case to apply for a picture. 第22頁 561131 六、申請專利範圍 地蝕刻該圖案化犧牲層。 liEHil 第23頁Page 22 561131 VI. Patent application scope The patterned sacrificial layer is etched. liEHil Page 23
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US11287320B2 (en) 2017-05-23 2022-03-29 Hamamatsu Photonics K.K. Filter controlling expression derivation method, light measurement system, control method for Fabry-Perot interference filter, and filter control program

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11287320B2 (en) 2017-05-23 2022-03-29 Hamamatsu Photonics K.K. Filter controlling expression derivation method, light measurement system, control method for Fabry-Perot interference filter, and filter control program
TWI788353B (en) * 2017-05-23 2023-01-01 日商濱松赫德尼古斯股份有限公司 Derivation method of optical filter control equation, optical measurement system, control method of Fabry-Pereaux interference filter, and optical filter control program

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