TW560016B - One-time formation of flip-chip type ball grid array semiconductor package and its manufacturing method - Google Patents

Abstract

A kind of one-time formed flip-chip type ball grid array semiconductor package and its manufacturing method are disclosed in the present invention. Through the surface tension of soldering paste, the soldering paste of solder ball array is filled into the conduction holes of the substrate via the substrate surfaces, so as to complete flip-chip attachment and soldering ball array package in one time. Thus, the manufacturing steps can be effectively saved. Therefore, the flip-chip package can be completed without requiring the actions of forming bumps and underfill on the chip and substrate surface when generating flip-chip attachment. In addition, by using the surface tension of the soldering paste itself for the soldering ball array, the amount of soldering paste filled into the conducting holes of substrate can be controlled. The invention is used to simplify the processes of flip-chip attachment and soldering ball array package such that it is capable of relatively decreasing the factors influencing the manufacturing process and making the manufacturing process more stable for reducing the packaging cost.

Description

560016 V. Description of the invention (1) [Application of the invention The invention is a method, especially the assembly and its manufacturer [Background of the invention Today semiconductors are light, thin, short, semiconductor component structure reliability, density, packaging and recent years A variety of new chip-on-chip direct-current wafer (DCA) technologies have been introduced. Among them, the chip-on-solder ba (lead frame) technology can reduce the size of small-chip packages after packaging. This technology is in line with small-scale development. , Point. Because of the semiconducting range] A flip-chip brake-array semiconductor structure and its manufacturing method are a one-shot flip-chip brake-array semiconductor structure. ] The structure of body components is accompanied by the development trend of electronic products toward small, high-speed and high-functionality, which makes the technology of packaging continue to break through innovation. As the requirements for increasing components and reducing component sizes continue to increase, the conditions for bonding technology are becoming more stringent. Traditional wireb ο nding technology gradually develops bonding technology, such as flip-chip bonding technology (f 1 ip-chip) or flip-chip direct chip attachment, which is used in volume for integrated circuit chip packaging. The technology of forming a solder ball array (array 1 1) on the surface of the wafer is used to replace the lead frame used in conventional packaging, and the wafer directly contacts and is bonded to the substrate in a reversed manner, and the electronic signal transmission distance between the wafer and the substrate is reduced. The size of the chip makes the size of the chip package similar before and after. In the future, high-frequency noise is easy to control, multi-functional, high-density and trend. In terms of the electrical connection of the substrate, the ball-ball array (ba 1 1 BGA) structure has replaced the traditional The structure of the pins to form the fulcrum and the welded component becomes increasingly finer and more complex. Therefore, the semiconductor

IIIIill Page 4 560016 V. Description of the invention (2) " "-The body component has been installed from the original bilateral pins to the four sides. However, when the number of pins on the I edge is too high, the pin pitch becomes very high, which causes a problem of low yield during the process of bonding the circuit board. Therefore, the brake ball array (ba 1 1 gr 丨 darray, BGA) construction method changes the packaging method of the substrate by using pins to form fulcrum and solder joints. An array of solder balls is arranged on the bottom area of the substrate instead of the traditional pins, so that the pitch of the foot is changed by 〇 · 5 _ expands to 丨 · 5 and yield rate is improved as a result. In addition, the flip-chip bonding technology and the solder ball array packaging method can be combined to develop a flip-chip bonding (F 1 i p C h i p) solder ball array assembly (B G A) technology. This combined technology also has the characteristics of good frequency response, less interference of signals in the chip, and better electrical performance than other packaging methods. At the same time, the process of applying flip-chip bonding (F 1 i p C h i p) and solder ball array assembly (B g A) technology ’includes two parts: flip-chip technology and B G A assembly. First of all, in terms of flip chip technology, the bumps and ball structures to be joined are first made at the positions set on the substrate and the wafer surface, and then the wafer is placed at the preset position of the US board to be soldered and the bottom is filled with glue (Underfi 1 1) Fill in the sealing material. Among them, the bumps and the ball structure can be generated by evaporation method. During the vapor deposition, the metal vapor passes through the mesh cover (ma sk) to generate the bump pattern at the desired position of the wafer or the substrate. In addition, in the BGA structure assembly, it is necessary to additionally make a brake ball array at a predetermined position of the substrate to achieve the electrical connection of the substrate; the BGA structure assembly process often uses electroplating or solder ball printing technology to generate a large number of question balls Array. Although the application of flip-chip bonding and solder ball array assembly technology has its advantages, it is necessary to separate the two parts when combining flip-chip technology and BGA assembly.

III

m II

ill · Page 5 560016 V. Description of the invention (3) Fabrication of bump and brake ball structure, and then joint through various heat treatment procedures. Therefore, the manufacturing process is quite complicated, which leads to many factors affecting the process and causes the process to be unstable; it also relatively increases the packaging cost due to the increase in the number of process steps. [Objective and Summary of the Invention]

In order to solve the problems of the above-mentioned conventional technology, the present invention provides a flip-chip gate array semiconductor structure and its manufacturing method, which can simplify the process of flip-chip bonding and solder ball array assembly technology, and can relatively reduce the impact process. Factors and reduce packaging costs. Compared with the general process of forming bumps and gate ball structures on both sides of the wafer and the substrate, respectively, the once-molded flip-chip gate ball array semiconductor structure and manufacturing method of the present invention can save about bumping. ), Flip-chip bonding and under-filling (under fi 1 1) more than 20 process steps °

The once-molded flip-chip gate ball array semiconductor structure disclosed by the present invention and the manufacturing method thereof use the surface tension of the solder paste to fill the solder of the solder ball array into the via holes of the substrate through the wires on the surface of the substrate. Crystal bonding and solder ball array assembly are completed at one time; process steps can be effectively saved. When flip-chip bonding occurs, the flip-chip package is completed without the need to form bumping and underfill operations on the wafer and substrate. And the surface tension of the solder paste of the solder ball array can be used to control the amount of solder paste filled in the substrate via hole. At the same time, the present invention uses the substrate vias filled with solder paste to conduct the upper and lower circuits of the substrate; therefore, it has the characteristics of being capable of stacking multiple layers of substrates. The once-formed flip-chip gate ball array semiconductor structure disclosed in the present invention includes: a substrate having a plurality of via holes filled with solder paste

560016 5. Description of the invention (4) and a plurality of solder balls, each of which is filled with solder paste, is connected to one of the plurality of solder balls; and more than one chip is conducted through a plurality of paths, and more than ^ A proper pitch of the wafer. Fill in the lead of the tin and use a plurality of inter-via holes each with more than one wafer through hole and the substrate spacer element and the base. One of them can be used to form an electrical board to form a plurality of via holes connected to the chip. It uses a plurality of solder balls of a plurality of crystal plates to melt and shape a plurality of conductive pieces to complete a substrate to a suitable wafer. In addition, it is mounted on its manufacturing surface, the lead solder paste is introduced into the conductive holes, and the conductive holes are formed. The preferred method further includes a method, and the method of the present invention for temperature reflow soldering when the plurality of vias of the plurality of interlayers are formed into a plurality of holes. The method of the present invention refers to the size of a plurality of solder paste balls in advance and an example to explain one of the above steps. Several steps of solder ball and solder ball spacer elements; and a step of solder paste and solder ball wafers. Sub-forming includes: each of which is aligned with the substrate and the base thermal substrate to reach along the tin substrate, and further includes a flip-chip gate array semiconductor: providing a substrate having a plurality of vias each having One by one; provide more than one crystal isolation _ proper distance, the board reaches the electrical connection to an appropriate temperature, so that a plurality of paste balls of the vias are connected into a circuit, and at the same time a plurality of alignment base lines are filled into the contact To more than one crystal, the force σ heats more than one to conduct. Among them, a plurality of surface vias are used. The shape can be multiple shaped flip-chip solder balls. You can use solder paste on the printed cloth to fill the volume of the solder balls through the solder paste to make the substrate and a gate ball array half-brush coating. Surface tension control of the tin of the hole. The amount of paste formed by the conductor on the substrate

1_SI: Page 7 560016

Fifth, the description of the invention (5) root body structured solder paste, the second completion factor between the substrates in the reflow hot-melt melting substrates: according to the present invention and its system and the flip-chip connection on the surface formed on the substrate surface; It can reduce the solder paste of the substrate pre-surface of the method disclosed in detail. The wire packing structure can be effectively packaged into the substrate once exposed by the method of the invention. of. In this way, the purpose of saving process costs is clear. When the flip chip of the present invention is formed at the junction of the substrate surface, the via on the surface of the substrate surface paste itself opens the vias; at the same time, the flip chip bonding and tin steps are achieved; The flip-chip embodiment of the present invention is matched with a layer of through holes in the semi-conductive wire of the brake ball array. Then, the brake ball array is affected by the force, and a semi-conductive map of the brake ball array is formed along the formation substrate and the crystal ball array with a small influence on the process. The first figure is not shown. The first figure is an embodiment of the present invention. A top view of a once-formed flip-chip gate array semiconductor structure, the structure of which includes: 56 (28X2) vias filled with solder paste 3 and 56 (28 2) solder balls 丨 丨The substrate 10 and the mother vias 13 each have a lead 12 connected to a solder ball 1 1 ′ and a wafer 20 ′. The wafer is electrically connected to the substrate 10 through the vias 13 filled with solder paste. It is isolated from the substrate by a plurality of spacer elements (not shown). It can be seen from FIG. 2 that the via holes filled with the solder paste 3 are connected to a solder ball 1 with a wire 丨 2 in a group of 7 and the direct control of the solder ball 1 2 6 0 Micrometer (Vm, micrometer), and the length of individual wires 12 varies slightly due to the different distance between each via 13 and the solder ball 1 1, where the maximum wire length is about 380 microns (vm, micrometer ). The invention further comprises a flip-chip gate ball array semiconductor structure formed at one time.

Page 8560016 V. Description of the invention (6) The steps include providing a substrate with a plurality of = a plurality of solder balls: a plurality of vias are connected to the 1 'female one by one of a plurality of wire connections. The plurality of vias are composed of a plurality of wires, which are connected to one of the plurality of solder balls; a chip is provided, and the beans are formed by: = spacer: a distance between the substrate and the substrate, and the chip is scheduled A plurality of vias are aligned with the base substrate at a position of ί: ίί; finally, the two solder balls are formed into a molten solder paste and a plurality of via holes are formed to form a plurality of tins. = 禝 Several tin τ balls make the chip and substrate achieve circuit conduction. -浐 ϋ'Γ illustrates the present invention, please refer to FIG. 3; FIG. 3 is the present invention; a cross-section of a flip-chip gate array semiconductor structure formed by a man-made shape " not shown in the figure, its wafer 2 0 is a plurality of spacer elements 2 1 US = formation-a proper distance ^ invention is a material of the tin material itself ^ plane: λ two: Ϊ 1: the surface of the ball 11 melts to form a solder paste along the wire 12 to achieve circuit conduction . The tin τ of the guide 13 is also shaped by the surface tension of tin twilight itself. In this way, the lunar bonding was completed at the same time back to Tan. In order to make the solder ball array of the substrate and the gate cover ^: it! 2 cases are to form a plurality of solder balls by printing Γ1 ::: ί: ϊΓ before the surface is covered with solder paste, so that the solder balls can be melted into ^ The tin through hole; the quality of the t wire q is copper & is a metal material of Shao. In addition, the size and shape of the plurality of via holes and the plurality of solder ball seeking factors are controlled by the two small shapes and shapes of the plurality of via holes of the plurality of via holes after the heat treatment. Imi Page 9 560016 V. Description of the invention (7) The above are only the preferred embodiments of the present invention, and are not used to limit the scope of the invention; Equal changes and modifications are all covered by the patent scope of the present invention.

Page 560016 Brief Description of Drawings Figure 1 is a top view of the semiconductor structure of a flip-chip brake ball array formed in one embodiment of the present invention; Figure 2 is a flip-chip brake ball formed in one embodiment of the present invention An enlarged view of a part of the array semiconductor structure; and FIG. 3 is a cross-sectional view of a flip-chip gate ball array semiconductor structure formed in one embodiment according to the present invention. [Illustration of Symbols] 10 substrate 11 solder ball 12 wire 13 via 13 chip 21 spacer

Page 11

Claims (1)

560016 A substrate having a plurality of wires, a plurality of filled vias, and a plurality of solder balls. The plurality of vias filled with solder paste are connected to the plurality of solder balls by the plurality of wires. Xidao, S 丨 Total, > the mother-the plurality of V through holes filled into the tin moon is made of one of the plurality of wires among the tin balls; and connected to the plurality of one or more crystal moons, The ^ a / fg | I; / I- ΛΑ η 埴 Λ level * +, the previous Japanese and Japanese films are used to achieve circuit conduction with the substrate through the plurality of vias into the tin τ. According to one of the Gorilla Semiconductor structures described in item 1 of the scope of the patent application, the one or more wafers: a polycrystalline brake ball array isolation A 4c: 0 / «χ A proper distance is formed from the substrate. For example, the first quantity in the scope of the patent application is the volume of the solder paste of the conductive t of the conductive tin T inserted into the solder paste. /, The size of the v through hole into the tin H, the plurality of solder balls 4. As described in item 1 of the scope of the patent application, a series of semiconductor structures with a Λ shape of a plurality of lead wires forming a flip-chip 1 ball drop T, In order to facilitate the introduction of the solder material into the guide 2 on the surface cloth, the tin is a ν through hole as described in the first item of the patent application scope. Is one of the materials. The material of "1" is copper and aluminum gold. As described in item 丨 of the patent application, the semiconductor structure is a series of flip-chip interstitial arrays. Lai is formed by printing. 560016 7. A fabrication and main method of a flip chip semiconductor ball array semiconductor fabrication method, the steps include: i, a plurality of wires and a plurality of wires connected to a substrate provided by the plurality of guides, which has a plurality of Vias, a plurality of solder balls, the plurality of vias are connected to one of the plurality of solder balls by one of the plurality of the plurality of solder balls' each of the plurality of via holes line _ provide more than one The number of wafers M .1 ..., fci &J; J cq μ., The plurality of which are intended to be electrically connected to the substrate are aligned with the plurality of the substrate = through holes; and I heat the substrate at a suitable temperature, so that the plurality of Solder balls are melted and depleted, and the plurality of vias are filled along the plurality of wires ^ / f, the plurality of solder pastes are passed through the plurality of solder paste balls, and the circuit board is electrically connected to the substrate with the solder paste . As mentioned, the manufacturing method of the secondary-molded cover shaft 歹 J + V body structure I, the-more than one spacer element is formed to isolate the substrate-the proper pitch.糸 Complex number sequence t ^ ϋ:: ί The 7th method of manufacturing a flip-chip brake ball array + ¥ structure I, wherein the step of adding the substrate is to simultaneously make the substrate and the one The above wafer ο. The method for manufacturing a flip-chip gate array of the sub-shape described in item 7 above, wherein the size of the plurality of vias and the size of the complex i are filled with the plurality of vias. The volume of Λ solder balls and the number of spacer elements, 560016 6. Scope of patent application Height control. 11. The manufacturing method of the flip-chip brake ball array semiconductor structure as described in item 7 of the patent application scope, wherein the plurality of solder balls are formed by printing. 1 2. A manufacturing method of a flip-chip gate ball array semiconductor structure as described in item 7 of the scope of the patent application, wherein the plurality of wires are coated with solder paste on the surface in advance to facilitate the plurality of solder balls The solder paste formed by melting is introduced into the plurality of via holes. 1 3. The manufacturing method of the flip-chip gate array semiconductor structure as described in item 7 of the scope of the patent application, wherein the material of the plurality of wires is one of copper and aluminum metal materials. Page 14