TW559952B - Multi-thickness silicide device - Google Patents

Abstract

A transistor device (10) formed on a semiconductor substrate (12) with an active layer (13) disposed on the semiconductor substrate having active regions (18) defined by isolation trenches (16). The device includes a gate (36) defining a channel (20) interposed between a source and a drain (22) formed within the active region of the substrate. Further, the device includes a multi-thickness silicide layer (42 and 44) formed on the main source and drain regions (24 and 26) and source and drain extension regions (28 and 30) wherein a portion (54) of the multi-thickness silicide layer which is formed on the source and drain extension regions is thinner than a portion (46) of the silicide layer which is formed on the main source and drain regions. The device further includes a second thin silicide layer formed on a polysilicon electrode of the gate. Further still, the device includes a disposable spacer used in the formation of the device. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a plurality of spacers used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

Description

559952 V. Description of the invention (1) --- I-[Field of invention] Θ The present invention relates to the manufacture of semiconductor devices, especially to devices containing multiple thicknesses of shixi metal, multilayer silicide metal, and multiple thickness multilayer silicide metal Manufacturing. [Background of the Invention] Integrated circuit devices such as electrically erasable and programmable read-only memories (EEPROMs), transistors, diodes, gate fluids, and similar devices are usually manufactured on a half-body base, such as Silicon. Even when this type of semiconductor substrate is doped, the resistance is still higher than that of most metal-containing materials. Resistive contacts and interconnect structures are undesirable for circuits because the resistance limits the maximum current flow and can generate heat and Can lead to reduced circuit accuracy, consistency, and performance. Therefore, for example, a metal oxide semiconductor (MOS) transistor device typically uses petrified metal or self-aligned silicide layers over the source, drain, and gate regions to reduce contact resistance. However, such transistors with silicided metal layers or self-aligned debris layers still tend to have high contact resistance. In addition to the aforementioned disadvantages, transistors made on the silicon (si 1 icon-on insulator (SOI) structure) have a so-called floating body effect (FBE), which is the body area Because the body area is electrically isolated from the substrate instead of the desired change, the floating body effect causes several undesired characteristics. For example, FBE causes a sharp increase in the relationship between the drain current and the drain voltage (the "tangled effect" ( kinkeffect)), abnormal subcritical current, transient current overshoot, and early breakdown of the device voltage VDS. The tangled effect can lead to a reduction in device gain, which is undesirable when used in analog applications, while the floating body effect is still the oxidation of silicon metal on the insulating layer

92072.ptd Page 7 559952 V. Description of the invention (2) The main obstacles to the acceptable operation of the semiconductor field effect transistor (SOI MOSFET). U.S. Patent No. 5,3 5 2,6 3 1 proposes the disadvantages of the contact resistance discussed above. In particular, U.S. Patent No. 5,3 5 2,6 3 1 describes the formation of a type of silicide metal over the gate. Over the electrode region and another type of silicide metal over the source and drain region, however, it is not suggested how to overcome the lightly doped drain and source region (also referred to as source and drain here) (Extended pole region) related resistance problems, and furthermore, it is not suggested how to overcome the disadvantages caused by the floating body effect. In U.S. Patent No. 5,9 6 5,9 1 7, a proposal to overcome the disadvantages caused by the floating body effect includes a metal connector (electrical contact) that directly contacts the top silicidation. The disclosed region overcomes some disadvantages caused by the floating body effect, such as, because the electrical contacts are directly coupled to the body region, the metal region, one side of the first doped region, and one side of the body region. The voltage applied to the electrical contact is set to the voltage of the body region. However, it is not suggested how to overcome the resistance in the lightly doped drain and source extension regions. Therefore, in this technique, it is necessary to adjust different regions such as the polycrystalline region of the source and drain regions, the junction region of the source and drain regions, and the source and drain extension regions. There is a need for resistive electrical devices. Furthermore, in this technique, electrical devices that are used in addition to providing adjusted resistance can also reduce the floating body effect caused by the association of the silicon-on-insulator (SO I) structure with these devices. There is demand. [Invention of disclosure]

92072.ptd Page 8 559952 V. Description of the invention (3) According to one aspect of the present invention, the present invention is a transistor device formed on a semiconductor substrate having a working area defined by an isolation trench. The device includes a gate defining a channel which is interposed between a source and a drain formed in an active region of the semiconductor substrate, and the source and the drain include the same source and drain extension regions as the source and the drain. The main source and drain regions. Furthermore, the device includes multiple thickness silicided metal layers formed on the main source and drain regions and the source and drain extension regions. In addition, a portion of the multiple-thickness petrified metal layer formed on the source and non-electrode extension regions is thinner than a portion of the multiple-thickness silicided metal layer formed on the main source and drain regions. According to an aspect of the present invention, the present invention is a transistor device formed on a semiconductor substrate having an active area defined by an isolation trench. The device includes a gate defining a channel, and the channel is inserted into the semiconductor substrate. Between the source and the drain formed in the active region. Furthermore, the device includes a plurality of thin silicided metal layers formed on the source and the drain. In addition, at least the plurality of thin silicided metal layers extend above the lower silicided metal layer. The device also includes most of the disposable spacers used to form the device. According to an aspect of the present invention, the present invention is a transistor device formed on a semiconductor substrate having an active area defined by an isolation trench. The device includes a gate defining a channel, and the channel is inserted into the semiconductor substrate. Between the source and the drain formed in the active region. Furthermore, the device includes a plurality of thin silicided metal layers formed on the source and drain electrodes. In addition, at least the plurality of thin silicided metal layers extend above the lower silicided metal layers

92072.ptd Page 9 559952 V. Description of the Invention (4) Layer. The device also includes a disposable spacer to form the device. According to another aspect of the present invention, the plurality of spacers are permanent spacers formed in a subsequent step in the formation process of the device. According to another aspect of the present invention, the first intermediate spacer is formed from the disposable spacer to control the formation of the source electrode and the electrode electrode and the multiple-thickness petrified metal layer. According to another aspect of the present invention, the multiple-thickness silicided metal layer includes at least two different types of silicided metal layers. According to another aspect of the present invention, the semiconductor substrate is a semiconductor-on-insulator (SOI) substrate, and the semiconductor substrate on the insulator has an embedded oxide interposed between the active layer and the main semiconductor substrate ( buried oxide (BOX) layer, wherein the BOX layer defines the active area. According to another aspect of the present invention, the semiconductor substrate is a germanium-on-insulator (G0I) substrate on an insulator. According to another aspect of the present invention, the present invention is a method of manufacturing a transistor device. The device is formed on a semiconductor substrate having an active region defined by an isolation trench. The method includes a step of forming a gate defining a channel interposed between a source and a drain formed in an active region of the semiconductor substrate. Furthermore, the method includes forming multiple thickness silicided metal layers on the main source and drain and the source and drain extension regions. In addition, the portions of the multiple-thickness silicide metal layer formed on the source and drain extension regions are ratios of the multiple-thickness silicide metal layers formed on the main source and drain regions.

559952 V. Description of the invention (5) According to another aspect of the present invention, the present invention is a method for manufacturing a transistor device, which is formed on a semiconductor substrate having an active area defined by an isolation trench. The method includes a step of forming a gate defining a channel interposed between a source and a drain formed in an active region of the semiconductor substrate. Furthermore, the method includes forming a plurality of thin silicided metal layers on the source and the drain. In addition, the method includes the step of forming a plurality of first spacers on the gate sidewall. In addition, the method includes the step of forming a plurality of second spacers on the plurality of first spacers. In addition, at least a plurality of thin silicided metal layers extend above the lower silicided metal layer. According to another aspect of the present invention, the present invention is a method for manufacturing a transistor device, which is formed on a semiconductor substrate having an active region defined by an isolation trench. The method includes a step of forming a gate defining a channel interposed between a source and a drain formed in an active region of the semiconductor substrate. Furthermore, the method includes forming a plurality of thin silicided metal layers on the source and the drain. In addition, the method includes the step of forming a disposable spacer on the gate sidewall. In addition, at least a plurality of thin silicided metal layers extend above the lower silicided metal layer. According to another aspect of the present invention, the method includes an additional step of selectively etching the disposable spacer at a level to adjust the formation of multiple thickness silicided metal layers. According to another aspect of the present invention, the semiconductor substrate is a semiconductor-on-insulator (SOI) substrate with an embedded oxide (Box) layer, the embedded oxide layer is interposed between the active layer and the main semiconductor substrate , Where the role

92072.ptd Page 11 559952 V. Description of the Invention (6) The area is defined by the embedded oxide layer. [Explanation of the preferred embodiment] In the detailed description, the same components are marked with the same component symbols. In order to illustrate the present invention in a clear and concise manner, the drawings are not necessarily drawn to scale and certain features are shown in some schematic ways. . An SO I transistor device including multiple thickness silicided metal layers according to the present invention will now be described. The device includes a gate defining a boundary channel which is interposed between the source and the drain and is disposed in one of the active areas of the SO I structure. Furthermore, the device includes multiple thickness silicided metal layers formed on the main source and drain regions and the source and drain extension regions, which will be described in detail later. In addition, portions of the multiple-thickness silicide metal layer formed on the source and drain extension regions are thinner than portions of the multiple-thickness silicide metal layer formed on the main source and drain regions. The device may include a silicided metal layer formed on the polycrystalline silicon electrode of the gate, and the multiple-thickness silicided metal layer includes at least two different kinds of shattered metal layers. An SOI transistor device including multiple thickness silicided metal layers obtains a semiconductor-on-insulator (SOI) transistor device with a significantly lower contact resistance in the main source / drain region than a conventional transistor device. In addition, a semiconductor-on-insulator (SO I) transistor device including multiple thicknesses of a silicided metal layer and a silicided metal layer on a polycrystalline silicon gate helps reduce AC effects. Furthermore, the extremely thin silicided metal layer formed on the source / drain extension region helps to reduce the floating body effect of the semiconductor (SO I) structure on the insulator. First referring to FIG. 1, the SO I transistor device of the present invention is marked as an element symbol. The SOI transistor device 10 is a semiconductor-on-insulator (SOI) device.

92072.ptd Page 12 559952 V. Description of the invention (7) In the structure, the semiconductor structure on the insulator has a semiconductor substrate 12, an embedded oxide (BOX) layer 14 formed on the semiconductor substrate 12, and the embedded structure. Semiconductor layer 13 on the oxide layer 14. Within the semiconductor layer 13, a shallow trench isolation (STI) region 16 is defined as a semiconductor active region 18 shown in FIG. In a specific embodiment, as shown in FIG. 1, the active region 18 has a p-type region, or a channel 20, and two N + (source and drain) regions 22, and the channel 20 is plugged. It is placed between the source and drain regions 22. Obviously, it can also be inserted into two P + intervals with η-type channels. The source and drain regions 22 include individual deep implant regions 24 and 26, and individual extension regions 28 and 30. The gate dielectric 32 is interposed between the lower surface 34 of the gate 36 and the upper surface 38 of the SOI semiconductor substrate 40. The gate dielectric 32 shown in FIG. 1 is a single-layer dielectric, but the The gate dielectric may be a multilayer dielectric. The multiple-thickness silicide metal layers 42 and 44 are disposed on the two source and drain regions 22 and 22. The silicide metal regions 46 are formed on the polycrystalline silicon regions of the individual deep implant regions 24 and 26. The thin silicided metal regions 48 are formed above the individual deep implant junction regions 50 and 52, and the extremely thin silicided metal regions 54 are formed above the individual extension regions 28 and 30. The multiple-thickness silicided metal layers 42 and 44 may be made of a well-known petrified metal such as cobalt silicide (CoSi2), titanium silicide (TiSi2), nickel silicide (NiSi2), or the like. In a specific embodiment, the multiple-thickness silicide metal layers 42 and 44 are made of cobalt silicide. The silicided metal region 46 may have a thickness between 100 angstroms (A) and 300 angstroms, the silicided metal region 48 may have a thickness between 50 angstroms and 250 angstroms, and the ultra-thin silicided metal region 54 may have

92072.ptd Page 13 559952 V. Description of the invention (8) On the top of the thickness between 25 Angstroms and 100 Angstroms is a shattered metal layer 56, which is a silicided metal dance. It can be made of the same appropriate magical metal material, the silicide: 56 56 also :; gold made of the same material as the shredded metal layers 42, 44; layer ττ; made of Xihua metal material The exemplary cocoa is an exemplary cocoa having a thickness between 100 angstroms and 200 angstroms. The metal layer 56 is: the active region 18, the channel 20, the source and the drain? The nine inter-electrode dielectrics 32, the closed electrodes 36, the shredded metal layer 56, and multiple thicknesses: 2: 2, form a pseudoelectric crystal device of the present invention. In the following, "Huaijin I", "I" with multiple thicknesses of silicided metal layers on top of the gate device's source I > and the SOI above the pole region will be described. The two pieces 58 of the shape shown in FIG. 1 extend from the upper surface 38 of the SOI substrate 40 to the gate dielectric 32. Ϊ = Ϊ3, either side extends upwards. Although the spacer 58 is shown, it is necessary to understand that the spacer It is not necessary to form 58 multiple-thickness layers 42, 44, which will be described in detail later. It can be used to discontinue the semiconductor device 21 (the steps similar to the aforementioned semiconductor device method are outlined in Figure 7). ^ Explain the steps of the method 71 ° '2nd to 6th figure ^ ^ The solution of the method is the method 71 0 and the half-device 21G described below are for illustration purposes only, and many of the foregoing The method 710 and / or the structure of the semiconductor device 21 are different from each other as appropriate. The method is also used in step 712. The polycrystalline silicon electrode system is formed on the SCH substrate as

559952 V. Description of Invention (9)

This is an intermediate stage for manufacturing the SOI transistor device 210. As shown in FIG. 2 'The SOI transistor device 210 includes a semiconductor substrate 212, an embedded oxide layer 214 formed on the semiconductor substrate 212, and a semiconductor layer provided on the embedded oxide BOX layer 214. 213. The exemplary box layer may have a thickness between 1800 angstroms and 2200 angstroms, and the exemplary semiconductor layer 213 disposed on the bqx layer 214 may have a thickness between 800 angstroms and 100 angstroms. Appropriate semiconductor materials such as silicon, carbide, germanium, or similar materials can be used as the semiconductor layer 213 disposed on the BOX layer 214. Within the semiconductor layer 213 disposed on the BOX layer 214 is a shallow trench isolation (STI) region 216. The STI region together with the BOX layer 214 defines the location of the semiconductor active region for the next step. The ST I area 2 1 6 is electrically isolated by filling with an insulator, such as an individual electrical device of the SOI transistor device 210. Other isolation techniques known in the art can also be used to isolate the S0i transistor device 21. The gate dielectric 232 is interposed between the lower surface 234 of the gate electrode 236 and a part of the upper surface 238 of the SOI semiconductor substrate 240. The gate dielectric 232 shown in FIG. 2 is a single-layer dielectric, but the The gate dielectric may be a multilayer dielectric as described above. The gate dielectric 232 may be made of a suitable gate dielectric material, such as silicon dioxide (SiO2), silicon nitride

(Si3N4), alumina (Al2O3), oxide or similar materials. In the present embodiment, the gate dielectric 232 is made of silicon nitride, the dielectric nitride (Hf02) and silicon oxynitride (SiNO) of the silicon nitride. The mass dielectric layer 232 may have, for example, 13 angstroms to 16 Angstrom thickness. The gate electrode 236 may be made of a typical well-known conductive material such as polycrystalline silicon, and the gate electrode 2 36 may have a thickness of, for example, 800 to 1200 angstroms.

559952 V. Description of the invention (10) '------- In step 714, the source electrode and the non-polar region are formed. Before the source and drain regions are formed, the semiconductor layer 213 shown in Fig. 3 and Fig. 3 may be appropriately doped to form an electrically active material. The soil plate 240 is the largest &;: Use layer ,. For example, boron or indium can be implanted to form a 卩 -type region or channel as an n-type device, and phosphorus or arsenic can be implanted to form an n-type region or channel as a p-type device. It is understood that before the gate is formed, the semiconductor layer 213 can be appropriately doped. A more detailed description of the process of forming the source and drain regions 222 after the gate is formed is described later. In this embodiment, the channel region 220 inserted between the source and drain regions 222 under the gate dielectric 232 is p-type doped by the aforementioned alternative method before this step. A 'disposable spacer' can then be formed on the gate to protect the formation of the gate 236 and the next extension region 228, 230 from the main source and drain regions 224, 2 2 6 from contact with dopants. To form the disposable spacer, a spacer material such as an oxidizing material, such as silicon dioxide (SiO2), silicon nitride (Si3N4), or similar oxidizing material, is then deposited on the substrate 2 4 0 (not shown). On the top, the deposit forms an oxide layer over the top surface 238 of the SOI substrate 240. The oxidative deposit can be performed by, for example, plasma enhanced chemical vapor deposition (PECVD). The oxide is etched with a suitable etchant, and the oxide layer of the substrate is reduced in size, leaving an oxide spacer similar to the spacer 268 shown in FIG. 5, which can be removed from the semiconductor. Surface 238 of substrate 240 extends

92072.ptd Page 16 559952

Protect the extension material during miscellaneous periods. In addition, although the Yan V 1 Ϊ 二 2a is to be implanted to illustrate the use of an implant as an example, it should be understood that the field # 克 # 旦 人 β k uses a larger number of implants. Furthermore, the dental implant " a beta electrode 236 is patterned and / or the spacer 278 is formed and implanted in the shape of 'Ϊ ^ #. For example, an oblique extension implant (35 to 45 degrees) is implanted with a total of four kelvins—Q "1Λ13 injectants are implanted between 3 · 5χ1013 and 5χΐ〇ΐ3 atoms / cm2 Energy implantation of 30 to 80 kilo-electron volts or a. / Ί 二 ί, 'Semiconductor device 210 can be subjected to rapid heating at this time or later, annealing (RTA) unusual rapid heating and tempering. Can be A temperature of 1,02 0 to 1,0 50 ° C is performed for 5 to 15 seconds. Subsequently, in step 716, a metal layer 260 is formed on the source extension region, and the electrode extension region 2 2 8, 2 3 0, and above the main source and drain regions 2 2 4 and 22 6, the metal layer 260 is formed by one of sputtering, chemical conversion, or evaporation. The metal layer 26V Can be included; any metal such as platinum, titanium, button, nickel, cobalt, tungsten and / or similar metals. In a specific embodiment, cobalt is used to form the metal layer 26. The reason why cobalt is preferred is that the cobalt silicide has a dopant. Diffusion and segregation constants allow the formation of shallow conformal source and drain junctions, as shown in Figure 4. After the metal layer 26 has been deposited, the Thermal cycle, the heating cycle is used to make part of the metal layer 260 react, the metal layer 2 60 covers the source extension region & 8 and the ^ and electrode extension region 230 and the source and drain Area 2 to 22. If the metal layer 260 includes a semiconductor and the semiconductor layer 213 is silicon, cobalt and silicon react within the interface area to form cobalt silicide (CoSCo). It is determined as the type of metal used as Silicified metal from 200 t to 70 0 ° C / self-aligned petrified metal

92072.ptd Page 18 559952

The extremely thin portion of the silicided metal layer 264 covers the source extension region 228 and the drain extension region 230 forming the extremely thin silicided metal layer 254, covering the gap between the electrodes and the thin silicided metal layer 254. Pieces 2 6 8 are shown in Figure 4 ^ A. It should be understood that different metals can be formed on the silicided metal layer 264, and the method described above can be used to obtain a region with multiple thicknesses and multiple layers of silicided metal (not shown). In addition, it should be understood that metal layers 2 74 of the same or different metals may be formed on the silicided metal layer 266 at this time, and processed in a self-alignment method as described above to manufacture the petrified metal layer 276 (such (Shown in Figure 6). Then, in step 720, a second spacer 278 is formed to protect the portion of the petrified metal layer 272 over the junction of the main source and drain junctions 25 and the region 252. Next, the metal layer 280 is deposited and heated as described above to form a multi-thickness silicide metal layer 282 (shown in FIG. 1) of cobalt silicide on the source and drain regions 222. The spacers 268 and 278 covering portions of the extremely thin silicided metal layer 254 and the thin silicided metal layer 2 72 prevent deposition of the metal layer 280 on the source extension region 228 and the drain extension region protected by the cover. 230 thin silicided metal layers 254, 272. Covers 268 and 278 covering the gate and the thin silicided metal layers 264 and 272 are shown in Figs. 5 and 6, respectively. It should be understood that different metals can be formed to cover the silicided metal layer 2 72 and the silicided metal layer (not shown) having multiple thickness regions and multiple layers can be obtained as described above. In addition, it should be understood that the same or different metal layers 282 may be formed on the silicided metal layer 276 at this time and in the self-aligned direction as described above.

92072.ptd Page 20 559952 V. Description of the invention (15) Process to produce a silicided metal layer 56 (as shown in Figure 1). In this way, a device 21 with multiple thicknesses of petrified metal can be fabricated. Another embodiment of an SOI transistor device including a plurality of thicknesses of a silicide metal layer and a connection spacer will now be described in accordance with the present invention. The device includes a gate defining a channel interposed between a source and a drain, and is disposed in one of the active regions of the SOI structure. Furthermore, the device includes multiple thickness silicided metal layers formed on the main source and drain regions and the source and drain extension regions, which will be described in detail later. Moreover, the device also includes a plurality of spacers for forming the device, wherein a first spacer is formed on the side wall of the gate, and a first spacer is formed on the first spacer. If necessary, a third spacer or more spacers may be formed on the aforementioned spacer. In addition, portions of the multiple-thickness silicide metal layer formed on the source and drain extension regions are thinner than portions of multiple-thickness petrified metal layers formed on the main source and drain regions. The device may include another petrified metal layer formed on the crystalline silicon electrode of the gate. Moreover, the multiple-thickness silicide metal layer may include two plutonium layers of at least two different silicide metals. Referring to FIG. 8 first, the S0I transistor device of the present invention is marked as a component symbol 1 0. The S0I transistor device 10 ′ is formed in a semiconductor-on-insulator (SO I) structure having a semiconductor substrate 12 and an embedded oxide (β〇χ) formed on the semiconductor substrate 12. ) Layer 14 and a semiconductor layer 13 disposed on the embedded oxide 14. Within the semiconductor layer 13, a shallow trench isolation (STI) region 16 together with the embedded oxide region 14 defines one of the active regions of the semiconductor active region 18 shown in FIG. In a specific embodiment, as shown in FIG. 8, the active region 8 is ρ.

559952 V. Description of the invention (16) Type region or channel region 20, and two n + (source and drain) regions 22, the channel 20 is inserted between the source and non-electrode region 22. Obviously, the n-type channel can also be inserted in the two P + intervals. The source and drain regions 22 include individual deep implant regions 24 and 26 and individual extension regions 28 and 30. A gate dielectric 32 is inserted between the lower surface 34 of the gate electrode 36 and the SOI semiconductor substrate 40.上 表面 38。 Between the upper surfaces 38. The gate dielectric 32 shown in Fig. 8 is a single-layer dielectric 'but the gate dielectric may be a multi-layer dielectric.

Multiple-thickness silicide metal layers 42 and 44 are disposed between the source and drain regions 22. On the wound, the Shixihua metal region 28 is formed on the polycrystalline silicon regions of the individual deep implant regions 2 & and 26 and the individual deep implant junction regions 50 and 52, and the ultra-thin petrochemical metal region 54 The lines are formed on the individual extensions 28 and 30. The multiple-thickness silicide metal layers 42 and 44 may be made of typical well-known silicide metals, such as cobalt silicide (CoSi2), titanium silicide (TiSi2), silicide button (TaSD, nickel silicide (NiSi2), or similar metals. In specific implementations, For example, the multiple thickness silicided metal layers 42, 44 are made of cobalt silicide. The silicided metal region 48 may have a thickness between 50 angstroms and 250 angstroms, and the ultra-thin silicided metal region 54 may have a thickness between 25 angstroms and 100 angstroms. On the top of the gate electrode 36, there is a silicon oxide layer, which can be the same appropriate silicide layer 76 as described above, or by the shattered metal layer or by other stone material layers. 76 may have a spacer of 100 angstroms to 200 angstroms. 6 8 is a metal layer 76 extending from the upper surface 38 of the substrate 40 covering the gate, the silicided metal layer 76 is made of a metal material, and the stone evening gold 42 , 44 made of the same material, made of the material. Exemplary thickness of the silicided metal. The dielectric 32 and the SOI 'spacer 7 of the gate 36 are covered from the space.

559952 V. Description of the invention (17) The upper surface 38 of the SOI substrate 40 of the piece 68 extends upward. The spacers 68 and 78 are permanent spacers for forming the multiple thickness layers 42, 44 and the source and drain regions 22, which will be described in detail later. It should be understood that the active region 18, the channel 20, the source and drain regions 22, the gate dielectric 3, the gate electrode 3 6, the silicided metal layer 7 6, multiple thicknesses of the silicided metal layers 42, 44 and each The spacers together constitute the S (H) device of the present invention. The operation principle of the SO I transistor with multiple thickness silicided metal layers over the source and drain regions of the gate device will be described in detail later. It should be understood that the SOI The transistor device 10 'may additionally have other shapes shown in Fig. 8. The steps of the method 1510 for a semiconductor device 31o (similar to the aforementioned semiconductor device 10) are summarized in the flowchart shown in Fig. Figures 9 to 14 illustrate each step of the method 1 5 1 0. It should be understood that the method 5 and the semiconductor device 310 described below are for illustration purposes only, and many of the foregoing are in materials, thickness, and / or structure Different suitable embodiments are also applicable to the method 1510 and / or the semiconductor device 31. In step 1512, the conventional polysilicon gate system is formed on the SO! Substrate as the SOI transistor device 3 丨〇 intermediate stage of manufacturing, as in the 9th As shown, the SOI transistor device 310 includes a semiconductor substrate 312, an embedded oxide (βχ) layer 314 formed on the semiconductor substrate 312, and a semiconductor layer 313 disposed on the buried oxide layer 314. The exemplary embedded oxide layer may have a thickness between 1800 angstroms and 2200 angstroms, and the exemplary semiconductor layer 313 disposed on the desired oxide layer 314 may have a thickness between 800 angstroms and 100 angstroms. A suitable semiconductor material such as silicon carbide, germanium or the like may be used as the semiconductor provided on the embedded oxide layer 314.

92072.ptd ΗΒ Page 23 559952 V. Description of the invention (18) A bulk layer 313 is a shallow trench isolation (STI) region 316 within the semiconductor layer 313 provided on the embedded oxide layer 314, and the shallow trench isolation region Together with the embedded oxide layer 314, the location of the semiconductor active region 318 for the next step is defined. The shallow trench isolation area 3 1 6 is filled with an insulator to electrically isolate individual electrical devices such as the SOI transistor device 310. Other isolation techniques known in the art can also be used to isolate the SOI transistor device 310. The gate dielectric 332 is interposed between the lower surface 334 of the gate electrode 336 and a part of the upper surface 338 of the SOI semiconductor substrate 340. The gate dielectric 332 shown in FIG. 9 is a single-layer dielectric, but the The gate dielectric may be a multilayer dielectric as described above. The gate dielectric 332 can be made of a suitable gate dielectric material, such as silicon dioxide (Si02), nitride nitride (Si3N4), aluminum oxide (Al203), hafnium oxide (Hf02), oxygen Silicon nitride (siN〇) or similar material. In this specific embodiment, the dielectric layer 3 3 2 is made of nitride nitride. The exemplary dielectric layer 332 of the nitride nitride may have a thickness between 13 angstroms and 16 angstroms. The gate electrode 336 can be made of a typical well-known conductive material such as polycrystalline silicon. The exemplary gate electrode 3 36 may have a thickness between 800 Angstroms and 1200 Angstroms. A more detailed description of the implantation process of forming the source and drain regions 322 that can be performed after the formation of the inter-electrode is described later. In this specific embodiment, the inter-electrode dielectric 332 is inserted below the channel area 32 °, which is performed by the aforementioned alternative method before this step. In step 1 5 1 4, the source electrode 1 Λ闰 %% — two, two, κ, 〆, and polar extension regions 328, 330 are formed as shown in FIG. 10. Prior to the formation of the source electrode and the extension of the electrode,

ΙΗΗ »92072.ptd Page 24 559952 V. Description of the invention (20) The size is reduced, leaving an oxide spacer similar to the spacer 3 6 8 shown in Figure 11. The oxide spacer can be removed from the semiconductor The surface 338 of the substrate 340 extends to a height between 3000 Angstroms and 4000 Angstroms. Subsequently, in step 1518, a metal layer 360 is formed over the source extension region and the drain extension region 328 and 330. The metal layer 360 is formed by sputtering, chemical vapor deposition (CVD) ) Or vapor deposition. The metal layer 360 may include any metal such as metal, metal, metal, metal, tungsten, and / or the like. In a specific embodiment, the metal layer 36 is formed using cobalt. The reason is that cobalt silicide is preferred. Having dopant diffusion and segregation constants allows the formation of shallow conformal source and drain junctions, as shown in Figure 12. After the metal layer 360 is deposited, a heating cycle is performed. The heating cycle is used to make a part of the metal layer 360 react. The metal layer 360 covers the source extension region 328 and the drain extension region 330. on. If the metal layer 360 includes silicon and the semiconductor layer 313 is silicon, cobalt and silicon react within the interface region to form cobalt silicide (CoS i2). Depends on the type of metal used. Typical heating cycle temperature for forming silicided / self-aligned silicided metal from 200 ° C to 70 ° C. In all cases, the silicided metal region 364 shown in FIG. 3 (also referred to as self-aligned silicided metal region in the case of self-alignment) is applied to the source and drain regions through the heating cycle. Formed within 3 2 2, all unreacted portions of the metal layer 3 60 are removed by known etching techniques, but the silicided metal region 3 6 4 is not removed. For example, cobalt can be etched using a directional etching chemistry such as hydrochloric acid (HC I) and water. It should be understood that at this time, a metal layer 362 of the same or dissimilar metal may be formed on the gate electrode 3 3 6 and processed by the self-alignment method as described above.

92072.ptd Page 26 559952 V. Description of the invention (22) The temperature is performed for 5 to 15 seconds. The second spacer 3 8 0 is formed in the manner described in step 1 5 2 4 and the spacer 3 8 0 is Formed on the spacer 3 7 8 and any exposed portion of the spacer 3 6 8. It should be understood that as long as the spacer 3 78 can only completely cover the spacer 368, the spacer 380 can only cover the spacer 378. Then in step 1 526, the metal layer 382 is deposited and heated as described above to the main source and drain junction regions 3 50, 3 5 2 and the main source region 324 and the main drain region. A multiple-thickness petrified metal layer 372 of cobalt silicide is formed above 326 (as shown in FIG. 14). The spacer 3 6 8 covering part of the petrified metal layer region 3 64 prevents the metal layer 36 6 from being deposited on the extremely thin portion of the silicided metal layer 364 covering the source and drain extension regions 328 and 33 0. To form an extremely thin petrified metal layer 3 5 4. It should be understood that different metals can be formed on the silicided metal layer 364 and the petrified metal layer having multiple thickness regions and multiple layers (not shown) can be obtained as described above. In addition, it must be understood that at this time, a metal layer 384 of the same or dissimilar metal may be formed on the silicided metal layer 366 and processed in a self-alignment method as described above to manufacture the silicided metal layer 76 (as shown in FIG. 8). As shown). Subsequently, in step 1528, a fourth or subsequent spacer may be formed to ensure compliance with the main source and the portion above the electrode region 3 2 2; and a metal layer. Then, the metal layer can be deposited and heated as described above to form a multiple thickness silicide metal layer of cobalt silicide on the source and drain regions 322. A spacer covering a portion of the previous silicided metal layer prevents the metal layer from being deposited on the film layers. In this way, multiple thickness silicided metal layers can be adjusted to the device

92072.ptd

559952 V. Description of Invention (23) Application. It should be understood that different metals can be formed on the silicided metal layer 360 and processed as described above to obtain a silicided metal layer having multiple thickness regions and multiple layers (not shown). In addition, it should be understood that at this time, a metal layer 382 of the same or dissimilar metal may be formed on the silicided metal layer 364 and processed in a self-alignment method as described above to manufacture the silicided metal layers 42 and 44 (as in Section 8 As shown in the figure). In this way, the device 10 'having petrified metal having multiple thicknesses can be manufactured. An SOI transistor device including multiple thickness silicided metal layers will now be described according to another embodiment of the present invention. The device includes a gate defining a channel interposed between a source and a drain, and one of the gates provided in an active area of the SO I structure. Furthermore, the device includes multiple thickness silicided metal layers formed on the main source and drain regions and the source and drain extension regions, which will be described in detail later. Moreover, the device also includes a single permanent spacer for forming the device, the device being formed from a disposable spacer formed on a side wall of the gate. Optionally, the disposable spacer may be formed in such a manner that it can be selectively etched multiple times during adjustment of the multilayer silicide metal as required for the application of the device. In addition, a portion of the multiple-thickness silicide metal layer formed on the source and drain extension regions is thinner than a portion of the multiple-thickness silicide metal layer formed on the main source and drain regions. The device includes a silicided metal layer formed on the polycrystalline silicon electrode of the gate. Moreover, the multiple-thickness silicide metal layer may include two layers of at least two different kinds of petrified metal layers. Furthermore, the multiple thickness silicided metal layers formed on the source and drain regions and the silicided metal layers formed on the polycrystalline silicon electrode may belong to different types, and

92072.ptd Page 29 559952 V. Description of Invention (24) ~ --- Self-aligning structure can be formed without new cover. Referring to FIG. 16 first, the S0! Transistor device of the present invention is marked with the component symbol 1 0n. The SO I transistor device 10 is formed in a semiconductor-on-insulator (SOI) structure. The SOI structure has a semiconductor substrate 2 and an embedded oxide (B0X) layer 14 ′ formed on the semiconductor substrate 12. And a semiconductor layer 13 disposed on the pseudo-embedded oxide layer 14. Within the semiconductor layer 13, a shallow trench isolation (STI) region 16 together with the embedded oxide region 4 defines one of the active regions as shown in the semiconductor active region 18 in FIG. In a specific embodiment, as shown in FIG. 16, the active region 18 is a P-type region or a channel region 20 and two N + (source and drain) regions 22, and the channel ^ 20 is interposed Between the source and drain regions 22. Obviously, the n-type channel can also be inserted in the two P + interval. The source and drain regions 22 include individual deep implant regions 24 and 26, and individual extension regions 28 and 30. The gate dielectric 3 2 is interposed on the lower surface 34 of the gate electrode 36 and Between the upper surfaces 38 of the SOI semiconductor substrate 40. The gate dielectric 32 shown in FIG. 16 is a single-layer dielectric, but the gate dielectric may be a multi-layer dielectric. The multiple-thickness silicide metal layers 42, 44 are disposed on the source and drain regions 22, and the silicide metal regions 28 are formed in individual deep implant regions 2 4 and 26 and individual deep implants. On the polycrystalline silicon regions of the junction regions 50 and 52, the ultra-thin petrified metal region 54 is formed on the individual extension regions 28 and 30. The multiple-thickness silicide metal layers 42 and 44 may be made of a typical well-known silicide metal, such as cobalt silicide (CoSi2), titanium silicide (TiSi2), silicide button (TaS i2), nickel silicide (N i S i2), or the like. metal. In a specific embodiment, the multiple-thickness shredded metal layers 42 and 44 are made of shredded metal. Shredded metal

559952 V. Description of the invention (25) The region 48 may have a thickness between 50 Angstroms and 250 Angstroms, and the ultra-thin petrified metal region 54 may have a thickness between 25 Angstroms and 100 Angstroms. On top of the gate electrode 36 is a silicided metal layer 76. The silicided metal layer 76 may be made of the same appropriate silicided metal material as described above. Made of the same material, or made of other silicided metal materials as previously described. An exemplary silicided metal layer 76 may have a thickness between 100 angstroms and 200 angstroms. The spacer 68 extends upward from the upper surface 38 of the substrate 40 covering the gate dielectric 32 and the gate dielectric 36, and the spacer 68 is used to form the ultra-thin silicided metal region 54. Permanent spacer, detailed later. It should be understood that the active area 18, channel 20, source and drain area 22, gate dielectric 3 2, gate electrode 3 6, silicided metal layer 7 6, multiple thicknesses The silicided metal layers 42 and 44 and the continuous spacers together constitute the 30 [] device of the present invention. The operation principle of the SOI transistor with multiple thicknesses of the silicided metal layer above the source and drain regions of the gate device is described later. Detailed description. It should be understood that the SCH transistor device 10 ″ may additionally have other shapes shown in FIG. 16. An overview of the steps of the method 2310 for a semiconductor device 41〇 (similar to the aforementioned semiconductor device 101). In the flowchart shown in Fig. 23, Figs. 17 to 22 illustrate each step of the method 2310. It should be understood that the method 2310 and the semiconductor device 410 described below are for illustration purposes only, and many of the aforementioned materials, Appropriate specific embodiments with different thicknesses and / or structures also apply In the method 2310 and / or the semiconductor device 41 °, ^ X ^ In step 2312, the conventional customer said μ ΟΑΤ ^ Xixi Shishixi gate system is formed on the SO I substrate as the S 0 I The intermediate stage of the manufacture of the transistor device 4 1 Q.pa b 1 υ. As in the first

92072.ptd 31st stomach 559952 V. Description of the invention (26) 17 As shown in the figure, the SOI transistor device 41 includes a semiconductor substrate 412, and an embedded oxide layer (βο) is formed on the semiconductor substrate 412. x) 414, and a semiconductor layer 413 disposed on the embedded oxide layer 414. The exemplary embedded oxide layer 414 may have a thickness between 1 800 Angstroms and 2200 Angstroms, and the exemplary semiconductor layer 413 disposed on the buried oxide layer 414 may have a thickness between 800 Angstroms and 1000 Angstroms. thickness of. A suitable semiconductor material such as silicon, carbide, germanium, or the like can be used as the semiconductor layer 413 provided on the embedded oxide layer 414, and the semiconductor layer 413 provided on the embedded oxide layer 414 is shallow. A trench isolation (STI) region 416. The shallow trench isolation region together with the post-oxide layer 414 define the location of the semiconductor active region 418 for the next step. The shallow trench isolation area 41-6 is filled with an insulator to electrically isolate individual electrical devices such as the SOI transistor device 4 10. Other isolation techniques known in the art can also be used to isolate the SOI transistor device 410. The gate dielectric 432 is interposed between the lower surface 434 of the gate electrode 436 and a part of the upper surface 438 of the SOI semiconductor substrate 44. The f gate dielectric 432 shown in FIG. 17 is a single-layer dielectric, but The gate dielectric may be a multilayer dielectric as described above. The gate dielectric 432 may be made of a suitable gate dielectric material, such as silicon dioxide (Si 02), silicon nitride (Si3N4), aluminum oxide (Al203), hafnium oxide (Hf〇2), Silicon oxynitride (siN〇) or similar materials. In this embodiment, the dielectric layer 432 is made of nitride nitride. The exemplary dielectric layer 432 of silicon nitride may have a thickness between 13 angstroms and 16 angstroms. The gate electrode 436 may be made of a typical well-known conductive material such as polycrystalline silicon. The gate electrode 436 may have a diameter of 800 to

559952 Description of the invention (27) Thickness between 1200 Angstroms. A more detailed description of the implantation process of the source and drain regions 4 2 2 that can be opened after the gate is formed is described later. In this embodiment, the channel region 420 inserted between the source and drain regions 422 under the inter-electrode dielectric 432 is type-doped by the aforementioned alternative method before this step. Before the gate is formed, the semiconductor layer 413 of the semiconductor substrate 44 0 may be appropriately doped to form a region or layer of an electrically active material as the final use of the active region of the SO I transistor device 4 1 0 to be formed. For example, boron or indium can be implanted to form a p-type region or channel as an n-type device, and phosphorus or ping can be implanted to form an n-type region or channel as a p-type device. It should be understood that after the interlayer is formed, the semiconductor layer 413 may be appropriately doped by a technique known in the art. Next, in step 2314, a disposable spacer 478 may be formed around the gate to ensure compliance with the gate 436 and the further extended regions 428, 430 for the main source and non-electrode regions in the next step. The formation of 426, 428 is free from contact with dopants. To form the disposable space, a spacer material such as an oxide material, such as silicon dioxide (Si 02), silicon nitride (Si3N4), or similar oxide material, is then deposited on the substrate 440 (not shown) The oxide layer is formed on the top surface 438 of the SOI substrate 440 by the deposit. The oxidized deposit can be performed, for example, by plasma-assisted chemical vapor deposition (PECVD). The disposable spacer 4 7 8 can be selectively etched multiple times to adjust the formation of the multiple thickness silicided metal layer. The oxide is etched with a suitable etchant.

92072.ptd Page 33 559952 V. Description of the invention (30) The implant may be the same material as the main vertical implant, or it may contain different materials. It should also be understood that the extension implants can be different from one another if needed. The resulting structure is shown in Figure 21. It is understood that many other sequences or steps can be used to complete the implant. In addition, 'Although the extension implant and the main implant are individually described with one implant,' it must be understood that a larger number of implants can be used. Furthermore, the halogen implant can be used for patterning the gate electrode 436 or / and forming spacers 468, 4 7 8 to implant the extension. For example, an obliquely extended implant (μ to 45 degrees) uses four rotations with a total implantation dose of 3 · 5 X 1 0 13 to 5 X 1 〇13 atoms / cm 2 with implantation energy of 30 to 80 Thousand electron volts are implanted ^ or BF2. In this way, the source and drain regions 422 are formed. After implantation ', the semiconductor device 410 may undergo rapid thermal annealing (RTA) at this time or later. The exemplary rapid thermal anneal can be performed at a temperature ranging from 0,020 to 1,050 ° C for a period of 5 to 15 seconds. Then, in step 2324, the 'metal layer 453 is deposited and heated as described above to form a multiple thickness silicided metal layer 454 on the source and drain extension regions 4 2 8 and 4 3 0 ( (As shown in Figure 16). A spacer 468 covering a portion of the petrified metal layer region 41 3 controls the deposition of a metal layer 453 overlying the source and non-polar extension regions 428 and 430, and thus controls the extremely thin petrified metal layer The layer 4 5 4 and the proximity of the source to the non-polar extensions 4 8 6, 4 8 8. It should be understood that different metals can be formed on the silicided metal layer 466 and processed as described above to obtain a silicided metal layer having multiple thickness regions and multiple layers (not shown). In addition, it is important to understand that

92072.ptd 559952 V. Description of the invention (31) A metal layer 484 may be formed over the shredded metal layer 466 and processed in a self-alignment method as described above to manufacture a silicided metal layer 7 6 (as shown in FIG. 16 As shown). It should be understood that different metals can be formed on the silicided metal layer 464, and the silicided metal layer having multiple thickness regions and multiple layers (not shown) can be obtained by processing as described above. In addition, it must be understood that at this time, metal layers (not shown) of the same or dissimilar metals may be formed over the silicided metal layer 464 and processed in a self-alignment method as described above to produce the silicided metal layer 42, 44 (as shown in Figure 16). In this way, a device 10 with multiple thicknesses of silicidated metal can be manufactured. As described in the above drawings, in other specific embodiments of the present invention, the source and drain regions 222, 322, or 422 can be made using methods described below. As mentioned above, the ion implant can use dopant atoms to dope the silicided metal region 242, 244, 342, 344, or 442, 444. Side, ytterbium, or padding can be used alone or as the doping in any combination. Agent atom. Therefore, an n-type channel transistor or a p-type channel transistor may be formed. In one embodiment, the dopant atom is provided only in the silicided metal region 242, 244, 342, 344, or 442, 444. Dopant atoms are used for ion implantation. The dopant atoms are driven into the semiconductor from the silicided metal region 2 4 2, 2 4 4, 3 4 2, 3 4 4 or 442, 444 using another heating cycle. Layer 213, 313, or 413 to form the source and drain regions 2 2 2, 3 2 2 or 4 2 2. In another embodiment, the ion implant of the dopant atom can be implanted with high energy to Ensure that the dopant atoms penetrate the silicided metal region 242, 244, 342, 344 or 442, 444 and As the source and drain regions 2 2 3 2 2 2 or 4 2 to be important that the metal silicide

92072.ptd Page 37 559952 V. Description of the invention (32) The source and drain regions 222, 322, or 422 can be formed by ion implantation of regions 242, 244, 342, 344, or 442, 444. The method of Figure 6, Figures 9 to 14 or Figures 17 to 22 is performed at any point in time. Self-alignment is preferred but not necessary. After implantation, the semiconductor device 210, 310, or 410 is subjected to rapid thermal annealing (RTA). The exemplary rapid thermal annealing can be performed at a temperature of 1,020 to 1,050 ° C for a period of 5 to 15 seconds. In another embodiment, the semiconductor layer 2 1 3 is lightly doped and forms a polycrystalline silicon gate and the intermediate structure as shown in FIG. 1. The structure is lightly doped to form a lightly doped thin layer on the source and drain regions 2 2. A metal layer such as cobalt is deposited on the platinum lightly doped layer and annealed as described above to form a thin layer of petrified metal in the thin lightly doped region. It should be understood that the same metal or dissimilar metal layer may also be deposited on the polycrystalline silicon gate 236 to form a self-aligned silicided metal structure. Then, a spacer may be formed using the aforementioned method to protect a portion of the thin silicided metal layer. Now, using the aforementioned method, heavier doping can be done to form the main source and drain regions 224, 226. Next, another metal layer that is the same as or different from the previous one is deposited and annealed as previously described to form a thin silicided metal region overlying the main source and drain regions 224,226. In this way, a device 2 1 0 having multiple thicknesses of silicided metal is manufactured. It should be understood that the method of forming a spacer and depositing a metal layer to form a multiple-thickness region can be performed multiple times to adjust the multiple-thickness structure to suit the application to which it will be applied. [Industrial applicability] The aforementioned electrical device can adjust the resistance in different regions, such as the source

92072.ptd page 38 V. Description of the invention (33) Polycrystalline silicon region, drain, source, and drain extension regions with drain region. " The junction between the Hai source and the non-polar region and the effect of the floating body effect on the device 'can reduce the shortcomings of the electrical installation of β U on the SOI structure. Although the device 10, J 〇, "seldom exemplify, the other # and 1 〇" are based on the SO I structure of the transistor (EEPROMs), can be built \ Read memory donkeys, M, lay-type read-only memory (EPROMs), flash memory two machines, one, one pole, thin film transistors (TFTs) and similar devices can be shaped: Yu Gang described in the soi structure It is formed on or on other substrates such as germanium (GOI) on the insulating layer. Furthermore, these devices can also be formed on a large substrate to benefit from the features of the invention described above. Although the specific embodiments of the present invention have been described in detail, it should be understood that the scope of the present invention is not limited to this, but includes all the changes, modifications, and changes that fall within the spirit and scope of the scope of the attached patent application. Equivalent device.

92072.ptd Page 39 559952

[Brief description of the drawings] :: Ming: These and other features will be explained with reference to the attached description and drawings, where: ^ The picture shows an insulating + conductor (SOI) transistor including multiple thickness silicided metal layers according to the present invention A cross-sectional view of the device; it is apparent that the thickness of the first layer of silicon, the first metal layer, and the second metal layer of the device on the edge of the body. The thickness I to FIG. 6 are the semiconductor-on-insulator (SOI) transistors of FIG. 1. The surface drawing 'contains the multiplexed metal layer according to the present invention in the middle stage of manufacturing; the figure is a flowchart of the method for manufacturing the semiconductor (S01) transistor device on the multi-thickness shredded metal edge body according to the present invention in FIG. 1 8 is a cross-sectional view of a semiconductor-on-insulator (S0I) transistor device including multiple thickness silicidation according to another embodiment of the present invention; 9 to 14 are semiconductor-on-insulator (s 〇I) A cross-sectional view of a transistor, including a petrified metal layer according to the present invention during the manufacturing phase; FIG. 15 is an insulator including a petrified metal layer with multiple thicknesses according to the present invention in FIG. 8 Semiconductor (SO I) Transistor FIG. 16 is a cross-sectional view of a semiconductor-on-insulator (SO I) transistor device including multiple thickness silicided metal layers according to another embodiment of the present invention, and FIGS. 17 to 22 are FIG. 16 is a cross-sectional view of a semiconductor-on-insulator (SOI) transistor device including a multiple-thickness silicided metal layer according to the present invention at an intermediate stage of manufacturing;

92072.ptd Page 40 559952

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 23 is a diagram of a “soi” transistor device on an insulator of FIG. 16 [Description of Element Symbols] 1 0, 1 0, 1 1 0, 2 1 0, 3 1 0, 4 1 0 Transistor devices 1 2, 2 1 2, 3 1 2, 41 2, 240, 340, 440 Semiconductor substrates 13, 213, 313, 413 Active layers (semiconductor layers) 14, 214, 314, 414 embedded oxide layer 16, 216, 316, 416 shallow trench isolation area 18 active area 20 channel 2, 222, 224, 22 6, 322, 422 source and non-polar area 24, 26 deep implant area 28, 30 Extension area 32, 232, 332, 432 Gate dielectric 34, 234, 334, 434 Lower surface 36, 23 6, 336, 436 Gate electrode 38, 238, 338, 438 Upper surface 40 SOI semiconductor substrate 42, 44, 282 Multi-thickness silicided metal layers 46,242, 244, 264, 342, 344, 364,442, 444, 464 Shixihua metal area 48 Thin silicided metal area layer map. 5 0, 52 Deep implant junction 54 Very thin petrified metal zone

92072.ptd Page 41 559952 Simple illustrations 56,76,264,266,272,276,354,364,366,464,466 Silicided metal layer 58, 68, 78, 268, 2 78, 324, 32 6, 368, 378, 380, 424, 426, 478, 468 Spacer 22 0 , 42 0 channel area 228, 230, 328, 330, 428, 430, 486, 488 source and drain extension areas 260, 262, 280, 360, 362, 382, 460, 462, 484 metal layer 250, 252, 352, 356, 450, 452 Main source and non-electrode junctions 254, 272, 368, 378 Covers

92072.ptd Page 42

Claims (1)

559952… Jewish: 911Q6 € g. Year. June (0 __ VI. Patent application scope 1. A transistor device (1 0) formed on a semiconductor substrate (1 2), the semiconductor substrate having an active area (1 8) defined by an isolation trench (16) ), The device includes: a gate electrode (3 6), which defines a channel (2 0) interposed between a source electrode and a drain electrode (2 2) formed in an active region of the semiconductor substrate, wherein the source electrode And drain include the main source and drain regions (2 4 and 2 6) and source and drain extension regions (2 8 and 30); and multiple thickness silicided metal layers (4 2 and 4 4), which are It is formed on the main source and drain regions and the source and drain extension regions, wherein the multiple-thickness petrified metal layers formed on the source and non-electrode extension regions are divided into points (5 4) It is thinner than the portion (4 6) of the silicided metal) formed on the main source and drain regions. 2. The transistor device according to item 1 of the patent application scope includes a plurality of spacers for forming the device. 3. The transistor device as claimed in claim 1 includes a disposable spacer for forming the device. 4. For example, the transistor device of the scope of patent application, wherein the semiconductor substrate is a semiconductor (S 0 I) substrate on an insulating layer. The semiconductor substrate on the insulating layer is interposed between the active layer and the main semiconductor substrate. An embedded oxide (BOX) layer, and the active area is again defined by the embedded oxide layer. 5. The transistor device as claimed in claim 4, wherein the semiconductor substrate on the insulating layer is a germanium on insulating layer (GO I) substrate. 6. If the transistor device according to any one of claims 1 to 5, Revised 92072.ptc Page 1 2003. 07. 09. 044 559952 _ Case No. 91106470 Bang > Year I month and month I revised _ 6. In the scope of the patent application, the multiple thickness silicided metal layer contains at least two different types Petrified metal layer. 7. The transistor device according to item 6 of the patent application, wherein the at least two different types of petrified metal layers include: a first silicided metal layer formed on the source and drain regions and extending Into the extension region; and a second silicide metal layer formed on the main source and drain regions. 8. The transistor device according to item 6 of the patent application, wherein the at least two different types of petrified metal layers include: a first silicided metal layer formed on the source and drain regions, and A thickness in a range between 25 Angstroms and 100 Angstroms extends into the extension region; and a second silicided metal layer formed in the main portion with a thickness in a range between 50 Angstroms and 250 Angstroms. Source and drain regions. 9. The transistor device according to any one of claims 1 to 5, comprising a second silicided metal layer formed on a polycrystalline silicon electrode of the gate. 10. The transistor device according to any one of claims 1 to 5, wherein the multiple thickness silicided metal layer formed on the polycrystalline silicon region of the main source and the drain region is formed on the main source. The portion of the silicided metal layer in the main junction region of the pole and drain regions is thicker. 1 1. The transistor device according to any one of claims 1 to 5 in which the multi-thickness silicide gold formed on the source and drain extension regions is formed. Revised 92072.ptc Page 2 Within the range. 1 2. The transistor device according to any one of claims 1 to 5, wherein the thickness of the portion of the multiple-thick silicided metal layer formed on the main source and drain regions is 50 angstroms. In the range between 2 and 50 Angstroms. 13. The transistor device according to item 10 of the scope of patent application, wherein the thickness of the portion of the multi-thick silicide metal layer formed on the polycrystalline silicon region of the main source and drain regions is between 100 Angstroms and 100 Angstroms. Within the range of 3 0 0 angstroms. 1 4. The transistor device according to item 2 of the patent application scope, wherein the plurality of spacers are permanent spacers formed in successive steps during the formation process of the device. 1 5. The transistor device according to item 2 of the patent application scope, wherein the first spacer is formed on the side wall of the gate; and the second spacer is formed on the first spacer. 16. The transistor device according to item 2 of the patent application scope, wherein the third spacer is formed on the previous spacer. 1 7. The transistor device as claimed in claim 3, wherein the permanent spacer is formed by the disposable spacer. 18. The transistor device of claim 3, wherein the disposable spacer forms a first intermediate spacer to control the formation of the source and drain regions and the multiple-thickness silicided metal layer. 19. The transistor device of claim 18, wherein the first intermediate spacer forms a second intermediate spacer. 2 0. A method for manufacturing a transistor device formed on a semiconductor substrate having an active area defined by an isolation trench, the method includes the following steps Revised 92072.ptc Page 3 2003. 07. 09. 046 559952 _Case No. 91106470 Song > Year > 〇 P Pending Amendment _6. Application for patent scope Steps: Form the gate, the gate definition is formed in the A channel between the source and the drain is interposed in one of the active regions of the semiconductor substrate; a multiple-thickness silicided metal layer formed on the main source and the drain region and the source and the drain extension region, wherein The portion of the multiple thickness silicided metal layer formed on the source and drain extension regions is thinner than the portion of the silicided metal layer formed on the main source and drain regions. 2 1. The method according to item 20 of the patent application scope, further comprising the steps of: forming a first spacer on a gate sidewall; and forming a second spacer on the first spacer. 2 2. The method of claim 20 in the scope of patent application, further comprising the following steps: forming a disposable spacer on a side wall of the gate electrode. 2 3. The method according to any one of claims 20 to 22 in the scope of the patent application, which comprises a portion of a multiple-thick silicided metal layer formed on the polycrystalline silicon region of the main source and drain regions, compared to a portion formed on A step of thickening a portion of the multiple thickness silicided metal layer above the main interface between the main source and the drain region. 24. The method according to any one of claims 20 to 22, wherein the semiconductor substrate is provided with an embedded oxide (BOX) layer interposed between the active layer and the main semiconductor substrate. A semiconductor-on-insulator (SOI) substrate and the active region is defined by the embedded oxide layer. 25. The method according to item 24 of the scope of patent application, further comprising a multiple thickness silicided metal layer formed on the polycrystalline silicon region of the main source and drain regions. Revised 92072.ptc 2003. 07. 09. 047 Page 4 559952 _ Case No. 91106470 Amendment _ 6. The scope of the patent application is formed above the main interface between the main source and drain regions Steps of thickening part of the multiple thickness silicided metal layer. 26. The method according to item 21 of the patent application scope, further comprising the step of forming a third spacer on the second spacer. 27. The method according to item 21 of the patent application scope, further comprising the step of selectively etching the disposable spacer multiple times to adjust the formation of the multiple thickness silicided metal layer. Revised 92072.ptc 2003.07.09. 048 Page 5 559952 559952 L one one β / 9 410 466 f 436 Figure 21 442 422 468, 432 ^ 464 468 434 444, 438 464 "422 41 (414-1 424 450 418 430 426 416 413 412 · 440