558867 A7 B7 五、發明説明（1 ) 包含_聯場效電晶體之電路配置 本發明係關於一種包含串聯場效電晶體之電路配置。本 發明特別是關於一種包含高頻率應用之場效電晶體的電路 配置。 包括串聯場效電晶體，舉例來說，四極管或五極真空 管，之電路配置，通常用作高頻率應用之可控制放大器。 串聯之場效電晶體具有複數個閘極終端，待處理之信號通 常被施加到第一閘極，而第二閘極則被用來控制增益。在 此一情況中，控制是希望涵蓋大的增益週期（如70 dB )。 舉例來說，此類型之電路配置顯示於德國專利41 34 177文 件中。 調整金屬氧化物半導體（MOS )四極管/五極真空管之增 益，通常是藉由調降連接到第二閘極之電壓來實施。如果 達到線性化的控制回應、高度控制範圍與低的互調失真， 則與調降施加到第二閘極之電壓有關，第一閘極上的電壓 將被調升。早期包括串聯場效電晶體之電路配置，舉例來 說，電視接收器之調整器電路，係藉由穩定操作電流之電 路來達成，其通常包含源極電阻器。 圖8概要地顯示此一電路配置，其包括兩個串聯場效電 晶體ATI與AT2與源極電阻Rs與高頻區塊之電容器Cs。將 被放大的信號E，被連接到第一場效電晶體AT 1之閘極電 極G1，而增益之控制則經由信號R來實施，其中信號R係 施加到第二場效電晶體AT2之閘極電極G 2。雖然額外的 源極暫存器R s降低可用供應電壓約3伏特，但既然這些電 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 558867 A8 B8 C8 D8 六 、申請專利範圍 路正常是以9至1 2伏特的供應電壓運作，此一缺點是可以 被容許的。圖9顯示此一電路之行為，其使用之實例為電 路增益為施加到閘極電極G 2之電壓（虛線）的函數。可以 發現在施加到閘極電極G 2之電壓的相當大範圍上，大多 可以線性地控制電路之增益。 在現代的電子信號處理中，使用愈來愈小的操作電壓。 這反而導致如圖8所示之源極電阻器Rs無法使用於現代之 電路配置中的情況，除非兩個串聯場效電晶體AT 1與 AT2，有小的供應電壓比例。可是，因為缺少源極電阻R s， 實質上的控制範圍，現在由電晶體特性單獨決定。 圖9顯示此一電路無源極電阻Rs之行為（實線）。從調升 狀態開始，而為了接著改變成短的與陡峭的下降，初始時 適度地執行調降的動作。因此，實際之增益控制，係在施 加到閘極電極G 2之電壓的相對小間隔上實施。可是，既 然在短的與陡峭的下降範圍中，即使是施加到閘極電極 G 2之電壓的小改變，與電晶體特性中小的偏差，都將引 起控制路徑增益中激烈改變，則在一控制信號增益之完整 控制循環中，因為增益之短的與陡峭的下降，使用電路變 得愈來愈困難。愈來愈精細的電晶體與往較低操作電壓的 趨勢，強化了這些特性。 因此，本發明之目的在具體指明包含串聯場效電晶體之 電路配置，其中此一電晶體減少或完全避免上述問題。本 發明之目的尤其是在具體說明包含串聯場效電晶體之電路 配置，其中此一配置保證有定義之開始與結束點之間，延 -5- 本纸張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)558867 A7 B7 V. Description of the invention (1) Circuit configuration including FET field effect transistor The present invention relates to a circuit configuration including a series field effect transistor. The present invention particularly relates to a circuit configuration including a field effect transistor for high-frequency applications. Circuit configurations that include series field effect transistors, such as tetrodes or pentodes, are often used as controllable amplifiers for high-frequency applications. The field effect transistor in series has a plurality of gate terminals. The signal to be processed is usually applied to the first gate and the second gate is used to control the gain. In this case, the control is intended to cover large gain periods (such as 70 dB). For example, this type of circuit configuration is shown in German patent 41 34 177. Adjusting the gain of a metal-oxide-semiconductor (MOS) tetrode / pentode vacuum tube is usually implemented by reducing the voltage connected to the second gate. If linearized control response, high control range, and low intermodulation distortion are achieved, it is related to reducing the voltage applied to the second gate, and the voltage on the first gate will be increased. Early circuit configurations including series field effect transistors, for example, TV receiver regulator circuits were achieved by circuits that stabilized operating currents, which usually included source resistors. FIG. 8 schematically shows this circuit configuration, which includes two field effect transistors ATI and AT2 in series, a source resistor Rs, and a capacitor Cs in a high-frequency block. The signal E to be amplified is connected to the gate electrode G1 of the first field effect transistor AT1, and the gain control is implemented by a signal R, where the signal R is applied to the gate of the second field effect transistor AT2极 electrode G 2. Although the additional source register R s reduces the available supply voltage by about 3 volts, since these electrical dimensions are applicable to China National Standard (CNS) A4 specifications (210X 297 mm) 558867 A8 B8 C8 D8 The patent application range normally operates with a supply voltage of 9 to 12 volts. This disadvantage can be tolerated. Figure 9 shows the behavior of this circuit, using an example where the circuit gain is a function of the voltage (dashed line) applied to the gate electrode G 2. It can be found that in a considerable range of the voltage applied to the gate electrode G 2, the gain of the circuit can be controlled linearly in most cases. In modern electronic signal processing, smaller and smaller operating voltages are used. This in turn leads to the situation where the source resistor Rs shown in FIG. 8 cannot be used in modern circuit configurations, unless the two series effect transistors AT 1 and AT 2 have a small supply voltage ratio. However, due to the lack of the source resistance R s, the substantial control range is now determined solely by the transistor characteristics. Figure 9 shows the behavior of the passive resistor Rs for this circuit (solid line). Starting from the raised state, and in order to change to a short and steep descent, the lowering action is performed moderately initially. Therefore, the actual gain control is performed at relatively small intervals of the voltage applied to the gate electrode G 2. However, since in a short and steep falling range, even a small change in the voltage applied to the gate electrode G 2 and a small deviation from the transistor characteristics will cause a drastic change in the control path gain, a control In the complete control loop of the signal gain, it becomes more and more difficult to use the circuit because of the short and steep drop of the gain. Increasingly finer transistors and a trend towards lower operating voltages reinforce these characteristics. Therefore, an object of the present invention is to specify a circuit configuration including a series field-effect transistor in which such a transistor reduces or completely avoids the above problems. The purpose of the present invention is to specifically describe the circuit configuration including a series field effect transistor, in which this configuration guarantees a defined start and end point. This paper standard applies to China National Standard (CNS) A4. Specifications (210 X 297 mm)
裝 訂 # 558867 A7 ~ ______B7 五、發明説明（3 ) 伸與線性化的控制響應。 此了目的係藉由包含至少兩個串聯場效電晶體之電路配 置來達成，其中該兩個串聯場效電晶體係中請專利範圍第 ^項中所主張之場效電晶體。本發明之進一步有利的具體 異施例、精緻與態樣，將從相依之申請專利 附圖中顯現。 +根據本發明’提供_種包含至少兩個串聯場效電晶體之 :路配置，其特別是對於高頻率應用，並具有—源極終 : 汲極終场、至少一個連接到第一操作電晶體之閘極 私極的輸出信號端，以及至少一個連接到第二操作電晶體 疋閘極電極的控制電壓端。根據本發明之電路配置，其特 徵為提供一電壓分壓器，其配置於控制電壓端與第二操作 :晶：之閘極電極之間，一第一電路單元，其連接到控制 私壓‘在超過第一、預定臨界電壓時，接通電壓分壓 =，以及一第二電路單元，其連接到控制電壓端，在超過 第二、預定臨界電壓時，使電壓分壓器失效，其 界電壓高於第一臨界電壓。 因此，根據本發明之電路配置，具有控制路徑之延伸係 建立自一定義之臨界，以及最後調升被壓縮成小間隔的優 點。由於根據本發明之電路配置，在信號增益之改良控制 =完整控制循環中，可以用相當直接的方式使用，因此， 實際之增益控制係在相當地放大的間隔上執行。 此外，根據本發明之電路配置，具有可以用簡單的方 法，以其尺寸度量匹配串聯操作電晶體之特性與各個應用 558867 A7 B7 五、發明説明（4 ) 之要求的優點。 在一較佳具體實施例中，電壓分壓器包括附有至少一個 第一電阻器之第一支路（arm)，以及附有至少一個第二電 阻器之第二支路，第二操作電晶體之閘極電極連接到一終 端，此一終端係配置於電壓分壓器之第一與第二支路之 間，而控制電壓終端則連接到電壓分壓器之第二支路。 在一進一步較佳具體實施例中，所提供之第一電路單元 是第一控制電晶體，其在電壓分壓器之第一支路中，係以 和第一電阻器串聯的方式連接。在此一情況中，對於第一 控制電晶體具有與第二操作電晶體相同之臨界電壓，是尤 其較佳的。此外，連接第一控制電晶體之汲極端與第一控 制電晶體之閘極電極是較佳的。 在一進一步較佳具體實施例中，第二電路單元具有至少 一個第二控制電晶體，其在電壓分壓器之第二支路中，係 以和第二電阻器並聯的方式連接。在此一情況中，第二控 制電晶體為”正常地斷路’’類型之P通道電晶體，是尤其較 佳的。 在一進一步較佳具體實施例中，第二電路單元具有至少 一個第二控制電晶體，其在電壓分壓器之第一支路中，係 以和第一電阻器串聯的方式連接。在此一情況中，第二控 制電晶體為”正常地接通”類型之η通道電晶體，是尤其較 佳的。 在一進一步較佳具體實施例中，控制電壓端經由電容 器，額外地連接到第二操作電晶體之閘極電極。此外，對 -7- 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 558867 A7 B7 五、發明説明（5 ) 於第一操作電晶體之閘極電極，最好提供一偏壓電路。在 此一情況中，偏壓電路宜具有至少兩個串聯場效電晶體， 且其閘極電極分別連接到第一與第二操作電晶體之閘極電 極。 圖式之簡單說明： 以下使用圖式之圖形，更詳細地解說本發明，其中： 圖1顯示根據本發明之電路配置的第一具體實施例， 圖2顯示增益之響應為控制電壓之函數， 圖3顯示根據本發明之電路配置的第二具體實施例， 圖4顯示根據本發明之電路配置之進一步具體實施例， 圖5顯示根據本發明之電路配置之進一步具體實施例， 圖6顯示根據本發明之電路配置之進一步具體實施例， 圖7顯示根據本發明之電路配置之進一步具體實施例， 圖8顯示根據先前技藝之電路配置的具體實施例，及 圖9顯示根據先前技藝之電路配置的響應，包括無源極 電阻器Rs(實線）與具有源極電阻器Rs(虛線）。 發明之詳細說明： 圖1顯示一電路配置之具體實施例，其係根據本發明。 在此一情況中，圖1中所示之電路配置包括兩個串聯場效 電晶體AT 1與AT2，其配置於源極終端與汲極終端之間。 也提供一輸入信號終端E，其連接到第一操作電晶體ATI 之閘極電極。控制電壓端R係相應地提供，其連接到第二 操作電晶體之閘極電極AT2。 電阻器R1與R2形成一電壓分壓器，其配置於控制電壓 -8- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 558867 A7 B7 五、發明説明（6 ) 端R與第二操作電晶體AT2之閘極電極之間。因此，電壓 分壓器包括附有第一電阻器R1之第一支路，與附有第二 電阻器R2之第二支路，其中第二操作電晶體AT2之閘極 電極被連接到配置於電壓分壓器之第一與第二支路之間的 終端，而控制電壓端R則是被連接到電壓分壓器之第二支 路。 此外，提供第一電路單元，其經由電阻器R1與R2連接 到控制電壓端R，並在超過第一、預定臨界電壓時，接通 電壓分壓器。在圖1所示之具體實施例中，所提供之第一 電路單元是第一控制電晶體ST1，其於電壓分壓器之第一 支路中，係以和第一電阻器R 1、第一控制電晶體ST1之汲 極終端，與所連接之第一控制電晶體ST1之閘極電極，串 聯的方式連接。此外，第一控制電晶體ST1具有與第二操 作電晶體AT2相同的臨界電壓。 此外，提供第二電路單元，其連接到控制電壓端R，並 在超過第二、預定臨界電壓時，使電壓分壓器失效，其中 第二臨界電壓高於第一臨界電壓。在如圖1所示之具體實 施例，第二電路單元具有第二控制電晶體ST2，其於電壓 分壓器之第二支路中，係以和第二電阻器R2並聯的方式 連接。在此一實例中，第二控制電晶體ST2是”正常地斷 路’’類型的p通道電晶體。 此外，提供第一操作電晶體AT1之閘極電極的偏壓電 路。在如圖1所示之具體實施例中，偏壓電路包括兩個串 聯場效電晶體BT1與BT2，其閘極電極分別連接到第一與 -9 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 558867 A7 B7 五、發明説明（7 ) 第二操作電晶體AT1與AT2之閘極電極。串聯場效電晶體 BT1與BT2在源極與汲極連接之間，係以和串聯操作之電 晶體ATI與AT2並聯的方式連接。為了改善增益、反饋與 交叉耦合特性，控制電壓端R係經由電容器C k，額外地 連接到第二操作電晶體A T 2之閘極電極。 下列具體實施例考慮控制響應在調升的方向中，總是從 完全地調降的狀態開始，也就是說，在下文中，行為被描 述成控制電壓端R上，控制電壓增加的函數。第一控制電 晶體ST1，具有與第二操作電晶體AT2相同之臨界電壓， 只有在超過臨界電壓時，才接通電壓分壓器。接著，直到 控制電壓不變地供應給第二操作電晶體AT2之閘極電極。 如此一來，控制之接通電壓或臨界電壓中之分散，都無法 變有效到任何大的程度。在後續範圍中，以控制路徑之本 質上陡峭的部分，調升第二操作電晶體AT2，電壓分壓器 變得有效，並以比率R1/(R1+R2)響應。 一旦控制電壓端R上的控制電壓達到第二臨界電壓.，第 二控制電晶體ST2變成接通的。這導致第二控制電晶體 ST2橋接第二電阻器R2，從而使後者無效。整個電壓分壓 器也相應地變無效，而控制電壓再一次實質上不變地供應 給第二操作電晶體AT2之閘極電壓。因此，和傳統控制比 較起來，很大程度地縮短了控制路徑之後續、緩慢地升起 的部分。這與控制電壓載入之增加有關，並轉而與發生整 個系統之負值反饋效應的優點有關。也就是說，控制電晶 體之控制臨界，不會突然地變得有效。圖2顯示相應之增 -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 558867 A7 B7 五、發明説明（8 ) 益響應為控制電壓之函數。此處，曲線1顯示根據本發明 之電路配置而建立的增益響應，而曲線2顯示根據先前技 藝之電路配置而建立的增益響應。 圖3顯示根據本發明之電路配置的第二具體實施例。除 了下列差異之外，第二具體實施例實質上與第一具體實施 例相當。除了在電壓分壓器之第二支路中，以和第二電阻 器R2並聯的方式連接之第二控制電晶體ST2外，圖3所示 之具體實施例的第二電路單元，具有由電阻器R3與R4所 形成之第二電壓分壓器。在此一情況中，第二電壓分壓器 係配置於第二控制電晶體ST2之閘極電極與控制電壓端R 之間。因此，可能經由第二電壓分壓器來設定第二電路單 元之臨界電壓。 視情況，可以提供進一步之電阻器Rv給第二電壓分壓 器之上游。在源極阻抗非常低的情況中，壓縮相可以藉由 此一電阻器R v來延伸。 圖4顯示根據本發明之電路配置的進一步具體實施例。 除了下列差異之外，此一進一步之具體實施例實質上與第 二具體實施例相當。除了第二控制電晶體ST2，以及由電 阻器R3與R4所形成第二電壓分壓器之外，圖4中所示之 具體實施例中的第二電路單元，具有進一步之控制電晶體 ST3與進一步之電阻器R5。 由於控制電壓增加，控制電晶體ST3是調升的，轉而意 味著第二控制電晶體ST2是接通的。因此，進一步之控制 電晶體ST3的接通電壓，乘以第二電壓分壓器之分壓器比 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 558867 A7 B7 五、發明説明（9 ) 率R4/(R4+R3)，決定了第二電路單元之臨界電壓。在此一 情況中，為了保持放大倍率R4/(R3+R4)(公差之放大）是小 的，控制電晶體ST3之臨界應該儘量高。 圖5顯示根據本發明之電路配置的進一步具體實施例。 與先前所示之具體實施例相反，圖5中所示之具體實施例 的第二電路單元，具有第二控制電晶體ST2，其於電壓分 壓器之第一支路中，以和第一電阻器R1串聯的方式連接。 在此一具體實施例中，第二控制電晶體ST2是「正常接通」 類型的η通道電晶體。 由於控制電壓增加，控制電晶體ST3是調升的，轉而意 味著第二控制電晶體ST2是斷路的。因此，第一電壓分壓 器之第一支路變成無效，轉而實質上不變地供應控制電壓 給第二操作電晶體ΑΤ2之閘極電極G2。再一次，進一步 . 控制電晶體ST3之接通電壓，乘以第二電壓分壓器之分壓 器比率R4/(R4+R3)，因此決定了第二電路單元之臨界電 壓。 圖6顯示根據本發明之電路配置的具體實施例。除了下 列差異以外，此一進一步具體實施例實質上與圖5所示之 具體實施例相當。在此一具體實施例的情況中，不是”正 常接通’’類型的η通道電晶體，而是使用”正常斷路π的η通 道電晶體，作為第二控制電晶體ST2。此外，此一具體實 施例中之電阻器R 5，不是直接連接到控制電壓端R，而 是連接到沒極端。 由於控制電壓增加，控制電晶體ST3是調升的，轉而意 -12- 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 558867 A7 B7 五、發明説明（1〇 ) 味著第二控制電晶體ST2是斷路的。因此，第一電壓分壓 器之第一支路變成無效，轉而實質上不變地供應控制電壓 給第二操作電晶體AT2之閘極電極G2。為了其適度地發 生，在第一電壓分壓器之第一支路中，於R1與R2之間， 插入第二控制電晶體ST2。在此一情況中，控制電晶體 ST2之源極上的電阻器R 1，具有高的負值反饋效應，從而 避免了突然的躍遷。為了保持放大倍率R4/(R3+R4)(公差 之放大）是小的，控制電晶體ST3之臨界應該儘量高。既 然操作電晶體AT1具有一通常是較高的臨界，因為偏壓電 路，此一作法也方便有利地用來控制電晶體ST2。當然， 也有可能從結合或其他的作法產生較高的臨界值。 圖7顯示根據本發明之電路配置的進一步具體實施例。 除了下列差異以外，此一進一步具體實施例實質上與圖6 中之具體實施例相當。圖7中所示之電路配置不同於與圖 6中所示之電路配置之處，在於第二操作電晶體AT2之閘 極電壓G 2的驅動中，額外的電壓抵銷。舉例來說，如果 操作電晶體AT2具有非常低的接通電壓，但在分量上確保 非常高的接通電壓，則這可以藉由額外的電晶體T來達 成。 根據本發明之電路配置，係基於藉助電壓分壓器R 1與 R2之延伸控制路徑，供應以比例R1/(R1+R2)分壓之控制 電壓給第二操作電晶體AT2之閘極電極。可是，此一延伸 只希望與控制路徑之陡峭部分相關。因此，提供第一與第 二電路單元，以使接通之電壓處於正確之位置，並明顯地 -13- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）Binding # 558867 A7 ~ ______B7 V. Description of the invention (3) Control response of stretching and linearization. This purpose is achieved by a circuit configuration including at least two field-effect transistors in series, wherein the two field-effect transistors in the series-claimed field-effect transistor system claimed in item ^ of the patent scope. Further advantageous specific embodiments, refinements and aspects of the present invention will appear from the dependent patent application drawings. + According to the present invention, 'provide_ a kind of circuit configuration including at least two field-effect transistors in series, which is especially for high frequency applications, and has-source end: drain end field, at least one connected to the first operating circuit An output signal terminal of the gate electrode of the crystal and at least one control voltage terminal connected to the gate electrode of the second operating transistor. According to the circuit configuration of the present invention, a voltage divider is provided, which is arranged between the control voltage terminal and the second operation: crystal: gate electrode, a first circuit unit, which is connected to the control private voltage ' When the first and predetermined threshold voltages are exceeded, the turn-on voltage is divided by =, and a second circuit unit is connected to the control voltage terminal. When the second and predetermined threshold voltages are exceeded, the voltage divider is invalidated. The voltage is higher than the first threshold voltage. Therefore, according to the circuit configuration of the present invention, the extension with the control path establishes a self-defined threshold, and finally has the advantage that the lifting is compressed into small intervals. Since the circuit configuration according to the present invention can be used in a fairly straightforward manner in the improved control of the signal gain = complete control loop, the actual gain control is performed at fairly enlarged intervals. In addition, the circuit configuration according to the present invention has the advantage that the characteristics of the series-operated transistor can be matched with various applications in a simple way with its size measurement. 558867 A7 B7 V. The requirements of the invention description (4). In a preferred embodiment, the voltage divider includes a first arm with at least one first resistor, and a second arm with at least one second resistor. The gate electrode of the crystal is connected to a terminal. The terminal is disposed between the first and second branches of the voltage divider, and the control voltage terminal is connected to the second branch of the voltage divider. In a further preferred embodiment, the first circuit unit provided is a first control transistor, which is connected in series with the first resistor in the first branch of the voltage divider. In this case, it is particularly preferred that the first control transistor has the same threshold voltage as the second operating transistor. In addition, it is preferable to connect the drain terminal of the first control transistor with the gate electrode of the first control transistor. In a further preferred embodiment, the second circuit unit has at least one second control transistor which is connected in parallel with the second resistor in the second branch of the voltage divider. In this case, the second control transistor is a “normally open” type P-channel transistor, which is particularly preferred. In a further preferred embodiment, the second circuit unit has at least one second transistor. The control transistor is connected in series with the first resistor in the first branch of the voltage divider. In this case, the second control transistor is of the “normally turned on” type η Channel transistors are particularly preferred. In a further preferred embodiment, the control voltage terminal is additionally connected to the gate electrode of the second operating transistor via a capacitor. In addition, it is applicable to -7- this paper size China National Standard (CNS) A4 specification (210 X 297 mm) 558867 A7 B7 V. Description of the invention (5) For the gate electrode of the first operating transistor, it is better to provide a bias circuit. In this case The bias circuit should have at least two field-effect transistors in series, and the gate electrodes of the bias circuits should be connected to the gate electrodes of the first and second operating transistors, respectively. Brief description of the diagram: Explain in more detail The present invention, wherein: FIG. 1 shows a first specific embodiment of the circuit configuration according to the present invention, FIG. 2 shows a gain response as a function of a control voltage, and FIG. 3 shows a second specific embodiment of the circuit configuration according to the present invention. 4 shows a further specific embodiment of the circuit configuration according to the present invention, FIG. 5 shows a further specific embodiment of the circuit configuration according to the present invention, FIG. 6 shows a further specific embodiment of the circuit configuration according to the present invention, and FIG. 7 shows a further specific embodiment of the circuit configuration according to the present invention A further specific embodiment of the circuit configuration is shown in FIG. 8. FIG. 8 shows a specific embodiment of the circuit configuration according to the prior art, and FIG. 9 shows the response of the circuit configuration according to the prior art, including the passive resistor Rs (solid line) and Resistor Rs (dotted line). Detailed description of the invention: Figure 1 shows a specific embodiment of a circuit configuration according to the invention. In this case, the circuit configuration shown in Figure 1 includes two series field effects Transistors AT 1 and AT 2 are arranged between the source terminal and the drain terminal. An input signal terminal E is also provided, which is connected to the first operating circuit. The gate electrode of the body ATI. The control voltage terminal R is provided correspondingly, and it is connected to the gate electrode AT2 of the second operating transistor. The resistors R1 and R2 form a voltage divider, which is configured at the control voltage -8- This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) 558867 A7 B7 V. Description of the invention (6) Between the terminal R and the gate electrode of the second operating transistor AT2. Therefore, the voltage division The device includes a first branch with a first resistor R1 and a second branch with a second resistor R2, wherein a gate electrode of the second operating transistor AT2 is connected to a voltage divider arranged in the voltage divider. The terminal between the first and second branches, and the control voltage terminal R is the second branch connected to the voltage divider. In addition, a first circuit unit is provided, which is connected to the control voltage terminal R via resistors R1 and R2, and turns on the voltage divider when the first, predetermined threshold voltage is exceeded. In the specific embodiment shown in FIG. 1, the first circuit unit provided is a first control transistor ST1, which is connected to the first resistor R 1 and the first resistor R 1 in the first branch of the voltage divider. A drain terminal of a control transistor ST1 is connected in series with a gate electrode of the first control transistor ST1 connected thereto. In addition, the first control transistor ST1 has the same threshold voltage as the second operation transistor AT2. In addition, a second circuit unit is provided, which is connected to the control voltage terminal R and disables the voltage divider when the second, predetermined threshold voltage is exceeded, wherein the second threshold voltage is higher than the first threshold voltage. In the specific embodiment shown in FIG. 1, the second circuit unit has a second control transistor ST2, which is connected in parallel with the second resistor R2 in the second branch of the voltage divider. In this example, the second control transistor ST2 is a "normally open" type p-channel transistor. In addition, a bias circuit is provided for the gate electrode of the first operating transistor AT1. In the specific embodiment shown, the bias circuit includes two field effect transistors BT1 and BT2 in series, and the gate electrodes are connected to the first and -9, respectively.-This paper standard applies to China National Standard (CNS) A4 specification (210 X 297 mm) 558867 A7 B7 V. Description of the invention (7) Gate electrode of the second operation transistor AT1 and AT2. The series field effect transistors BT1 and BT2 are connected between the source and the drain, and are connected in series with The operating transistor ATI is connected in parallel with AT2. In order to improve the gain, feedback and cross-coupling characteristics, the control voltage terminal R is additionally connected to the gate electrode of the second operating transistor AT 2 via a capacitor C k. The following details The embodiment considers that the control response always starts from the fully adjusted state in the direction of the increase, that is, in the following, the behavior is described as a function of the increase of the control voltage at the control voltage terminal R. The first control circuit Crystal ST1, with There is the same critical voltage as the second operating transistor AT2, and the voltage divider is turned on only when the critical voltage is exceeded. Then, the control electrode is supplied to the gate electrode of the second operating transistor AT2 constantly. In the meantime, the dispersion of the control on-voltage or the threshold voltage cannot be effective to any great extent. In the subsequent range, the second operating transistor AT2 is raised with the intrinsically steep part of the control path to increase the voltage. The voltage divider becomes effective and responds with the ratio R1 / (R1 + R2). Once the control voltage on the control voltage terminal R reaches the second threshold voltage, the second control transistor ST2 becomes on. This causes the second The control transistor ST2 bridges the second resistor R2, thereby invalidating the latter. The entire voltage divider also becomes ineffective accordingly, and the control voltage is again supplied to the gate voltage of the second operation transistor AT2 substantially unchanged. Therefore, compared with the traditional control, the subsequent, slowly rising part of the control path is greatly shortened. This is related to the increase in the control voltage loading, and in turn, to the occurrence of the entire system The negative feedback effect is related to the advantages. That is to say, the control threshold of the control transistor will not suddenly become effective. Figure 2 shows the corresponding increase-10- This paper size applies to the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) 558867 A7 B7 V. Description of the invention (8) The beneficial response is a function of the control voltage. Here, curve 1 shows the gain response established according to the circuit configuration of the present invention, and curve 2 shows the gain response according to the previous art. The gain response established by the circuit configuration. Figure 3 shows a second specific embodiment of the circuit configuration according to the present invention. The second specific embodiment is substantially equivalent to the first specific embodiment except for the following differences. In addition to the second control transistor ST2 connected in parallel with the second resistor R2 in the second branch of the voltage divider, the second circuit unit of the specific embodiment shown in FIG. The second voltage divider formed by the dividers R3 and R4. In this case, the second voltage divider is disposed between the gate electrode of the second control transistor ST2 and the control voltage terminal R. Therefore, it is possible to set the threshold voltage of the second circuit unit through the second voltage divider. Optionally, a further resistor Rv may be provided upstream of the second voltage divider. In the case where the source impedance is very low, the compressed phase can be extended by this resistor R v. FIG. 4 shows a further specific embodiment of the circuit configuration according to the present invention. Except for the following differences, this further specific embodiment is substantially equivalent to the second specific embodiment. In addition to the second control transistor ST2 and the second voltage divider formed by the resistors R3 and R4, the second circuit unit in the specific embodiment shown in FIG. 4 has further control transistors ST3 and Further resistor R5. As the control voltage increases, the control transistor ST3 is raised, which in turn means that the second control transistor ST2 is on. Therefore, to further control the turn-on voltage of transistor ST3, multiply it by the voltage divider ratio of the second voltage divider-11-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 558867 A7 B7 V. Description of the invention (9) The ratio R4 / (R4 + R3) determines the critical voltage of the second circuit unit. In this case, in order to keep the magnification R4 / (R3 + R4) (magnification of tolerance) small, the threshold for controlling transistor ST3 should be as high as possible. FIG. 5 shows a further specific embodiment of the circuit configuration according to the present invention. Contrary to the specific embodiment shown previously, the second circuit unit of the specific embodiment shown in FIG. 5 has a second control transistor ST2, which is in the first branch of the voltage divider, and The resistor R1 is connected in series. In this specific embodiment, the second control transistor ST2 is an n-channel transistor of the "normally on" type. As the control voltage increases, the control transistor ST3 is raised, which in turn means that the second control transistor ST2 is open. Therefore, the first branch of the first voltage divider becomes inactive, and in turn supplies a control voltage to the gate electrode G2 of the second operating transistor AT2 substantially unchanged. Once again, further control the on-voltage of transistor ST3 and multiply it by the ratio R4 / (R4 + R3) of the second voltage divider, thus determining the critical voltage of the second circuit unit. FIG. 6 shows a specific embodiment of a circuit configuration according to the present invention. Except for the following differences, this further specific embodiment is substantially equivalent to the specific embodiment shown in FIG. 5. In the case of this specific embodiment, instead of the "normally-on" type n-channel transistor, an "n-channel" transistor of "normally-off π" is used as the second control transistor ST2. In addition, the resistor R 5 in this embodiment is not directly connected to the control voltage terminal R, but is connected to a non-polar terminal. Due to the increase of the control voltage, the control transistor ST3 is raised, and it is changed to -12- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 558867 A7 B7 V. Description of the invention (1) It means that the second control transistor ST2 is open. Therefore, the first branch of the first voltage divider becomes ineffective, and instead supplies a control voltage to the gate electrode G2 of the second operation transistor AT2 substantially unchanged. For its moderate occurrence, in the first branch of the first voltage divider, a second control transistor ST2 is inserted between R1 and R2. In this case, the resistor R1 on the source of the control transistor ST2 has a high negative feedback effect, thereby avoiding a sudden transition. In order to keep the magnification ratio R4 / (R3 + R4) (enlargement of tolerance) small, the threshold for controlling transistor ST3 should be as high as possible. Although the operation of the transistor AT1 has a generally higher threshold, this method is also convenient and advantageous for controlling the transistor ST2 because of the bias circuit. Of course, it is also possible to generate higher threshold values from combination or other methods. FIG. 7 shows a further specific embodiment of the circuit configuration according to the present invention. Except for the following differences, this further specific embodiment is substantially equivalent to the specific embodiment in FIG. 6. The circuit configuration shown in FIG. 7 is different from the circuit configuration shown in FIG. 6 in that the extra voltage offset is driven in the driving of the gate voltage G 2 of the second operation transistor AT2. For example, if the operating transistor AT2 has a very low turn-on voltage, but a very high turn-on voltage is ensured in terms of component, this can be achieved by an additional transistor T. According to the circuit configuration of the present invention, based on the extended control path by means of voltage dividers R1 and R2, a control voltage divided by a ratio R1 / (R1 + R2) is supplied to the gate electrode of the second operation transistor AT2. However, this extension is only expected to be related to the steep part of the control path. Therefore, the first and second circuit units are provided so that the voltage to be turned on is in the correct position, and obviously -13- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)