TW558779B - Method for bonding conductive members in semiconductor package - Google Patents

Method for bonding conductive members in semiconductor package Download PDF

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Publication number
TW558779B
TW558779B TW091110203A TW91110203A TW558779B TW 558779 B TW558779 B TW 558779B TW 091110203 A TW091110203 A TW 091110203A TW 91110203 A TW91110203 A TW 91110203A TW 558779 B TW558779 B TW 558779B
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Taiwan
Prior art keywords
area
power supply
wafer
ground
item
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TW091110203A
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Chinese (zh)
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Chien-Ping Huang
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Siliconware Precision Industries Co Ltd
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Priority to TW091110203A priority Critical patent/TW558779B/en
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Publication of TW558779B publication Critical patent/TW558779B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48233—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a potential ring of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A method for bonding conductive members in a semiconductor package is proposed. First, a chip carrier mounted with a chip is prepared, and defined with a power plate attach area and a ground plate attach area without interfering with chip-bonding for the chip carrier. The chip is formed with a power plane corresponding in position to the power plate attach area, and a ground plane corresponding in position to the ground plate attach area. Then, a plurality of metal bumps are bonded to the power plane and ground plane of the chip, and to the power plate attach area and ground plate attach area of the chip carrier. Subsequently, a plurality of conductive members (such as a power plate and a ground plate) are prepared, with a metal layer being formed respectively on the conductive members at positions corresponding to the power plane, ground plane, power plate attach area and ground plate attach area. Finally, a thermo-compression or solder-reflowing process is performed for bonding the metal layers to the metal bumps by forming of eutectic junction, so as to allow the conductive members to be electrically coupled to the chip and the chip carrier. As the eutectic junction is low in electrical resistance without adversely affecting velocity of electrical current, thereby preventing electrical failure from occurrence. Moreover, forming of the eutectic junction, instead of using a conductive adhesive, would more effectively reduce delamination and help increase bondability between the conductive members and the chip or chip carrier.

Description

558779 五、發明說明α) 【發明領域】： 本發明係關於一種導電元件銲 :源供應元件及接地元件電性銲固於半導體提供 接方法。 丁守肢打裝件内之銲 【先前技藝說明】： 球柵陣列（Ball Grid Arrw dm、 、 特徵係於基板底面上植佈多數以陣列方式：：：：J件之 於皁位面積内容納較多之輪入/龄 鈐球’以558779 V. Description of the invention α) [Field of the invention]: The present invention relates to a method for welding a conductive element: a source supply element and a ground element which are electrically welded to a semiconductor. Welding in Ding Shoulim's mounting parts [Previous description of technology]: Ball grid array (Ball Grid Arrw dm,, features are mostly planted on the bottom surface of the substrate in an array mode: ::: J pieces are contained in the soap area area More rounds / age ball

Connection)，而得符合具高 ^ ^ 坐道础门在度電子疋件及電子電路之 +導體曰曰片所f，故現已成為封 ： 板上之多數銲球係用以提供半導體封裝件電性導；；：； =路板等外部裝置上，為使封裝件整合於外 ^ =較，之電性品質’必須提供封裝件接地⑺。 電 2 p〇wer\及訊號（Signal)傳遞等功能。因此，在封 裝件之結構设計上，基板亦須配置有相對應之接地元件、 電源供應70件以及訊號傳輸元件以供銲球電性連通，俾令 封裝sa片運作時產生預期之電性效果。 鑒此美國專利第5, 545, 923號遂揭露於基板上設置 有接地環（Ground Ring)、電源環（p〇wer Ring)及訊 號銲線墊（Signal Finger )之設計。如第4圖及第5圖所 不，該半導體結構3係於一基板30第一表面3〇〇之晶片接置 區302外區域上佈設一電源環35、_接地環36以及多數訊 號銲線墊305;並另安置一配有多數訊號銲墊312、電源銲 墊313及接地銲墊314之半導體晶片31至該晶片接置區302Connection), and it has to meet the high-conductivity requirements of electronic components and electronic circuits on the basis of high-level gates, so it is now sealed: Most solder balls on the board are used to provide semiconductor packages Electrical conductivity;;: = external components such as circuit boards, in order to integrate the package with the external ^ = comparison, the electrical quality 'must provide the package ground ⑺. Electricity 2 p〇wer \ and signal (Signal) transmission and other functions. Therefore, in the structural design of the package, the substrate must also be equipped with corresponding grounding components, 70 power supplies and signal transmission components for the electrical connection of the solder balls, so that the expected electrical effect will be produced when the package sa chip operates. . In view of this, U.S. Patent No. 5,545,923 discloses a design provided with a ground ring, a power ring, and a signal finger pad on the substrate. As shown in FIG. 4 and FIG. 5, the semiconductor structure 3 is provided with a power ring 35, a ground ring 36 and most signal bonding wires on an area outside the wafer receiving area 302 of the first surface 300 of the substrate 30. Pad 305; and another semiconductor wafer 31 equipped with a plurality of signal pads 312, power pads 313, and ground pads 314 to the wafer receiving area 302

第7頁 558779 五、發明說明（2) 上’以利銲線作業完成後形成多數訊號線3 0 6、電源線3 5 6 以及接地線3 6 6。其中，訊號線3 0 6係導電連接該晶片3 1上 各訊號銲墊312至基板30上之該等訊號銲線墊305，而電源 線3 5 6係連接該等電源銲墊3 i 3至該電源環3 5上，且接地線 366則電性連接該等接地銲墊314至該接地環36上。復於後 續製程中以多數銲球39植接到基板30之第二表面3〇1上， 7使母一鋒球39藉導電跡線307與其所連接之電源環35、 接地環3 6以及訊號銲線墊3 〇 5電性通連，俾供封裝件與外 部裝置導電銲結後，半導體結構可藉該電源環35及接地 3 6維持晶片3 1運作之電性品質。 、，然而，上揭之半導體封裝件於設計上具有諸多缺點。 百先，電源環及接地環之設置佔據晶片周圍之基板面積， 故而限制基板表面之線路佈局，使封裝件尺寸無法有效 減而不符合封裝件輕薄短小之發展潮流。再者，為減少、曰曰 片運作時之雜訊產生，基板表面上須設置多 UaPacitor)安置之去輕銲塾（Dec〇upUng pad電）谷，器 電源環、接地環之增設限制住基板空間而使去耦銲墊之 局更形困難，且電源線、接地線及訊號線係以多層次 =式佈設於基板表面亦須精確控制不同層次間之佈線弧、言 (Loop Height )，造成打線困難度倍增。 门 是以，業者再開發出一無須設置電源環及接地環， 可降低佈線複雜性之球栅陣列半導體封裝件。如第6圖 示，此封裝件3亦同於上述封裝結構於—基板3〇上預置_ 晶片接置區302，且該晶片接置區3〇2周圍亦佈設有多數訊Page 7 558779 V. Description of the invention (2) After the completion of the welding operation, most signal lines 3 0 6, power lines 3 5 6 and ground lines 3 6 6 are formed. Among them, the signal line 3 0 6 is conductively connected to the signal pads 312 on the chip 31 to the signal pads 305 on the substrate 30, and the power line 3 5 6 is connected to the power pads 3 i 3 to The power ring 35 is connected, and the ground wire 366 is electrically connected to the ground pads 314 to the ground ring 36. In the subsequent process, the majority of the solder balls 39 are planted on the second surface 3101 of the substrate 30, and the female-one ball 39 is connected to the power supply ring 35, the ground ring 36, and the signal by the conductive trace 307 The bonding pads 305 are electrically connected, and after the package and the external device are conductively bonded, the semiconductor structure can maintain the electrical quality of the operation of the chip 31 by the power ring 35 and the ground 36. However, the semiconductor package disclosed above has many disadvantages in design. Baixian, the arrangement of the power supply ring and the grounding ring occupy the area of the substrate around the chip, so the layout of the circuit on the surface of the substrate is restricted, so that the size of the package cannot be effectively reduced, and it does not meet the trend of thin, light and short packages. In addition, in order to reduce the noise generated during the film operation, multiple UaPacitors must be set on the surface of the substrate. DecOupUng pad valleys are placed on the surface of the substrate. The addition of a power supply ring and a grounding ring restricts the substrate. Space makes the decoupling pads even more difficult, and the power lines, ground lines, and signal lines are laid on the surface of the substrate in a multi-level = manner, and the wiring arcs and loop heights between different levels must be accurately controlled, causing Difficulty in wiring. As a result, the industry has developed a ball grid array semiconductor package that eliminates the need for power and ground rings and reduces wiring complexity. As shown in FIG. 6, this package 3 is also preset on the substrate _ the wafer receiving area 302 in the same manner as the above package structure, and a majority of information is also arranged around the wafer receiving area 302.

558779 五、發明說明（3) 號銲線墊3 0 5，其特點在於該等訊號銲線墊3 〇 5以外之兩側 基板30上分別增設一電源件接置區303及一接地件接置區 304，且安置於該晶片接置區302上之半導體晶片31，其作 用表面310上未設置銲墊之區域亦另形成有一電源區315及 一接地區3 1 6，使晶片3 1上之電源區3 1 5與基板3 0上之電源 件接置區303 ;以及晶片31上之接地區316與基板30上之接 地件接置區3 0 4各配置於相同側。於是，當一電源件3 &之 兩端分別黏著於該電源區3 1 5及該電源件接置區3 0 3，且一 接地件36之兩端亦分別黏妥於該接地區3 1 6及該接地件接 置區304後，兩撐設於晶片31上方且共平面之電源件35及 接地件3 6可以免除電源線及接地線佈設，甚至提供晶片3 ^ 遮蔽效果（Shielding)，使晶片31免受外界電磁干擾 (Electromagnetic Interference，EMI)而有助於提昇 半導體封裝件3之性能。 然而，該電源件3 5及接地件3 6與晶片3 1作用表面3 1 〇 上的電源區315/接地區316以及基板30上之電源件接置區 303/接地件接置區304係仰賴一導電膠37提供黏著，而該 導電膠37因含有如聚亞醯胺（Poiyimide)等高電阻係數 及高熱膨脹係數材質構成之介質，遂與金屬材質所製之電 源件35或接地件36相較下，該導電膠37之電阻係數明顯高 出電源件35或接地件36甚多，造成電流穿越導電膠37的速 度難同穿越電源件35或接地件36般快速而引發電性衰退。 此外，由於電源件3 5兩端與電源區31 5及電源件接置區3 〇 3 之黏著方式以及接地件36兩端與接地區316及接地件接置558779 V. Description of the invention (3) No. 3 wire bonding pad 3 0 5 is characterized in that a power supply device receiving area 303 and a grounding device connection are respectively added to the substrates 30 on both sides other than the signal wire bonding pads 305. Region 304, and the semiconductor wafer 31 disposed on the wafer receiving region 302, and a region on the active surface 310 where no pad is provided is also formed with a power source region 315 and a connecting region 3 1 6 so that the wafer 31 The power supply area 3 1 5 is connected to the power device connection area 303 on the substrate 30; and the connection area 316 on the wafer 31 and the ground device connection area 3 4 on the substrate 30 are each disposed on the same side. Therefore, when both ends of a power supply component 3 & are respectively adhered to the power supply area 3 1 5 and the power component connection area 3 0 3, and both ends of a grounding component 36 are also adhered to the connection area 3 1 respectively. 6 and the grounding member connection area 304, the two coplanar power supply parts 35 and the grounding part 3 supported above the chip 31 can be exempted from the layout of the power and ground wires, and even provide the chip 3 ^ Shielding, Protecting the chip 31 from external electromagnetic interference (EMI) and helping to improve the performance of the semiconductor package 3. However, the power supply part 35 and the grounding part 36 are connected to the power supply area 315 / connection area 316 on the active surface 3 10 of the wafer 31 and the power supply connection area 303 / ground connection area 304 on the substrate 30. A conductive adhesive 37 provides adhesion, and the conductive adhesive 37 is in phase with the power source component 35 or the grounding component 36 made of metal material because it contains a medium composed of a material with high electrical resistivity and high coefficient of thermal expansion such as polyimide. In comparison, the resistivity of the conductive adhesive 37 is significantly higher than that of the power supply component 35 or the grounding component 36, which makes it difficult for the current to pass through the conductive adhesive 37 as fast as it passes through the power supply component 35 or the grounding component 36, causing electrical degradation. In addition, due to the adhesion of the two ends of the power supply part 35 to the power supply area 315 and the power supply connection area 303 and the two ends of the grounding piece 36 to the connection area 316 and the grounding part

第9頁 558779 五、發明說明（4) 區304之黏著方式均係於電源件35及接地件36之支撐部 350,360和延伸部352,362上塗佈導電膠37後，再貼合至晶 片31之電源區315/接地區316以及該基板3〇之電源件接置 區303/接地件接置區3Q4上；因此，金屬材質之電源件π 及^地件36與導電膠37間往往因熱膨脹係數不同而於溫度 循壞下產生過大熱應力，致使電源件3 5 /接地件3 6盥晶η 31或基板30間發生脫爲,η 1 t ^ 私王脫層（Delamination)而損及封奘杜q 之電性品質。 』衣汗d 因此，如何有效解決上 生產良率，進而開發增進一 及基板間銲接信賴性之導電 解決之課題。 【發明概述】： 述缺失，改善半導體封裝件之 電源件/接地件與半導體晶片 元件銲接方法，實為今日必須 •本發=之主要目的在提供一種導電元件之銲接方法， 運用共金鲜接方式將導電元件電性銲結至半導體晶片及 板上減小電流穿越導電元件與晶片、基板之接合部ς 之電性阻力’以避免電性衰退發生。 一種導電元件之銲接方法， 件電性連結至半導體晶片及 晶片、基板接觸面之熱應 本發明之另一目的在提供 毋須使用導電膠即可將導電元 基板上，俾減少該導電元件與 力，以避免脫層產生。 本發明之再一目的在提供一種導電元件之銲接方法， 以共金接合方式取代導電膠以銲連導電元件至半導體晶 及基板上，俾以增強導電元件與晶片、基板間之銲接^賴Page 9 558779 V. Description of the invention (4) The bonding methods of the area 304 are all applied to the support parts 350, 360 and extension parts 352, 362 of the power supply part 35 and the grounding part 36, and then the conductive adhesive 37 is applied to the power supply of the chip 31 Area 315 / connection area 316 and the power supply connection area 303 / ground connection area 3Q4 of the substrate 30; therefore, the thermal expansion coefficients between the power supply components π and ^ ground components 36 made of metal materials and the conductive adhesive 37 are often different. Excessive thermal stress is generated under the temperature cycling, which causes the power supply part 3 5 / grounding part 36 to be separated between the η 31 or the substrate 30, η 1 t ^ Delamination and damage to the seal q Electrical quality. "Yihan d. Therefore, how to effectively solve the production yield, and then develop a conductive solution to improve the reliability of soldering between substrates. [Summary of the invention]: The lack of the above descriptions, improving the welding method of power supply / grounding components of semiconductor packages and semiconductor wafer components, is a must today. The main purpose of this invention = is to provide a welding method of conductive components, using common gold fresh connection The method electrically bonds the conductive elements to the semiconductor wafer and the board to reduce the electrical resistance of the current passing through the joints of the conductive elements, the wafer and the substrate, to avoid electrical degradation. A method for soldering conductive elements, the heat of which is electrically connected to the semiconductor wafer and the contact surfaces of the wafer and the substrate. Another object of the present invention is to provide a conductive element substrate without using a conductive adhesive, thereby reducing the conductive element and force. To avoid delamination. Yet another object of the present invention is to provide a method for welding conductive elements, which replaces the conductive adhesive with a gold bonding method to connect the conductive elements to the semiconductor crystal and the substrate, thereby enhancing the welding between the conductive elements, the wafer, and the substrate.

16650.ptd 第10頁 55877916650.ptd Page 10 558779

五、發明說明（5) 性。 基於上述及其他目的，本發明之導電元件銲接方法係 包栝以下步驟··首先預製一晶片承載件如基板，於其一表 面上預先定義有一晶片接置區，且該晶片接置區外並形成 有至少一電源件接置區及接地件接置區；備妥一半導體晶 片’該晶片之電路面上形成有至少一電源區及接地區，並 將該晶片載接至該基板之晶片接置區上，以使該電源區對 應至該電源件接置區，並使該接地區對應至該接地件接置 區，之後，植設複數個金屬銲塊至該晶片之電源區及接地 區，以及該基板之電源件接置區與接地件接置區上；接 著，擇一電源件及一接地件，並分別於該電源件及接地件 對應於晶片電源區、晶片接地區、基板電源件接置區及基 板接地件接置區之部位上敷設至少一金屬層（即錫鉛合金 或錫製之金屬預鍍層）：最後，採熱壓或回銲方法將該金 屬層與其對應之金屬銲塊接合而形成一共金接合部，俾使 該電源件及接地件銲固並電性連接於該晶片與基板上，即 完成本發明之導電元件銲接方法。 本發明導電元件之銲接方法之特點，係摒除傳統藉導 電朦將電源件/接地件黏著於晶片及基板上之方式，改以 共金接合技術而使導電元件（即電源件/接地件）銲固至 晶片之電源區/接地區以及基板之電源件接置區/接地件接 置區上。由於晶片之電源區及接地區，以及基板之電源件 接置區與接地件接置區上形成有複數個具突出端（Stud) 或其他態樣之金屬銲塊，因此電源件/接地件之金屬層經5. Description of the invention (5). Based on the above and other objectives, the method for soldering conductive elements of the present invention includes the following steps: First, a wafer carrier such as a substrate is prefabricated, and a wafer receiving area is defined in advance on one surface, and the wafer receiving area is outside the wafer receiving area and At least one power supply connection area and ground connection area are formed; a semiconductor wafer is prepared, and at least one power supply area and connection area is formed on the circuit surface of the wafer, and the wafer is connected to the wafer connection of the substrate. Place the area so that the power supply area corresponds to the power supply connection area, and the connection area corresponds to the ground connection area. After that, a plurality of metal solder bumps are planted to the power supply area and connection area of the chip. , And the power supply component connection area and the grounding component connection area of the substrate; then, select a power supply component and a grounding component, and correspond to the chip power supply area, the chip connection area, and the substrate power supply respectively on the power supply component and the grounding component. At least one metal layer (that is, a tin-lead alloy or a tin metal pre-plated layer) is laid on the part receiving area and the substrate grounding part receiving area: Finally, the metal layer is corresponding to it by hot pressing or reflow method Metal bonding pads formed a total gold bonding to enabling the welding power supply unit and the ground fixing member and electrically connected to the substrate on the wafer, i.e., the conductive elements to complete the welding process of the present invention. The characteristic of the welding method of the conductive element of the present invention is to eliminate the traditional method of adhering the power supply component / grounding component to the wafer and the substrate by conducting conductivity, and to use a common gold bonding technology to weld the conductive component (ie, the power component / grounding component). It is fixed to the power supply area / connection area of the chip and the power supply connection area / ground connection area of the substrate. Because the power supply area and connection area of the chip, and the power supply area and grounding area of the substrate are formed with a plurality of metal solder bumps with studs or other shapes, Metal layer warp

16650.ptd 第11頁 558779 五、發明說明（6) 熱壓（Thermocompression)或回銲（Solder Reflow)方 式處理時，該金屬層會於高溫環境下潤濕（Wetting )而 與熔融態之質軟金屬銲塊間形成一共價介面金屬共化物 (Intermetallic Compound)之共金層致使電源件或接地 件等導電元件可直接電性連接至晶片及基板而無須再施用 任何導電膠材。該導電元件與晶片/基板間形成之共價合 金部具有甚小之電性阻抗值，因此不會影響電流行進速度 而能防止電性衰弱發生，而共金接合方法亦可提供較強之 銲接牢固性，而使該導電元件與晶片及基板形成穩固地接 合關係。再而，導電元件之接合無須使用導電膠，故電源 件或接地件與晶片/基板之接合部位不會因導電膠高熱膨 脹係數的特性而產生過大熱應力，同時金屬銲塊選用突出 端設計亦可在未影響導電功能之情況下，進一步縮減導電 元件與金屬銲塊間之接觸面積，使脫層現象發生可能性大 為減低’繼而增進共金接合部之銲接信賴性。 【發明詳細說明1 : 第1圖所示者係本發明導電元件銲接方法之第一實施 例之整體流程步驟；步驟18至ld所含元件標號悉參照下揭 實施例所含之圖式表示之。如步驟13及第2A圖所示，先備 一晶片承載件如基板10，該基板10上黏著有至少一半導體 晶片11，並施予打線，其中，該半導體晶片i J上各形成有 至少一電源區11 5及接地區11 6，同時該晶片承載件i 〇上未 影響銲線分布之區域上，亦界定有一個以上與該電源區16650.ptd Page 11 558779 V. Description of the invention (6) When processed by Thermocompression or Solder Reflow, the metal layer will be wetted in a high temperature environment and soft with the molten state. A co-gold layer of a covalent interface metal compound (Intermetallic Compound) is formed between the metal solder blocks, so that conductive components such as power components or grounding components can be directly and electrically connected to the chip and the substrate without applying any conductive adhesive. The covalent alloy portion formed between the conductive element and the wafer / substrate has a very small electrical resistance value, so it does not affect the current traveling speed and can prevent electrical weakness from occurring. The co-gold bonding method can also provide stronger welding Fastness, so that the conductive element forms a stable bonding relationship with the wafer and the substrate. Furthermore, conductive adhesive is not required for the bonding of conductive components, so the joint between the power supply or grounding piece and the wafer / substrate will not generate excessive thermal stress due to the high thermal expansion coefficient of the conductive adhesive. At the same time, the protruding end design of the metal solder bump is also selected. It can further reduce the contact area between the conductive element and the metal pad without affecting the conductive function, so that the possibility of delamination is greatly reduced, and the soldering reliability of the common gold joint is improved. [Detailed description of the invention 1: The one shown in FIG. 1 is the overall process steps of the first embodiment of the welding method of the conductive element of the present invention; the component numbers included in steps 18 to 1d are described with reference to the drawings included in the embodiment disclosed below. . As shown in step 13 and FIG. 2A, a wafer carrier such as a substrate 10 is prepared, and at least one semiconductor wafer 11 is adhered to the substrate 10, and wire bonding is performed, wherein each of the semiconductor wafers i J is formed with at least one The power supply area 115 and the connection area 11 16 are defined at the same time on the wafer carrier i 0 which does not affect the distribution of the bonding wires.

558779 五、發明說明（7) 11 5對應之電源件接置區1 〇 3以及與該接地區11 6對應之接 地件接置區104;之後，如步驟ib及第2B圖所示和步驟ic 及第2C圖所示，於該晶片11之電源區115及接地區116，以 及該基板1 0之電源件接置區1 〇 3及接地件接置區1 〇 4上分別 形成複數個金屬凸塊1 4 ;而後，擇一電源件1 5及一接地件 I 6 ’令該電源件1 5及接地件1 6相對應於該晶片11電源區 II 5、晶片11接地區11 6、基板1 〇電源件接置區丨03、基板 10接地件接置區104之區域上鍍敷一金屬預鍍層17;最後 施以步驟Id如第2D圖所示，令該電源件15及接地件16之兩 端熱壓接合至該晶片11及該基板10上，以供各金屬預鍍層 17與相對應之金屬凸塊14形成一共金接合部，即完成本^ 明全部製程。以下臻以第2A至2E圖再詳細揭露第一實施例 之各階段步驟。 如第2A圖所示，首先備妥一晶片承載件（同以下基板 10所示）’適用於本發明銲接方法之晶片承載件得為一基 板或導線架，唯因基板具有較高之佈局靈活性，遂下揭實 施例内容皆採基板為例例釋之。該基板丨〇具有一第一表面 100及一相對之第二表面1〇1，於該基板1〇之第一表面1〇〇 上預先定義有一晶片接置區102，且該晶片接置區ι〇2外不 影響銲線作業之區域上並形成有至少一電源件接置區丨〇3 及一接地件接置區1〇4以分置於該基板1〇之兩側；基板1〇 之第一表面100上形成有多數之銲線墊105 ( Fingei^s )， 俾令送達該銲線墊105之電子訊號經貫穿基板1〇之導電跡 線（未圖式）傳遞至基板1〇第二表面1〇1之多數銲球塾558779 V. Description of the invention (7) 11 5 corresponds to the power supply connection area 1 03 and the ground connection area 104 corresponding to the connection area 11 6; after that, as shown in steps ib and 2B and step ic As shown in FIG. 2C, a plurality of metal bumps are formed on the power supply region 115 and the connection region 116 of the chip 11, and the power supply connection region 10 and ground connection region 104 of the substrate 10 respectively. Block 1 4; Then, select a power supply part 15 and a grounding part I 6 'so that the power supply part 15 and the grounding part 16 correspond to the chip 11 power supply area II 5, the chip 11 connection area 11 6, and the substrate 1 〇 Power supply connection area 丨 03, the base plate 10 ground connection area 104 is plated with a metal pre-plating layer 17; finally, the step Id is shown in Figure 2D, so that the power supply 15 and ground 16 Both ends are hot-press bonded to the wafer 11 and the substrate 10, so that each metal pre-plated layer 17 and the corresponding metal bump 14 form a common gold bonding portion, and the entire process of the present invention is completed. The steps of the first embodiment will be disclosed in detail below with reference to FIGS. 2A to 2E. As shown in FIG. 2A, first prepare a wafer carrier (same as the following substrate 10). The wafer carrier suitable for the soldering method of the present invention may be a substrate or a lead frame, because the substrate has a high layout flexibility. Therefore, the contents of the following embodiments are illustrated by using a substrate as an example. The substrate has a first surface 100 and an opposite second surface 101. A wafer receiving area 102 is defined in advance on the first surface 100 of the substrate 10, and the wafer receiving area 102 〇2 outside the area that does not affect the bonding wire operation and formed at least one power supply connection area 丨 03 and a ground connection area 104 to be placed on both sides of the substrate 10; substrate 10 A plurality of bonding pads 105 (Fingei ^ s) are formed on the first surface 100, and the electronic signals sent to the bonding pads 105 are transmitted to the substrate 10 through conductive traces (not shown) passing through the substrate 10. The majority of the solder balls on the two surfaces 101

第13頁 558779 五、發明說明（8) · (未圖式）（Ball Pads)上。之後，預備至少一半導體 晶片11，該晶片11具有一作用表面11 〇 (即佈設有多數電 子電路與電子元件之表面）與一非作用表面111，於該晶 片10之作用表面110上周圍區域佈設有多數訊號銲墊112 (Signal Pads)、電源銲墊 113 (Power Pads)及接地銲 m 墊114 (Ground Pads)，且該作用表面110未設有銲墊之 區域上亦形成有一電源區1 1 5 ( Power Plane )及一接地區 116 (Ground Plane)，用以分別電性整合（Consolidate )該等電源銲墊1 1 3及接地銲墊11 4，以構成該晶片1 1對外 之電源供應及接地集中地；以一如銀膠或聚亞醯胺膠片等 參 膠黏層1 2將該晶片1 1之非作用表面1 1 1黏著至該基板1 〇晶 片接置£102上’其中’該晶片11之電源區115係朝向該基 板1 0之電源件接置區1 〇 3，而該晶片11之接地區11 6則朝向 該基板1 0之接地件接置區1 〇 4，以使提供電源功能與接地 功能之元件得分別整合於基板1 〇兩側。復以慣用之銲線技 術將該半導體晶片11電性連接至基板1〇第一表面1〇〇上， 即可運用本發明之銲接方法安置導電元件。 如第2B圖所示，應用傳統銲線方法（Wire B〇nding ) 令一打線機13 (Wire Bonder)將金質鲜料（Gold Wire) 點鲜壓接至該晶片1丨之電源區n 5及接地區π 6與該基板丨〇 φ 之電源件接置區103及接地件接置區104上俾形成複數個金 ^凸塊14(stud bump)，唯金球點銲至上述部位後係以拉 高方式收尾，因此每一金質凸塊14倶形成有一向上凸起之 · 突出端140。Page 13 558779 V. Description of the invention (8) · (not shown) (Ball Pads). Thereafter, at least one semiconductor wafer 11 is prepared. The wafer 11 has an active surface 11 0 (that is, a surface on which most electronic circuits and electronic components are arranged) and a non-active surface 111, and is arranged on the surrounding area on the active surface 110 of the wafer 10. There are many signal pads 112 (Signal Pads), power pads 113 (Power Pads), and ground pads 114 (Ground Pads), and a power supply area is also formed on the active surface 110 where no pads are provided 1 1 5 (Power Plane) and a ground area 116 (Ground Plane), which are used to electrically integrate (Consolidate) the power pads 1 1 3 and ground pads 11 4 respectively to form the chip 1 1 external power supply and The ground is concentrated; a non-active surface 1 1 1 of the wafer 1 1 is adhered to the substrate with a reference adhesive layer 1 2 such as silver glue or polyurethane film. The power supply region 115 of the wafer 11 is oriented toward the power component receiving area 1 03 of the substrate 10, and the wafer connection area 116 is directed toward the ground component receiving area 1 04 of the substrate 10 so that the supply is provided. Power supply function and ground function components must be integrated on the substrate 1 Both sides. The semiconductor wafer 11 is electrically connected to the first surface 100 of the substrate 100 by a conventional bonding wire technology, and then the conductive component can be set by using the soldering method of the present invention. As shown in FIG. 2B, the conventional wire bonding method (Wire Bonding) is used to make a wire bonder 13 (Gold Wire) spot crimp to the power supply area n 5 of the chip 1 丨A plurality of gold bumps 14 (stud bumps) are formed on the connection area π 6 and the power device connection area 103 and ground connection area 104 of the substrate 丨 φ. It is closed in a pull-up manner, so each gold bump 14 倶 is formed with a protruding end 140 protruding upward.

16650.ptd 第14頁 558779 五、發明說明（9) ^而，如^2C圖所示，選擇一電源件15 (p〇wer a e 一妾地件Η ( Ground Plate )作為提供晶片u ^ ^ ^ μ .X粑之導電兀件，該電源件1 5及接地件1 6 ._ 質製成，每一電源件1 5及接地件1 6各包含 有一體成型之一支撐部150, 160，一平坦部151，161及一延 =部1 52, 1 62，使該平坦部151，161藉該支撐部15〇, 16〇之 支持而架撐於半導體晶片11上方，而藉延伸部1 52, 1 62與 基板10相接。其中，該電源件15支撐部ι5〇對應於晶片η 電源區11 5上之部位係定義作一第一電源件端面丨53，該電 源，15延伸部152對應於基板10上電源件接置區1〇3之部位 係定義作一第二電源件端面丨5 4 ;同理，該接地件丨6支撐 部1 6 0對應於晶片1丨接地區η 6上之部位係定義為一第一接 地件端面1 6 3 ’而該接地件1 6延伸部1 6 2對應於基板1 〇上接 地件接置區1 0 4之部位則定義為一第二接地件端面丨6 4。於 該第一電源件端面1 5 3、第二電源件端面1 5 4、第一接地件 端面163及第一接地件端面164上各鍍敷一錫錯合金或錫材 質構成之金屬預鍍層1 7，藉以引導後續熱壓合製程中潤濕 (Wetting )之產生。 接著’如第2D圖所示，將載有該電源件15及接地件16 之基板10置入一熱壓治具18内實施熱壓合製程。該熱壓治 具18係由一上模180及一得與該上模180合模之下模（未圖 式）所構成，該上模1 8 0具有一對應於該晶片11電源區11 5 及晶片11接地區11 6上方並能往復移動之壓塊1 8 0 a，以及 兩分別對應於該基板1 0之電源件接置區1 0 3、基板1 0之接16650.ptd Page 14 558779 V. Description of the invention (9) ^ And, as shown in the ^ 2C diagram, a power source 15 (p〇wer ae, ground plate) (Ground Plate) is selected as the chip ^ ^ ^ μ.X 粑 conductive parts, the power supply parts 15 and grounding parts 16 ._ are made of high quality, each power supply part 15 and grounding parts 16 each include an integrally formed support part 150, 160, one The flat portions 151, 161 and one extension = portions 1 52, 1 62, so that the flat portions 151, 161 are supported above the semiconductor wafer 11 by the support of the support portions 15 and 16 and the extension portions 1 52, 1 62 is connected to the substrate 10. Among them, the supporting part 15 of the power source 15 corresponding to the chip η power source area 115 is defined as an end face of the first power source 53, and the power source 15 extension 152 corresponds to The position of the power element receiving area 103 on the substrate 10 is defined as an end face of the second power element 5 4; similarly, the grounding element 6 support portion 1 6 0 corresponds to the chip 1 1 of the contact area η 6 The part is defined as a first grounding member end surface 16 3 ′, and the grounding member 16 extending portion 16 2 corresponds to the grounding member receiving area 1 0 4 on the substrate 10 is defined as a first Two grounding element end surfaces 丨 6 4. Each of the first power source end surface 1 5 3, the second power source end surface 1 5 4, the first grounding element end surface 163 and the first grounding element end surface 164 is plated with a tin alloy or A metal pre-plated layer 17 made of tin material is used to guide the generation of wetting in the subsequent hot-pressing process. Then, 'as shown in FIG. 2D, the substrate 10 carrying the power supply 15 and the ground 16 is placed. A hot-pressing process is carried out in a hot-pressing fixture 18. The hot-pressing fixture 18 is composed of an upper mold 180 and a lower mold (not shown) for closing the upper mold 180, and the upper mold 1 8 0 has a pressing block 1 8 0 a corresponding to the power supply area 11 5 of the chip 11 and the contact area 11 6 of the chip 11 and can be moved back and forth, and two power supply contact areas 1 corresponding to the substrate 10 respectively. 0 3.Board connection 1 0

16650.ptd 第 15 頁 558779 五、發明說明（ίο) 地件接置區104上方之壓腳18〇b ;遂待基板1〇移入治具18 後’、/台具18提供高溫環境並令該壓塊18〇a及壓腳18〇b向下 施壓’導致電源件1 5之第一電源件端面丨5 3、第二電源件 端面154上各金屬預鍍層17潤濕（Wetting)而與相對應之 晶片11電源區115及基板1〇電源件接置區1〇3上之金質凸塊 1 4而形成一共金接合部1 9 ;同理，該接地件丨6之第一接地 件端面163、第二接地件端面164上各金屬預鍍層17亦會與 相對應之晶片1 1接地區1 1 6及基板1 〇之接地件接置區1 〇4上 各金質凸塊14產生共金接合。 是以，如第2 E圖所示，經熱壓合完成之電源件1 5及接 地件1 6以共金接合方式分別電性銲結於半導體晶片1 1以及 基板10上；由於共金接合部19材質之電性阻抗值甚小，因 此電子訊號自導電元件（即電源件1 5及接地件1 6 )傳遞到該 共金接合部19時不會影響電流進行速度而能免於電性衰弱 之發生，且採共金接合亦能提供較佳之銲固接合性，致使 該電源件1 5及接地件1 6與晶片11及基板1 〇間形成穩固之銲 結，甚至突出端1 4 0之形成亦能減少金質凸塊1 4與電源件 1 5或接地件1 6間之接觸面積’使脫層發生之疑慮大幅降 低。 篱二實施例： 第3A至3D圖所示者係本發明導電元件銲接方法之第〆 實施例之製程步驟。如圖所示，該實施例之步驟大致同於 前述第一實施例，亦係將一載有至少一半導體晶片2 1之基 板2 0施以打線，再以本發明之導電元件銲接方法進行一電16650.ptd Page 15 558779 V. Description of the invention (ίο) The presser foot 18〇b above the ground part receiving area 104; after the substrate 10 is moved into the fixture 18, the platform 18 provides a high temperature environment and makes the The pressing of the pressing block 18〇a and the pressing foot 18〇b downwardly causes the end face of the first power supply member 15 of the power supply member 15 and the metal pre-plated layer 17 on the end face 154 of the second power supply member to wet and cause wetting. The corresponding gold bumps 14 on the power supply region 115 of the wafer 11 and the power supply connection region 10 of the substrate 10 form a corresponding gold joint 19; similarly, the first grounding element of the grounding element 6 Each metal pre-plated layer 17 on the end surface 163 and the second grounding end surface 164 will also be generated with each of the gold bumps 14 on the grounding piece receiving area 1 04 of the corresponding wafer 11 1 contact area 1 16 and the substrate 10 Common gold bonding. Therefore, as shown in FIG. 2E, the power supply parts 15 and the ground parts 16 that have been thermocompression-bonded are electrically bonded to the semiconductor wafer 11 and the substrate 10 by a common gold bonding method; The electrical impedance value of the material of the part 19 is very small, so when the electronic signal is transmitted from the conductive element (ie, the power part 15 and the ground part 16) to the common gold joint part 19, it will not affect the speed of the current and can be avoided from electrical properties. The occurrence of weakness, and the use of co-gold bonding can also provide better soldering and bonding, so that the power supply 15 and ground 16 and the wafer 11 and the substrate 10 formed a stable solder joint, even protruding end 1 4 0 The formation can also reduce the contact area between the gold bumps 14 and the power supply parts 15 or the grounding parts 16 and greatly reduce the doubt of the occurrence of delamination. Second embodiment: The processes shown in Figures 3A to 3D are the process steps of the second embodiment of the method for welding a conductive element according to the present invention. As shown in the figure, the steps of this embodiment are substantially the same as the foregoing first embodiment, and a substrate 20 carrying at least one semiconductor wafer 21 is wire-bonded, and then a conductive component welding method of the present invention is used to perform a Electricity

16650.ptd 第16頁 558779 五、發明說明（11) 源件2 5及一接地件2 6之銲接作業；惟第二實施例提供之銲 接方法較前實施例不同者，係在該晶片2 1之電源區2 1 5、 晶片21之接地區216以及基板20之電源件接置區203和基板 2 0之接地件接置區2 0 4上，以習用之銲塊製程取代金球點 銲技術而植設複數個錫銲凸塊24 (Solder Bump);並且 為配合該等錫銲凸塊24之使用，如第3C及3D圖所示，該電 源件2 5之第一電源件端面2 5 3、第二電源件端面2 5 4，以及 該接地件26之第一接地件端面263與第二接地件端面264上 均形成有一體成型之至少一凸部2 5 5, 265，以於各凸部 2 5 5,2 65上+預鍍一錫鉛合金或錫層27後，送入烘爐（〇ven )内施予鬲/jnL回銲作業。同於前述第一實施例，回輝提供 ::::會導致凸部255 265上之金屬預鍍層27潤濕而與、 :端面2人53之錫笛銲凸塊24產生共金接合；此外’該第-電源 第二技第一電源件端面254及第一接地件端面263、 避：錫録ΙίΓ/64上各凸部255,2 65所提供之高度h亦能 同第-實施例之功效，遂 作業時程，塊製程取代逐-點銲金球能縮短 質凸=戶可節；=2材質之錫銲凸塊替代價昂之金 已，並非：3 Ϊ，僅係用以說明本發明之具體實施例而 術内容之可：施範®，本發明之實質技 所完成之技述，！請專利範圍中，任何他人 印實體或方法’若與下述之申請專利範圍所定16650.ptd Page 16 558779 V. Description of the invention (11) Welding operation of source part 25 and a grounding part 26; however, the welding method provided in the second embodiment is different from the previous embodiment and is on the wafer 2 1 Power supply area 2 1 5, chip 21 connection area 216 and substrate 20 power component connection area 203 and substrate 20 ground component connection area 204, replacing the gold ball spot welding technology with the conventional solder bump process And a plurality of solder bumps 24 (Solder Bump) are planted; and in order to cooperate with the solder bumps 24, as shown in FIGS. 3C and 3D, the end face of the first power supply part 25 of the power supply part 2 5 3. The second power source end face 2 5 4 and the first grounding end face 263 and the second grounding end face 264 of the grounding member 26 each have at least one convex portion 2 5 5, 265 integrally formed. After the protrusions 2 5 5, 2 65+ are pre-plated with a tin-lead alloy or tin layer 27, they are sent to an oven (0ven) for 鬲 / jnL reflow operation. As in the aforementioned first embodiment, Huihui provides :::: which will cause the metal pre-plated layer 27 on the protrusions 255 265 to wet and cause a gold joint with the tin flute solder bumps 24 on the end face 2 and 53; 'The second-power source second technology first power source end surface 254 and first grounding element end surface 263, avoid: the height h provided by each convex portion 255, 2 65 on Xilu I / 64 can also be the same as that of the first embodiment Efficacy, operation time, block process instead of point-to-spot welding gold balls can shorten the quality of convexity = household can be saved; = 2 solder bumps of material have replaced expensive gold, not: 3 Ϊ, just for illustration The specific embodiment of the present invention and the technical content can be: Shi Fan®, the technical description of the substantial laboratory of the present invention ,! Please be within the scope of the patent. Any other entity or method of printing is determined by the scope of the patent application below.

558779558779

16650.ptd 第18頁 55877916650.ptd Page 18 558779

【圖式簡單說明】： 以下炫就各具體例配合所附圖式詳細揭露 點及功效： +赞明之特 之整 第1圖係本發明導電元件銲接方法之第一實 體製作步驟流程圖； 例 第2A至2E圖係本發明導電元件銲接方法第— 詳細製程示意圖； 1苑例之 第3A至3D圖係本發明導電元件銲接方法第-詳細製程示意圖； 乐一實施例之 第4圖係美國專利第5,545,923號半導體封不意圖， 裝件之 上視 示意Γ圖以係及美國專利第5’545,923號半導體封裝件之剖面 第6圖係習知之半導體封裝件之剖面示意圖 【符號標號說明】： 1 0, 2 0, 30 基板 101,301 第二表面 103, 203, 303電源件接置區 1 0 5, 30 5 銲線墊 110,310 作用表面 112,312 訊號銲墊 114,314 接地銲墊 116,216,316 接地區 13 打線機 I 00, 3 00 第一表面 102，302 晶片接置區 104,204,304接地件接置區 11，21，31半導體晶片 111 非作用表面 113, 313 電源銲墊 II 5，2 1 5，3 1 5 電源區 12 膠黏層 14, 24 金質凸塊[Brief description of the drawings]: The following shows the detailed disclosure points and effects of the specific examples in conjunction with the attached drawings: + Zamming's special first figure is a flowchart of the first physical manufacturing steps of the conductive component welding method of the present invention; Figures 2A to 2E are the first detailed schematic diagram of the welding method of the conductive element of the present invention; Figures 3A to 3D of the first example are the schematic-detailed process schematic of the welding method of the conductive element of the present invention; Patent No. 5,545,923 semiconductor package is not intended, the top view of the package is schematically shown in Figure Γ and the US Patent No. 5'545,923 semiconductor package cross-section Figure 6 is a conventional schematic diagram of the semiconductor package [symbols]: 1 0, 2 0, 30 Substrate 101, 301 Second surface 103, 203, 303 Power component connection area 1 0 5, 30 5 Wire bonding pads 110, 310 Active surface 112, 312 Signal bonding pads 114, 314 Ground bonding pads 116, 216, 316 Connection area 13 Wire bonding machine I 00 , 3 00 First surface 102,302 Wafer contact area 104,204,304 Ground contact area 11, 21, 31 Semiconductor wafer 111 Non-active surface 113, 313 Power pad II 5, 2 1 5, 3 1 5 Power zone 12 Adhesive layer 14, 24 Gold bumps

16650.ptd 第19頁 558779 圖式簡單說明 140 突出端 15,25 電源件 1 50, 350 支撐部 151 平坦部 152,352 延伸部 1 53, 2 53 第一電源件端面 154,254 第二電源件端 面 16, 26 接地件 160,360 支撐部 161 平坦部 1 62, 362 延伸部 1 63, 2 63 第一接地件端面 164,264 第二接地件端 面 17, 27 金屬預鍍層 18 熱壓治具 180 治具上模 180a 壓塊 180b 壓腳 19 共金接合部 255 凸部 265 凸部 306 訊號線 307 導電跡線 35 電源ί哀 356 電源線 36 接地線 366 接地線 37 導電膠 39 銲球 h 凸部高度16650.ptd Page 19 558779 Brief description of drawings 140 Protruding end 15,25 Power supply part 1 50, 350 Support part 151 Flat part 152,352 Extension part 1, 53, 2 53 First power supply end face 154,254 Second power supply end face 16, 26 Grounding piece 160, 360 Supporting portion 161 Flat portion 1 62, 362 Extension 1 63, 2 63 First grounding piece end face 164,264 Second grounding piece end face 17, 27 Metal pre-plated layer 18 Hot press fixture 180 Fixture upper mold 180a Press block 180b Presser foot 19 Common gold joint 255 Convex section 265 Convex section 306 Signal line 307 Conductive trace 35 Power source 356 Power line 36 Ground line 366 Ground line 37 Conductive glue 39 Solder ball h Height of projection

16650.ptd 第20頁16650.ptd Page 20

Claims (1)

558779 六、申請專利範圍 1. 一種導電元件之銲接方法，係包栝以下步驟： 先備一晶片承載件，於其一表面上預先定義出一 晶片接置區，且該表面於晶片接置區外之區域另形成 有一電源件接置區及一接地件接置區， 將一晶片接置於該晶片承載件之晶片接置區上， 該晶片上形成有一對應至該電源件接置區之電源區及 一對應至該接地件接置區之接地區； 植設複數個金屬銲塊至該晶片之電源區與接地區 以及該晶片承載件之電源件接置區與接地件接置區； 製備一電源件及一接地件，炎分別於該電源件及 接地件之兩端敷設一金屬層；以及 將該電源件及接地件接合至該晶片與晶片承載件 上，以使該電源件兩端上之金屬層分別與該電源區及 電源件接置區銲接，並使該接地件兩端上之金屬層分 別與該接地區及接地件接置區上之金屬銲塊銲接，俾 以形成共金接合部，而令該電源件及接地件得藉該共 金接合部而電性銲結至該晶片與晶片承載件。 2. 如申請專利範圍第1項之導電元件銲接方法，其中，該 晶片承載件係一基板。 3. 如申請專利範圍第1項之導電元件銲接方法，其中，該 晶片承載件係一導線架。 4. 如申請專利範圍第1項之導電元件銲接方法，其中，該 晶片形成有電源區及接地區之表面上佈設有多數電源 銲墊及接地銲墊，該電源銲墊及接地銲墊分別以重配558779 VI. Application for Patent Scope 1. A method for welding conductive components, including the following steps: Prepare a wafer carrier, define a wafer receiving area on one surface in advance, and the surface is in the wafer receiving area. In the outer area, a power device receiving area and a grounding device receiving area are formed. A wafer is placed on the wafer receiving area of the wafer carrier, and a wafer corresponding to the power device receiving area is formed on the wafer. A power supply area and a connection area corresponding to the ground piece connection area; planting a plurality of metal solder bumps to the power supply area and connection area of the chip and the power piece connection area and ground piece connection area of the chip carrier; Preparing a power supply part and a grounding part, laying a metal layer on both ends of the power supply part and the grounding part respectively; and bonding the power supply part and the grounding part to the wafer and the wafer carrier so that the power supply part two The metal layers on the ends are respectively welded to the power supply area and the power piece connection area, and the metal layers on both ends of the grounding piece are welded to the metal pads on the connection area and the grounding piece connection area, respectively, to form Engaging gold, while enabling the power supply unit and the ground member obtained by the co-gold bonding and electrically to the wafer and a bonding wafer carrier. 2. The method for soldering conductive elements according to item 1 of the patent application, wherein the wafer carrier is a substrate. 3. The method for soldering conductive elements according to item 1 of the patent application, wherein the chip carrier is a lead frame. 4. For the conductive component welding method of the first patent application scope, wherein the power supply area and the ground area of the wafer are provided with a plurality of power supply pads and ground pads, the power supply pads and the ground pads are respectively Reassign 558779 六、申請專利範圍 (Re-distribution)方式而電性整合至該電源區及接地 區。 5. 如申請 金屬銲 6. 如申請 金質銲 7. 如申請 金質銲 晶片之 置區與 8. 如申請 金屬銲 9. 如申請 電源件 支撐部 令該平 ，並使 件之電 I 0.如申請 電源件 金屬層 II ·如申請 接地件 支撐部 專利範圍 塊係金質 專利範圍 塊具有一 專利範圍 塊係藉一 電源區與 接地件接 專利範圍 塊係桿錫 專利範圍 係具有一 上敷設一 坦部得藉 該延伸部 源件接置 專利範圍 之支撐部 敷設至該 專利範圍 係具有一 上敷設一 第1項之導電元件銲接方法，其中，該 銲塊。 第5項之導電元件銲接方法，其中，該 向上凸起之突出端（Stud )。 第5項之導電元件銲接方法，其中，該 打線機（Wire Bonder)點銲壓接至該 接地區以及該晶片承載件之電源件接 置區。 第1項之導電元件銲接方法，其中，該 凸塊。 第1項之導電元件銲接方法，其中，該 支撐部、一平坦部及一延伸部，使該 金屬層而銲接至該晶片之電源區，俾 該支撐部之支持而架撐於該晶片上方 上敷設一金屬層而銲接至該晶片承載 區。 第9項之導電元件銲接方法，其中，該 及延伸部分別形成有一凸部，以令該 凸部上。 第1項之導電元件銲接方法，其中，該 支撐部、一平坦部及一延伸部，使該 金屬層而銲接至該晶片之接地區，俾558779 6. Re-distribution is applied to the power supply area and ground area. 5. If applying for metal welding 6. If applying for gold welding 7. If applying for gold welding wafer placement area and 8. If applying for metal welding 9. If applying for power supply support section to level the flat and make the parts electrical I 0 .For example, apply for the metal layer II of the power supply part. · For the patent range of the grounding support, the block is a gold patent range. The block has a patent range. The block is connected to the ground by a power supply block. The patent range is a rod tin. To lay a tank, the supporting part in the patent range of the extension source connection patent can be laid to the patent range, which has a method for welding a conductive element of the first item, wherein the soldering block. The welding method of the conductive element of item 5, wherein the protruding end (Stud) protruding upward. The conductive component welding method according to item 5, wherein the wire bonder is spot-welded to the bonding area and the power supply component receiving area of the wafer carrier. The method of soldering a conductive element according to item 1, wherein the bump. The conductive component soldering method of item 1, wherein the support portion, a flat portion, and an extension portion enable the metal layer to be soldered to the power supply region of the wafer, and supported by the support portion and supported on the wafer. A metal layer is laid and soldered to the wafer carrying area. The method of soldering a conductive element according to item 9, wherein the convex portion and the extending portion are respectively formed so that the convex portion is formed on the convex portion. The conductive element welding method of item 1, wherein the support portion, a flat portion, and an extension portion cause the metal layer to be soldered to a land area of the wafer, 俾 16650.ptd 第22頁 558779 六、申請專利範圍 令該平坦部得藉該支撐部之支持而架撐於該晶片上方 ，並使該延伸部上敷設一金屬層而銲接至該晶片承載 件之接地件接置區。 12. 如申請專利範圍第11項之導電元件銲接方法，其中， 該接地件之支撐部及延伸部分別形成有一凸部，以令 該金屬層敷設至該凸部上。 13. 如申請專利範圍第1項之導電元件銲接方法，其中，該 金屬層係一錫錯合金層。16650.ptd Page 22 558779 6. The scope of patent application allows the flat portion to be supported above the wafer by the support of the support portion, and a metal layer is laid on the extension portion to be soldered to the ground of the wafer carrier Piece picking area. 12. The welding method for conductive elements according to item 11 of the scope of patent application, wherein the support portion and the extension portion of the grounding member are respectively formed with a convex portion, so that the metal layer is laid on the convex portion. 13. The welding method for conductive elements according to item 1 of the application, wherein the metal layer is a tin alloy layer. 14. 如申請專利範圍第1項之導電元件銲接方法，其中，該 金屬層係一錫層。 1 5.如申請專利範圍第1項之導電元件銲接方法，其中，該 金屬層係以熱壓合方式與該金屬銲塊銲接。 1 6.如申請專利範圍第1項之導電元件銲接方法，其中，該 金屬層係以回銲方式與該金屬銲塊銲接。14. The method for soldering conductive elements according to item 1 of the application, wherein the metal layer is a tin layer. 1 5. The method for welding a conductive element according to item 1 of the scope of patent application, wherein the metal layer is welded to the metal solder bump by a thermocompression bonding method. 16. The method for welding conductive elements according to item 1 of the scope of patent application, wherein the metal layer is welded to the metal solder bump by means of reflow soldering. 16650.ptd 第23頁16650.ptd Page 23
TW091110203A 2002-05-16 2002-05-16 Method for bonding conductive members in semiconductor package TW558779B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114299223A (en) * 2021-11-18 2022-04-08 芯瑞微(上海)电子科技有限公司 Three-dimensional model identification and construction method for multilayer routing package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114299223A (en) * 2021-11-18 2022-04-08 芯瑞微(上海)电子科技有限公司 Three-dimensional model identification and construction method for multilayer routing package
CN114299223B (en) * 2021-11-18 2024-01-23 芯瑞微(上海)电子科技有限公司 Three-dimensional model identification and construction method for multilayer wire bonding package

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