TW558726B - Improved material for use with ferreoelectrics - Google Patents

Improved material for use with ferreoelectrics Download PDF

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TW558726B
TW558726B TW091119562A TW91119562A TW558726B TW 558726 B TW558726 B TW 558726B TW 091119562 A TW091119562 A TW 091119562A TW 91119562 A TW91119562 A TW 91119562A TW 558726 B TW558726 B TW 558726B
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ferroelectric
oxide
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ruthenium
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Rainer Bruchhaus
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Infineon Technologies Ag
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

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Abstract

A liner layer comprising TiO2 enriched SRO is disclosed. The TiO2 enriched SRO liner improves the reliability of ferroelectric materials such as PZT without adversely impacting or degrading the ferroelectric properties of the PZT. The SRTO, in one embodiment is sputtered using an SRO target doped with 1-10% TiO2.

Description

558726 A7 _B7_ 五、發明説明（i ) 發明領域 本發明係關於鐵電積體電路，特別是關於可降低鐵電材 料中之疲勞（fatigue)的材料。 先前技藝 鐵電金屬氧化物陶磁材料，例如錘鈦酸鉛（Lead Zirconate Titanate，PZT), —直被探討其在鐵電半導體記憶體裝置上的 用途。一個鐵電記憶體裝置的記憶體單元包含一個用做儲 存元件的電容器。圖1顯示一種習知鐵電電容器ΗΠ。如圖1所 示，電容器包含夾在第一電極110及第二電極120之間的鐵電 金屬氧化物陶磁層150。典型上，電極是由如鉑之類的貴金 屬（noble metal)所構成。 鐵電電容器係使用鐵電材料之磁滞極化（hysteresis polarization)特性來儲存資訊。儲存於記憶體單元中的邏輯值 係依據鐵電電容器之極化而定。如果要改變電容器的極化， 就必須施加一大於切換電壓（強制電壓，coercive voltage)的電 壓通過電極。電容器之極化係依據施加之電壓極性而定。 鐵電電容器的優點之一是即使在電源被除去之後，仍保 持其極性狀態以形成一非揮發性記憶體單元。然而，在特定 次數的切換循環之後，疲勞現象會發生於鐵電材料之中。為 了降低發生於鐵電電容器中的疲勞，以鳃-釕-氧化物 (Strontium-Ruthenium-Oxide，SrRu03 或 SR0)當做襯材，附加於鐵電 薄膜和電極之間的構想已被提出。典型上，鳃-釕-氧化物是 以濺鍍形成。 然而，由於二氧化釕（Ru02)和氧化锶（SrO)所形成的化合 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐)558726 A7 _B7_ V. Description of the Invention (i) Field of the Invention The present invention relates to ferroelectric integrated circuits, and particularly to materials that can reduce fatigue in ferroelectric materials. Prior art Ferroelectric metal oxide ceramic magnetic materials, such as Lead Zirconate Titanate (PZT), have been explored for their use in ferroelectric semiconductor memory devices. The memory cell of a ferroelectric memory device contains a capacitor used as a storage element. FIG. 1 shows a conventional ferroelectric capacitor ΗΠ. As shown in FIG. 1, the capacitor includes a ferroelectric metal oxide ceramic magnetic layer 150 sandwiched between a first electrode 110 and a second electrode 120. Typically, the electrode is made of a noble metal such as platinum. Ferroelectric capacitors use hysteresis polarization characteristics of ferroelectric materials to store information. The logic value stored in the memory cell depends on the polarization of the ferroelectric capacitor. If the polarization of the capacitor is to be changed, a voltage greater than the switching voltage (coercive voltage) must be applied through the electrode. The polarization of a capacitor depends on the polarity of the applied voltage. One of the advantages of a ferroelectric capacitor is that it maintains its polar state to form a non-volatile memory cell even after the power source is removed. However, after a certain number of switching cycles, fatigue can occur in ferroelectric materials. In order to reduce the fatigue that occurs in ferroelectric capacitors, the concept of using gill-ruthenium-oxide (SrRu03 or SR0) as a lining material and attaching it between a ferroelectric film and an electrode has been proposed. Gill-ruthenium-oxide is typically formed by sputtering. However, due to the combination of ruthenium dioxide (Ru02) and strontium oxide (SrO) -4- This paper is sized to the Chinese National Standard (CNS) A4 (210X 297 mm)

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558726 A7 ____Β7 五、發明説明（2 ) 物的不安定性，使用鳃-釕-氧化物做為襯材時產生問題。特 別是’二氧化釕是一種揮發性氧化物，而如果氧化銷曝露於 環境的空氣下很谷易形成碳酸總（SrC〇3)。部份的二氧化釕在 非晶薄膜（在濺鍍的成膜過程中）結晶退火的過程中蒸發，導 致鳃-釕-氧化物層中的氧化鳃過量。這是所不想要的，因為 過量的氧化鳃會在鳃-釕-氧化物層的表面上產生花狀的外形 。此外，氧化鳃本身是一種絕緣材料，導致鐵電電容器性質 退化。 含有過量二氧化鳃的鳃_氧化物靶材被用來補償氧化鳃 在結晶退火過程中的損耗。然而，在鐵電材料的高溫結晶的 過程中，過量的二氧化鳃會擴散並與鐵電層反應，導致其鐵 電特性的降低。 由則述的纣論可知，提供一種可降低在鐵電材料中的疲 勞而且不會影響其鐵電特性的改善材料是想要的。 發明概述 本發明係關於使用可降低在鐵電材料中的疲勞而且不會 負面地影響其鐵電特性的材料。在本發明的一實施例中，該 材料I ;添加一氧化鈥之總_釕_氧化物。總-釕·氧化物包含 約1至10重量％的二氧化鈥（除非特別指明，否則本發明均二 用重量％來表示成份之比例）。在一實施例中，添加二氧化欽 的總-釕·氧化物係形成於—基板上，該基板已經被加工處理 以包含一第一電容器電極或一下電容器電極。如锆鈦酸鉛 j鐵電材料形成於添加二氧化鈦的鳃·釕_氧化物上。然後， 第二層添加二氧化鈦的鳃省-氧化物層形成於鐵電層上。隨 -5- 558726 A7 B7 五、發明説明（3 ) 後，形成上電極。在一實施例中，鳃-釕-氧化物添加層藉由 使用摻雜1-10% Ti02的鳃-釕-氧化物靶物以濺鍍的方式形 成。 圖式簡單說明 圖1顯示一種習知的鐵電電容器； 圖2顯示一種本發明之實施例的鐵電電容器； 圖3顯示一種本發明之實施例中用以沉積添加二氧化鈦的 鳃-对-氧化物層的系統；及 圖4顯示一種在結晶退火後的鈦酸鳃層。 發明詳述 圖2係顯示一種根據本發明之實施例的鐵電電容器20卜例 如，這樣的電容器是用於形成鐵電記憶體積體電路的鐵電 記憶體單元。如圖2所示，這個電容器包含第一電極210及第 二電極220。舉例而言，電極是由鉑或貴金屬（例如銥、鉛、 二氧化銥或其它導電氧化物）所構成。鐵電層150是設置於二 電極之間。在實施例中，鐵電材料包含錘鈦酸鉛或鑭錘鈦酸 船（Lead-Lanthanum-Zirconium-Titanate，PLZT)，也可使用如祕鈥酸 總（Strontium-Bismuth-Tantalate，SBT)這類的鐵電材料。 襯層230a和230b係提供於二電極與鐵電層之間以降低在鐵 電層中的疲勞。根據本發明，襯層包含添加二氧化鈦的鳃-釕-氧化物層（即掺雜二氧化鈥的魏-釘•氧化物層）。二氧化欽 改良了鳃-釕-氧化物層的安定性，也降低花狀外形的形成。 在一實施例中，鳃-釘-氧化物層係摻雜1至10重量％的二氧化 鈦。如果鳃-釕-氧化物層中的二氧化鈦超過10%會增加添加 -6 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)558726 A7 ____ Β7 V. Description of the invention (2) The instability of the material causes problems when using gill-ruthenium-oxide as the lining material. In particular, ruthenium dioxide is a volatile oxide, and if the oxidation pin is exposed to the ambient air, carbon dioxide is easily formed (SrC03). Part of the ruthenium dioxide evaporates during the crystallization annealing of the amorphous film (during the sputtering film formation process), resulting in excessive gill oxide in the gill-ruthenium-oxide layer. This is undesirable because excessive oxidized gills will produce a flower-like shape on the surface of the gill-ruthenium-oxide layer. In addition, the oxidized gill itself is an insulating material, which causes degradation of the properties of the ferroelectric capacitor. The gill-oxide target containing excessive gill dioxide was used to compensate for the loss of the gill oxide during the crystallization annealing process. However, during the high-temperature crystallization of ferroelectric materials, excess gills will diffuse and react with the ferroelectric layer, resulting in a reduction in its ferroelectric properties. As can be seen from the above discussion, it is desirable to provide an improved material that can reduce fatigue in ferroelectric materials without affecting its ferroelectric characteristics. SUMMARY OF THE INVENTION The present invention relates to the use of materials that reduce fatigue in ferroelectric materials without adversely affecting their ferroelectric properties. In one embodiment of the present invention, the material I is added with a total of ruthenium oxide. The total-ruthenium · oxide contains about 1 to 10% by weight of dioxide (unless otherwise specified, the present invention refers to the component ratio by weight%). In one embodiment, the total-ruthenium-oxide system added with dioxin is formed on a substrate, and the substrate has been processed to include a first capacitor electrode or a lower capacitor electrode. For example, lead zirconate titanate j ferroelectric materials are formed on gill-ruthenium oxide with titanium dioxide added. Then, a second titanium oxide-added gill province-oxide layer is formed on the ferroelectric layer. With -5- 558726 A7 B7 V. Description of the invention (3), the upper electrode is formed. In one embodiment, the gill-ruthenium-oxide addition layer is formed by sputtering using a gill-ruthenium-oxide target doped with 1-10% Ti02. Brief description of the drawings Figure 1 shows a conventional ferroelectric capacitor; Figure 2 shows a ferroelectric capacitor according to an embodiment of the present invention; Figure 3 shows a gill-pair-oxidation for depositing titanium dioxide added in an embodiment of the present invention Layer system; and Figure 4 shows a gill layer of titanate after crystallization annealing. Detailed description of the invention Fig. 2 shows a ferroelectric capacitor 20 according to an embodiment of the present invention. For example, such a capacitor is a ferroelectric memory cell for forming a ferroelectric memory volume circuit. As shown in FIG. 2, this capacitor includes a first electrode 210 and a second electrode 220. For example, the electrode is made of platinum or a precious metal, such as iridium, lead, iridium dioxide, or other conductive oxides. The ferroelectric layer 150 is disposed between two electrodes. In the embodiment, the ferroelectric material includes lead-titanate or lanthanum-titanate (PLZT), and Strontium-Bismuth-Tantalate (SBT) can also be used. Ferroelectric material. Liners 230a and 230b are provided between the two electrodes and the ferroelectric layer to reduce fatigue in the ferroelectric layer. According to the present invention, the underlayer comprises a gill-ruthenium-oxide layer (ie, a Wei-nail-doped oxide layer doped with dioxide) added with titanium dioxide. Chlorine dioxide improves the stability of the gill-ruthenium-oxide layer and reduces the formation of flower-like shapes. In one embodiment, the gill-nail-oxide layer is doped with 1 to 10% by weight of titanium dioxide. If the titanium dioxide in the gill-ruthenium-oxide layer exceeds 10%, it will be added -6-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

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558726 A7 B7 五、發明説明（4 ) 二氧化鈥之總-釕-氧化物層層的薄層電阻（sheet resistance)，並 超過期望的上限值，反而不利地影響電容器的性能。在一實 施例中，添加二氧化鈦之鳃-釕-氧化物層的厚度約5至50奈米 ，鐵電層的厚度約100至200奈米，而電極的厚度約10至100奈 米。摻雜二氧化鈦的鳃-釕_氧化物層的較佳厚度是在5至50奈 米這個範圍，而典型的锆鈦酸鉛層厚度是100至200奈米，鉑 為10至100奈米。 在一實施例中，添加二氧化鈦的鳃省-氧化物層是濺鍍於 基板上。圖3顯示一種用以沉積添加二氧化鈥之總·釘-氧化物 層的濺鍍系統3(H。濺鍍系統301包含用於安置基板的基板承 座305。舉例而言，基板已加工處理以包含做為電容器之下 電極的導電層（例如鉑）。視加工處理而定，導電層可被圖案 化，也可沒有被圖案化。濺鍍系統301也包含了添加1至10% 二氧化鈦之鳃-釘-氧化物陶磁化合物的濺鍍靶材310。 在濺鍍過程中，來自靶材的原子在基板上反應形成由氧 化鳃、二氧化鈦及二氧化釕的非晶層330。舉例說明，濺鍍 過程的參數如下： ’558726 A7 B7 V. Description of the Invention (4) The total sheet resistance of the total ruthenium-oxide layer of the dioxide, which exceeds the expected upper limit, adversely affects the performance of the capacitor. In one embodiment, the thickness of the gill-ruthenium-oxide layer added with titanium dioxide is about 5 to 50 nm, the thickness of the ferroelectric layer is about 100 to 200 nm, and the thickness of the electrode is about 10 to 100 nm. The preferred thickness of the titanium-doped gill-ruthenium oxide layer is in the range of 5 to 50 nm, while the thickness of a typical lead zirconate titanate layer is 100 to 200 nm and platinum is 10 to 100 nm. In one embodiment, the titanium dioxide-added gill province-oxide layer is sputtered on the substrate. Figure 3 shows a sputtering system 3 (H. Sputtering System 301 including a substrate-supported substrate 305 for depositing a substrate-deposited total nail-oxide layer). For example, the substrate is processed It contains a conductive layer (such as platinum) as the electrode below the capacitor. Depending on the processing, the conductive layer may or may not be patterned. The sputtering system 301 also includes the addition of 1 to 10% titanium dioxide. Gill-nail-oxide ceramic magnetron sputtering target 310. During the sputtering process, atoms from the target react on the substrate to form an amorphous layer 330 of gill oxide, titanium dioxide, and ruthenium dioxide. For example, sputtering The parameters of the plating process are as follows: ''

壓力 :0.5至 1 Pa 溫度 :室溫至650°C 電力 :500至 1000 W 反應氣體：5至50%體積重量之氬氣 舉例而言，在沉積之後，非晶層係施以450至700°C，持續 約30秒至5分鐘的退火製程結晶化。在退火過程中，過量的 氧化鈽被轉換成鈦酸鳃（SrTi03，STO)。鈦酸锶是具有鈣鐵礦 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)Pressure: 0.5 to 1 Pa Temperature: Room temperature to 650 ° C Electricity: 500 to 1000 W Reaction gas: 5 to 50% by volume of argon gas For example, after deposition, the amorphous layer is subjected to 450 to 700 ° C, crystallization during an annealing process that lasts about 30 seconds to 5 minutes. During the annealing process, an excess of thorium oxide was converted into titanate gills (SrTi03, STO). Strontium titanate is perovskite. This paper is sized for China National Standard (CNS) A4 (210 X 297 mm).

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558726 A7 B7 五、發明説明（5 ) 結構（相似於錘鈦酸鉛及其它類別的鐵電材料）的穩定材料。 如圖4所示，添加二氧化鈦的鳃-釕-氧化物層也含有反應的二 氧化鈥晶粒434 (grain)。魏-釕-氧化物層及未反應的二氧化鈥 晶粒係做為後續形成之鐵電層的結晶位置，觸發在鐵電層 中非常均勻的晶粒結構及增進鐵電特性。 在添加二氧化鈦之鳃-釕-氧化物層結晶化之後，製程持續 進行以形成鐵電電容器並完成積體電路。舉例而言，這些製 程包含形成鐵電層，第二層添加二氧化鈦之鳃-釕-氧化物層 ，上電極，内連線（interconnects)及内介電層（interlevel dielectrics) ，保護層（passivation layer)及封裝(packaging) 〇 雖然本發明已特別以參考個別實施例描述，熟悉該項技 藝者仍將明白在不偏離本發明範圍及精神下，本發明將有 各種修正及變化。因此本發明乏範圍不應以上述之實施例 決定，而應以本發明之申請專利範圍及其對等範圍決定。 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)558726 A7 B7 V. Description of the invention (5) Stable material with structure (similar to hammer lead titanate and other types of ferroelectric materials). As shown in Figure 4, the titanium-added gill-ruthenium-oxide layer also contains the reactive dioxide 'grains 434 (grain). The Wei-Ru-oxide layer and the unreacted dioxide 'grains serve as the crystalline sites for the subsequent formation of the ferroelectric layer, triggering a very uniform grain structure in the ferroelectric layer and improving ferroelectric properties. After crystallization of the gill-ruthenium-oxide layer with the addition of titanium dioxide, the process continues to form a ferroelectric capacitor and complete the integrated circuit. For example, these processes include the formation of a ferroelectric layer, a second layer of titanium gill-ruthenium-oxide layer, an upper electrode, interconnects and interlevel dielectrics, and a passivation layer. ) And packaging 〇 Although the present invention has been described with particular reference to individual embodiments, those skilled in the art will still understand that the present invention will have various modifications and changes without departing from the scope and spirit of the invention. Therefore, the lack of scope of the present invention should not be determined by the above-mentioned embodiments, but should be determined by the scope of patent application of the present invention and its equivalent scope. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

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Claims (1)

六、申請專利範圍Scope of patent application 沉積一第一非晶襯層於電極上； 沉積一鐵電層於第一非晶襯層上； ’儿積一第一非晶襯看於鐵電層上；及 」冗積一第二導電層於襯層上，第二導電層係用做第二 ㈣’其中襯層包含總-釘_氧化物L氧化物添加約i 2. 3. 至10重量％之二氧化鈥，其中襯層改良鐵電層之特性。 如申請專縣㈣丨項之料，其中鐵電層包含贼酸错。 如申請專利範圍第2項之方法，其中第—電極包含貴金屬 (noble metal) 〇 4·如申請專利範圍第3項之方法，其中第一電極包含舶。 5·如申請專利範圍第丨項之方法，其中電極包含貴金屬。 6·如申請專利範圍第5項之方法，其中電極包:始。 7·如申請專利範圍第1，2, 3，4, 5或6項之方法，更包含退 火製程以結晶化添加二氧化鈦之鳃_釕_氧化物層。 8.如申請專利r巳圍第7項之方其中退火製程包含以約 65〇 C加熱添加二氧化鈥之銳…釕_氧化物層約3〇秒。 9·如申凊專利範圍第8項之方法，更包含完成鐵電記憶體積 體電路之步驟。 10·如申請專利範圍第7項之方法，更包含完成鐵電記憶體積 體電路之步驟。 η· 一種形成一鐵電電容器的方法，包含·· -9 - 本紙張尺度通用國家標準(CNS) Μ規格ΰΐΟ X 297公釐) 558726 A BCD 申請專利範圍 沉積一第一非晶層於基板上； 沉積一鐵電層於第一非晶層上； 沉積一第二非晶襯層於鐵電層上；及 沉積一第二導電層於第二非晶襯層上，第二導電層係 用做第二電極，其中該襯層包含鳃-釕-氧化物，鳃-釕-氧 化物添加1至10重量％之二氧化鈦，其中該襯層改良鐵電 層之特性。 -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)Deposit a first amorphous liner on the electrode; deposit a ferroelectric layer on the first amorphous liner; 'a first amorphous liner on the ferroelectric layer; and "redundant a second conductive Layer on the backing layer, the second conductive layer is used as the second layer, wherein the backing layer contains the total-nail_oxide L oxide added about i 2. 3. to 10% by weight of the dioxide, wherein the backing layer is improved Characteristics of ferroelectric layers. For example, if you apply for special county materials, the ferroelectric layer contains thief acid. For example, the method of the second item of the patent application, wherein the first electrode comprises a noble metal. 4 · The method of the third item of the patent application, wherein the first electrode includes a ship. 5. The method according to the first item of the patent application, wherein the electrode comprises a precious metal. 6. The method according to item 5 of the scope of patent application, wherein the electrode package: start. 7. The method of claim 1, 2, 3, 4, 5 or 6, further comprising an annealing process to crystallize the gill-ruthenium-oxide layer to which titanium dioxide is added. 8. The method of claim 7 in the patent application wherein the annealing process includes heating the addition of the oxide of ruthenium ... at about 65 ° C for about 30 seconds. 9. The method in item 8 of the patent application scope further includes the steps of completing a ferroelectric memory volume circuit. 10. The method of item 7 in the scope of patent application, further comprising the step of completing a ferroelectric memory volume circuit. η · A method for forming a ferroelectric capacitor, including ... -9-Common National Standard (CNS) M size ΰΐ X 297 mm) 558726 A BCD application patent deposits a first amorphous layer on a substrate Depositing a ferroelectric layer on the first amorphous layer; depositing a second amorphous liner on the ferroelectric layer; and depositing a second conductive layer on the second amorphous liner, the second conductive layer is used for As a second electrode, the underlayer contains gill-ruthenium-oxide, and gill-ruthenium-oxide is added with 1 to 10% by weight of titanium dioxide, and the underlayer improves the characteristics of the ferroelectric layer. -10- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)
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