TW557567B - Double channel pseudomorphic high electron mobility transistor - Google Patents

Abstract

A double channel pseudomorphic high electron mobility transistor (PHEMT) is disclosed. The transistor uses two stacked structure composed of such as InGaP/InGaAs/GaAs as a channel structure of a transistor. Therefore, an InGaAs layer having a thicker thickness and higher In mole fraction can be used as channel layers to obtain the object of enhancing the transistor performance.

Description

557567 A7, ----- B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

V. Description of the invention () Field of invention: # 发 日月 is related to a pseudo-crystalline high electron mobility transistor (Pseud〇m〇rphic High) with a double channel structure.

EleeUon Mobility Transistor; phemt), in particular, relates to a type of transistor that uses a double-layer stack structure composed of, for example, indium gallium phosphide (InGaP) / indium gallium arsenide (InGaAs) / thallium arsenide (GaAs). Pseudocrystalline high electron mobility transistor with channel structure. Background of the invention: In general, σ 'is due to the low effective mass, high electron mobility, and saturation speed of the Shishenhua indium gallium material. Therefore, in order to obtain better performance, gallium arsenide is used as the substrate. In field-effect transistors with heterostructures, it has become a trend to use indium gallium arsenide instead of gallium arsenide as the channel material. In a heterostructure field effect transistor using gallium arsenide as a substrate and indium gallium arsenide as a channel material, due to the lattice constant difference between the two layers of gallium arsenide and indium gallium arsenide, When epitaxial growth of a thin indium gallium arsenide layer on a substrate results in considerable strain on the indium gallium arsenide layer. As the person skilled in the art knows, the strain generated on the indium gallium arsenide layer will further deepen the quantum well. This phenomenon is due to, for example, two of the pseudo-crystalline high electron mobility transistors Two-dimensional electron gas (TwO Electron Gas; 2DEG) is formed by the large increase in electrons. The two-dimensional electron gas generated by the quantum well can increase the carrier movement ^ and speed of the element. (The increase in indium content ’

This paper size applies the Chinese National Standard (CNS) A4 specification (210X297). 6 5 7 5 5 Description of the invention () = The lattice mismatch between the materials has also increased, making the neutron well in the transistor even more Deepening can further improve the performance of transistor components. However, when the content of indium is too high, it will cause the lattice of the indium gallium arsenide material to relax = where W is the phenomenon that the relaxation of the lattice is caused by the excessive accumulated strain in the lattice: after the release. The lattice defect formed by this Shao ’is like a multiple scattering center. The scattering centers generated by these lattice defects will cause the mobility and velocity of the seed to decrease. Due to the influence of the lattice configuration between materials, the thickness of the indium gallium arsenide channel material and the content of indium (In) are doubled to the limit, which causes the problem of critical thickness. 1 The critical thickness problem caused by the mismatch of the crystal rhenium constants between the materials ’’ S ’crystal rhenium elements cannot be made thick and have a high arsenic content.

Indium gallium material. As a result, transistor components will be limited in future higher-efficiency applications. I Purpose and summary of the invention: In view of the above background of the invention, the critical thickness problem caused by the lattice constant mismatch between the materials will cause the thickness and indium content of the indium gallium arsenide channel material to be limited, and the transistor cannot be effectively improved. Component effect Z 2 application. Μ Therefore, one of the main objects of the present invention is to provide a pseudomorphic two-electron mobility transistor using a double-layer Indium Gallium Phosphide (InGap) / InGaAs / GaAs stack Structure as the channel structure of the transistor element. In this way, a thicker indium gallium arsenide material with a higher indium content can be used as the channel layer. Therefore, the carrier transmission characteristics can be increased and the gate current can be improved. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 public love).

Ordered by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by employee consumer cooperatives 557567 A7 B7 V. Description of the invention (Pressure swing. The other purpose of = is to provide-a plane with a double-layered channel structure ::: ... 'It uses the upper, middle, and lower layers = the heterogeneous layer as the carrier supply layer. In this way, double-layer channels and AC linearity can be made. Another purpose of the electrical-body components to obtain excellent DC light is to Provide a high-electron mobility transistor crystal base = using Γ-gap material such as a disc as a buffer layer and Xiao M: said, the indium gallium phosphide layer above the middle channel structure can provide the transistor Basic characteristics, and the substrate leakage current under the channel structure of the indium recording layer p. The substrate has a very good sandwiching characteristic. Another purpose of making the electrical system is to provide A kind of double-layered channel structure with a layer of indium-gallium material in the channel structure and Shishenhua Steel's bridging material (the large discontinuity of the conductive band eCc) can effectively charge the carrier = in another layer Channel structure 'therefore reduces forward bias operation According to the above-mentioned purpose, the present invention further provides a pseudo-crystallized high electron mobility transistor having a double-layered channel structure, including at least: an insulating substrate; On the above semi-insulating substrate, a second undoped buffer layer is located on the first-undoped buffer layer, a first planar doped layer is located on the second undoped buffer layer, and An undoped isolation layer is located on the above-mentioned first planar doped layer; a first un-doped paper size is applicable to China National Standard (CNS) A4 (210X297 mm) 557567

2. Description of the invention (The hetero-channel layer is located on the above isolation layer: on the undoped isolation layer;-the second undoped layer is on the first-undoped channel layer; a second planar doped layer is on the above On the first undoped isolation layer; a third undoped isolation; on the second doped layer of the second earth M; a second undoped channel layer side

The fourth layer is described above; a fourth undoped isolation layer is located on the J < first undoped through fourth undoped spacer, and the third plane is doped on the third plane. Miscellaneous:-, Unchanged Schottky contact layer is located in ... Schottky contact layer :, and :: Four-plane doped layer is located in part of the undoped layer; The undoped insulating layer is located on the fourth planar doped layer described above; the ohmic contact layer is wiped on the electrode, and the electrode is on the fifth undoped isolation layer described above. ; A pan and 1 pole is located on a part of the doped ohmic contact layer; and a non-doped Schottky contact layer that is harmonized and exposed. Here, the pseudo-crystalline high thunder ·· JL · < Aτ jc ~ layer, the first-undoped spacer layer in the-undoped Λ transistor, and the second undoped spacer layer constitute this # 明 之The first layer of the channel structure, while the third unblended isolation layer, the second = meal channel layer, and the fourth undoped isolation layer constitute the first The layers and the fourth undoped isolation layer may be, for example, indium gallium phosphide, aluminum gallium arsenide (A1GaAs), or aluminum phosphide. The second un-doped isolation layer and the third undoped Isolation ~ The material may be, for example, gallium arsenide or indium phosphide (InP). In addition, the material of the first channel layer and the second undoped channel layer are both indium arsenide: doped. Therefore, the _th undoped channel layer and the second undoped channel layer are available: Applicable to China National Standard (CNS) A4 specification (210X297), 557567 A7

V. Description of the invention () Indium gallium arsenide material with higher indium content is used as the channel layer, so as to increase the characteristics of the carrier wheel and increase the gate voltage swing. The first planar doped layer, the second planar doped layer, and the third planar doped layer are used as carrier supply layers. The three-layer carrier supply layer can uniformly distribute the carriers in the above-mentioned double-layered channel structure, so that the transistor element can obtain excellent DC and AC linearity. Detailed description of the invention: The present invention discloses a pseudo-crystallized high electron mobility transistor having a double-layered channel structure, which uses a double-layered structure to form a transistor using, for example, an indium gallium phosphide / indium gallium arsenide / thallium halide stack structure. Channel structure, and the top, middle and bottom plane doping layers are used as the carrier supply layer. Therefore, in addition to using thicker and higher indium gallium indium gallium arsenide as the material of the channel layer, in order to increase the carrier transmission characteristics and increase the gate voltage swing, it can also make the The carriers are evenly distributed, so that the transistor element obtains excellent DC and AC linearity, thereby achieving the purpose of improving the element performance. In order to make the description of the present invention more detailed and complete, reference may be made to the following descriptions in conjunction with the diagrams in FIGS. 1 to 9. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economics Please refer to FIG. 1. FIG. 1 is a cross-sectional view of a pseudo-crystallized high electron mobility transistor having a double-layered channel structure according to a preferred embodiment of the present invention. The structure of the transistor of the present invention 00 is firstly applied to a semiconductor using, for example, Low Pressure Metal Organic Chemical Vapor Deposition (LP-MOCVD) or Molecular Beam Epitaxy (MB E). The substrate ii2 is based on the 6 paper standards applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 557567 A7 B7 Five printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives printed the invention description (in order to form an undoped buffer layer 114 to cover On the substrate 112; the undoped buffer layer 116 covers the buffer layer Η; the planar doping layer us covers the buffer layer 116; the undoped isolation layer 120 covers the planar doped layer ι8; The impurity channel layer 122 covers the isolation layer 120. The undoped isolation layer 124 covers the channel layer 122. The planar doped layer 126 covers the isolation layer 124. The undoped isolation layer 128 covers the planar doped layer. On the impurity layer 126; the undoped channel layer 130 covers the isolation layer 128; the undoped isolation layer 132 covers the channel layer 130; the planar doped layer 134 covers the isolation layer 132; Schottky contacts The layer 36 covers the planar doped layer 134; the planar doped layer 138 covers the Schottky contact layer 136; the undoped isolation layer 140 covers the planar doped layer 138; and the ohmic contact layer 142 covers the The isolation layer 140. Among them, the 'isolation layer 120, the channel layer 122, and the isolation layer 124 constitute a one-layer channel structure of the transistor 100, and the isolation layer 128, the channel layer 13 and the isolation layer 1 32 constitute the transistor 1'. 〇 Another layer of channel structure, that is, the isolation layer 120 / channel layer 122 / isolation layer 124 and the isolation layer 128 / channel layer 130 / isolation layer 13 2 are stacked to form the double-layer channel structure of the present invention. For example, a vacuum evaporation method is used to form a metal layer of the source electrode 144 and the drain electrode 146 (only the source electrode 144 and the drain electrode 146 are shown) and cover the ohmic contact layer 142. The metal layer may be, for example, Au / Ge (Ge) / nickel (Ni) stacked structure. Then under the environment of about 250 ° C for about 10 seconds Annealing step, so that the source electrode 144 and drain electrode 146 metal layer and ohms The contact layer 1 42 forms an ohmic contact. Then, using an example paper size Use Chinese National Standard (CNS) A4 specification (210X297 mm) 557567 A7 ----- B7 V. Description of the invention () (Please read the precautions on the back before filling this page) Photolithograph and etching, For example, wet etching defines the metal layers of source 1 44 and drain 46, and removes part of the metal layer, and exposes part of the ohmic contact layer 42, thereby forming source 1 on the ohmic contact layer 142, respectively. 44 and drain 1 46. After the source electrode 44 and the drain electrode 146 are formed, they are defined using, for example, lithography and a wet etching process, and the exposed ohmic contact layer 142 and the isolation layer 1 40 and a part of the planar doped layer 1 underneath are defined. 3, and part of the Schottky contact layer 136 is removed until the Schottky contact layer 136 is exposed, and the ohmic contact layer 142, the isolation layer 140, and the planar doped layer 138 on the Schottky contact layer 136 are removed. In the opening ι5〇. After the opening 150 of the Schottky contact layer 1 36 is formed, a gate electrode 148 is formed on the exposed Schottky contact layer 136 by, for example, evaporation, and a structure as shown in FIG. 1 is formed. . The material of the gate 148 may be, for example, aluminum, titanium (Ti), molybdenum (Mo), platinum (Pt), gold, and alloys thereof, such as titanium / gold alloy or platinum / gold alloy. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In the transistor 100 structure of the present invention, the material of the substrate 112 may be, for example, gallium arsenide or indium phosphide. The material of the buffer layer 14 may be, for example, gallium arsenide or indium phosphide, and the thickness of the buffer layer 114 is preferably between 01 and m. The material of the buffer layer 116 can be, for example, indium gallium phosphide (In0 49 Ga (). 5lP), AlxGabxAs, χ is between 0 ″ to ^ 〇, aluminum gallium phosphide (AluGauP), Or indium aluminum arsenide (Al 1O "η. 52As), and the thickness of the buffer layer 116 is preferably between 2000A and 5000a. The planar doped layer 118 is used as a carrier. Sub-supply layer, and the plane is doped. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm). ---- 557567 V. Description of the invention (Printing layer 118, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs) The doping concentration 5 (N +) is preferably between 1 × 1011 cm_2 (cm · 2) cm. The material of the isolation layer 120 may be, for example, indium gallium indium (In.49Ga〇5lP), Kunhua Indium gallium (AlxGai_xAs), X is between 0 ″ to! 0 ^, indium aluminum phosphide (A10.5ΐη〇5P), or indium aluminum arsenide (A1〇 ”InmAs), etc., and the thickness of the isolation layer 120 Preferably, it is between 30A and 80. The material of the channel layer 122 may be, for example, indium gallium arsenide (InxGai-xAs) with a thickness of 50A to 150. 〇5 to 〇3, or thickness between 100 InxGai xAs (A to 300A), χ is between 03 and 0.7. The material of the isolation layer 124 may be, for example, gallium 4 g or canned copper, and the thickness of the isolation layer 124 is preferably Between 30 and 80 people. The plane doping 1 126 is used as a carrier supply layer, and the doping concentration 5 (N +) of the plane doping layer & preferably is between 1 × 1. The material of ucm-2 to 5χ 1〇13 inserted into the isolation layer 128 may be, for example, gallium arsenide or indium phosphide, and the degree is preferably between 3. One for one. The channel layer 13. The material = is a thickness between 50A InxGaixAs up to 150A, InxGa 丨 xAs with X between 0.05 and 0.3, or thickness between 100A and 300A, x Between 0.3 and 0.7. The material of the isolation layer m may be, for example, indium gallium phosphide (In〇49GaG 5iP), aluminum gallium arsenide (α1χ ^ As), and X is between 0.1 and 1.0. , Indium indium (AlO5InO5P), or indium indium (Al ^ InmAs), etc., and the thickness of the isolation layer 132 is preferably between 30a and 80A. In addition, planar doping The layer 134 is used as a carrier supply layer, and the doping concentration of the planar doped layer 134 is 5 (N +) is preferably between 1x 1〇1] Coffee_2 to this paper size applies Chinese National Standard (CNS) A4 specifications (210X297). -------- (Please read the back Note II, please fill in this page) Order · 557567 Five Intellectual Property Bureau of the Ministry of Economic Affairs printed a description of the invention () 5 × 10 cm2. Schottky contact layer] The material of 1 3 6 may be, for example, indium gallium phosphide

(In〇.49Ga (). 51P), aluminum gallium arsenide (μ G broken mountain abxAs), χ is between 0 ″ to u, aluminum indium (Al〇5ln.5ρ), or # Please read first Note on the back, and then apply Α Shin Huaming Indium (AlG48ln〇.52As), etc., and the thick sound of the Schottky contact layer 136, θ a 9?

The 7 sub is preferably between 100A and 1,000A. The doped 澧 _ a / χτ + of the planar doped layer 13 8 is preferably between 1 × 10101 and 2 × 5 × 1013cm · 2. Imagination 1 / 1Γν & separation layer 1 40 material can be, for example, phosphating

Between 1.0, indium aluminum phosphide (Al〇5lnn, 87% yL • 5 G · 5. Or indium arsenide (Al〇48In〇.52As), etc.) and the thickness of the isolation layer 14G is preferably between 3 The material of the ohmic contact layer 142 may be, for example, a stone with a doping concentration ranging from ΐχ 101, -2 to 1 x 1 0 19 c πΓ2. Indium gallium (In 0 5 3 Ga0 4 7 As), and the thickness of the ohmic contact layer 142 is preferably between 2000A and 5000A. Please refer to f 2 @ '帛 2 _ 系' And% show the corresponding conductive band energy band diagram of a transistor of one of the preferred embodiments of the present invention, where Eρ is a Fermi level. In this embodiment, the material of the buffer layer 1 16 is a thickness of 3 〇 〇InowGaP (Powder Indium GaP); the isolation layer 120 is made of InowGao qP with a thickness of 50; the channel layer 122 is made of InGaGa (Powder) with a thickness of 100. 2Ga〇sAs); the isolation layer 124 is made of gallium arsenide with a thickness of 40a; the isolation layer 128 is made of gallium arsenide with a thickness of 40A; the channel layer 13 is made of indium gallium arsenide (In〇jGao.sAs) with a thickness of 100A ); The isolation layer 132 is made of 50 Filled with indium gallium (Ino.oGamP); and the Schottky contact layer 136 is made of indium gallium phosphide (In〇49 p) with a thickness of 450 people. In this embodiment, the transistor 100 uses InGaP / InGaAs / GaAs dual Layer channel structure, that is, 10 paper sizes are applicable to Chinese National Standard (CNS) A4 specifications (210X297 Gongchu) 557567 A7 B7 V. Description of the invention () Isolation layer 120 / channel layer 122 / isolation layer 124 and isolation layer 132 / channel Layer ^ 0 / isolation layer 丨 28, so thicker and higher indium content of the indium recording material can be used as the channel layer 1 22 and channel layer 丨 3, to achieve improved carrier transmission characteristics and increase the gate operating voltage In addition, the pulse doping plane doping layer i 34, the plane doping layer 126, and the plane doping layer 118 of the upper, middle, and lower three layers are used as the carrier supply layer, so that The carriers in the channel structure are evenly distributed, so that the transistor i⑽ obtains good DC and AC linearity. In addition, a large band gap galvanic material is used as the Schottky contact layer 1 3 6 and the buffer layer 丨 6 , Can also provide good Schottky characteristics and suppression of transistor 100 Shushu leak off the substrate 2 of the element to improve the leakage current characteristics of clipping the other hand, by

The large conduction band discontinuity (AEc) between the interfaces of InGaP / InGaAs (that is, channel layer 122 / isolation layer 120 and channel layer 130 / isolation layer 132) can effectively confine carriers to a two-layer channel structure. This reduces the leakage current during forward bias operation and improves the ability of forward bias operation. In addition, using materials such as gallium with a large band gap as buffer layers 1 16 and Schottky contact layers 1 36, the indium gallium phosphide layer above the channel structure can provide excellent Schottky characteristics of transistor elements. The indium gallium phosphide layer located under the channel structure can suppress the substrate leakage current leaked from the substrate 1 12. Therefore, the pinch-off characteristic of the transistor element can be further enhanced. Please refer to FIG. 3 to FIG. 5 together, where FIG. 3 is a diagram showing a relationship between a gate current (Ig) and a gate-drain voltage (VGD) of a transistor of a preferred embodiment of the present invention. Figure, Figure 4 shows the transistor 11 of Figure 3 (please read the precautions on the back first? This page}-、 一一-口 # · Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

557567 The Intellectual Property Bureau of the Five Ministry of Economic Affairs printed a description of the invention of the Consumer Cooperative of the Consumers (Q-Grade Leakage Current (IGL) vs. Temperature, and Figure 5 shows the gate-drain of the transistor in Figure 3 Voltage (v〇n) vs. temperature. In Figure 3, 'the gate area of the transistor element is χχ 8〇 # ㈤2, and the temperature is 3 00K. From Figure 3, the transistor element of the present invention is known. Have good Schottky characteristics of the gate. When the gate-drain voltage is 15 v, the gate-drain leakage current is at 300K, 330K, 360K, 390K, 420K, 450K, and 480K. 60 # A / mm, 96 / z A / mm, 110 // A / mm, 114 # A / mm, 203 # A / mm, 367 a A / mm, and 600 // A / mm, as shown in Figure 4 On the other hand, at the above temperatures, the corresponding starting voltages are 1.46V, my, 1.38V, 1.35V, 1.31V, 1.25V, and lmv, as shown in Figure 5. The crystal element still has low gate-drain leakage current and high starting voltage at high temperatures. Therefore, this also illustrates that the structural design of the transistor element of the present invention not only has good Schottky characteristics, It is also possible to confine the electrons in the channel layer, reduce the leakage & and increase the breakdown voltage, thereby improving the high temperature characteristics of the device. Please refer to FIG. 6, which illustrates a preferred embodiment of the present invention. The three-terminal characteristic diagram of the common source output current and voltage of the transistor at room temperature. The surface of this transistor element! Χ 8 〇 "m 2, the gate-source voltage (VGS) gap at each stage is · 0.5v 'x critical voltage is 5mv, and the temperature is 300K. "It can be found from the figure that the transistor element of the present invention has good transistor amplification, saturation, and stop characteristics, which clarifies the design. The structure has a good ability to lift the limit of the carrier. In addition, due to the large forward direction, 12 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210X297). 5. Description of the invention () When the pole voltage is at the same time, the line of the transistor element of the present invention is 1.5 to 1.5. The characteristics of the leakage current of the shoulder, please refer to Figure 7 '. Figure 7 shows the transistor in the room. One of the preferred embodiments of the source voltage (VGS) month Relationship diagram, the relationship between agricultural transduction value (gm) and gate-to-gate voltage, and the curve, which represents the relationship between the non-polar saturation current and voltage. The pole area of the pole 2 is as follows: 1x8ο # m2, and the source voltage (Vds) is fixed β Q υ ν, and the degree is 3 0 〇κ. As can be seen from Figure 7, at this time, The Office of the Electronic Crystal _ _ appealed that the maximum output current of the Japanese body components was 460mA / mm, and the maximum value was 162mS / mm. When the linear operating area is defined above the maximum transmissive value of 9G%, the saturation current area of one pole can be greater than 310mA / mm 'and the operating voltage area of the gate and source can be greater than 2V. The device has excellent linear operating characteristics. This also illustrates that by using a double-layered channel structure and the upper 'middle and lower three planar doped layers as the carrier supply layer', the carriers in the channel can be evenly decorated, so the component can be broad In the n-plane of the linear chirp region, the elimination of parallel conduction is operated at a large forward gate-source voltage +2.0 V, and the component still maintains a large transduction value of 135 mS / mm. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to FIG. 8. FIG. 8 shows the transconductance value (gm) and output conductance (gds) of the transistor at room temperature according to a preferred embodiment of the present invention. And voltage gain (Av) versus drain-source voltage (Vl) s), where curve d represents the relationship between transconductance value and drain-source voltage, and curve e represents the output conductance and 13 paper sizes are applicable China National Standard (CNS) A4 specification (210X297 mm) 557567

V. Description of the invention (The relationship between the printed source and the source voltage of the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, ,, M represents the relationship between the voltage gain and the source voltage. This, 2 ―From® The gate area of the component is lx8C. The bias voltage at the gate-source voltage (Vos) is +0.5 V, and the temperature is 300K. As can be seen from Figure 8, the degree of-is ^^, which is better. Carrier confinement capability and low / flat motor 'When the drain-source voltage is large n4l 2 · 5 V, a low output conductance of 0.41 mS / mm' can be obtained in conjunction with a high transduction value i6. ms / mm, you can get a very high voltage gain (Av = gm / gd. Value 390. And because the file of the present invention has a very high voltage gain value ', it is quite suitable for use in amplifier circuits. Please refer to Figure 9, Figure 9 is a green diagram showing the relationship between the frequency characteristics of the crystal and the non-polar current (Id) at room temperature in a preferred embodiment of the present invention. The gate area of 70 transistors of this transistor is lxl0〇 # m2. -The source voltage (Vds) is β, and / Ja degrees is 3 0 0 κ. At this time, when the bias condition is at the drain source voltage is 3.5V, the gate. Source voltage (Vgs) is + 〇 · 2 Under 5 v, its maximum unit current gain cut-off frequency (Unity Current Gain Cut_off FreqUenCy (/ τ)) is 13GHz, and the maximum oscillation frequency (Maximum Oscnllation Frequency; / max) is 32GHz, so it can be known that this transistor το component has Quite good frequency performance. Similarly, because the carriers in the channel can be evenly distributed, the element of the present invention also maintains a wide and linear frequency performance, as shown in Figure 9, when the drain current is 60 to 3 When the operating range is 60mA / mm, the frequency operating characteristics of this transistor element remain above 90% of its maximum unit current gain cut-off frequency and maximum oscillation frequency value. This also shows that the transistor element of the present invention is quite suitable for 14 papers. Standards are applicable to China National Standard (CNS) A4 specifications (210X297 mm) (Please read the precautions on the back before this page) '! · Binding · Order · 557567 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives V. Inventions Description (Suitable for the application of high-frequency circuits. To sum up ... the present invention has a double-layer channel structure of the proposed mobility-increasing transistor not only has low leakage current, The advantages of output conductance, profit, and excellent frequency performance have the advantages of wide and linear flow and AC operation area. Therefore, it is very suitable for microwave ... communication, microelectronics, and optoelectronics fields and industries, such as optical J Communication Department, · Power amplifiers, portable communication equipment, anti-collision radar, satellite communication, and regional wireless communication networks, etc. As understood by those familiar with this technology, the above is only a good idea of the present invention The examples are not intended to limit the patent application scope of the present invention, and any other equivalent alterations or modifications that have been made without departing from the spirit disclosed by the present invention should be included in the scope of the patent application described below. Brief description of the round form: The preferred embodiment of the present invention has been described in more detail in the preceding explanatory text with the following figures, of which: Figure 1 shows a preferred embodiment of the present invention with a double layer A cross-sectional view of a pseudo-crystalline high electron mobility transistor with a channel structure; FIG. 2 is a diagram showing a corresponding conductive band energy band of a transistor according to a preferred embodiment of the present invention; FIG. 3 is a diagram showing the present invention Zhi_Ling 4 Lian Nai (The relationship between the gate current (iG) and the gate-drain voltage (Vgd) at both ends of the transistor of the Jia Jiaguan example; Figure 4 shows the transistor of Figure 3 The relationship diagram of the gate leakage technician's temperature; crystalline high voltage 孑 15 557567 A7 ------- B7 V. Description of the invention () ~ "--Figure 5 shows the transistor of Figure 3 Gate-drain starting voltage (v ..) vs. temperature; Figure 6 shows a preferred embodiment of the present invention. The common source output current of the transistor at room temperature-voltage three Terminal characteristics diagram; FIG. 7 is a drawing showing the saturation current (IDS) and transconductance value (gm) of the transistor at a room temperature according to a preferred embodiment of the present invention. Relation diagram of voltage (ν〇; Figure 8 is a graph showing the transconductance value (gm), output conductance (gds) and voltage gain vs. source of the transistor at room temperature of a preferred embodiment of the present invention) The relationship diagram of voltage (VD s); and FIG. 9 is a diagram showing the relationship between the frequency characteristics of the transistor and the drain current (ID) at room temperature according to a preferred embodiment of the present invention. Printed by the Intellectual Property Bureau Staff Consumer Cooperative 100 Transistor 1 12 Substrate 1 14 Buffer layer 116 Buffer layer 118 Plane doped layer 120 Isolation layer 122 Channel layer 124 Isolation layer 126 Plane doped layer 128 Isolation layer 130 Channel layer 132 Isolation layer 134 planar doped layer 136 Schottky contact layer 138 planar doped layer 140 isolation layer 142 ohmic contact layer 144 source 146 drain 148 gate 16

557567 A7 B7 V. Description of the invention (150) Opening a Curve b Curve C Curve d Curve e Curve f Curve (Please read the precautions on the back before writing this page), τ Printed by the Employees ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 17 This paper size applies to China National Standard (CNS) A4 (210X297 mm)

Claims (1)

557567 VI. Application scope ABCD 1. A pseudomorphic high electron mobility transistor (PHEMT) with a double channel structure, at least: The substrate includes at least one undoped first buffer and An undoped second buffer layer is located on the first buffer layer and the base layer is located on the punching layer; a first first first second plate, wherein the substrate is doped with one channel junction in one plane and two channel junctions in one plane One of the three plane doped layers and one fourth plane doped layer expose one of the other undoped portions of the first ohmic contact layer 'source and-a gate electrode located on the doped layer on the second buffer layer; On the first plane doped layer; on the first channel structure; on the second plane doped layer; on the second channel structure; on the third plane; On the doped layer; the heterolayer is located on a part of the Schottky contact layer, and the Schottky contact layer; an isolation layer is located on the fourth plane doped reed · on the first isolation layer; Located in part of that J々 the ohmic contact; and the exposure of the Schottky contact layer. (Please read the precautions on the back first, then this page}-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2. As described in item 1 of the scope of patent application, there are one and nine channels of quasi-crystalline high electrons Mobility rate transistor, in which the substrate-board. Semi-discontinued 18 This paper size applies to Chinese National Standard (CNS) A4 (210x297 mm) 557567 A8 B8 C8 D8 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, application Patent scope 3. The quasi-crystalline high electron mobility transistor having a double-layer channel structure as described in item 2 of the scope of patent application, wherein the material of the substrate is gallium arsenide (GaAs) 〇4. The quasi-crystalline high electron mobility transistor with a double-layered channel structure as described in item 2, wherein the material of the substrate is indium phosphide (InP) ° 5. The double-layered channel as described in item 1 of the scope of patent application Structure of a pseudo-crystalline high electron mobility transistor, in which the material of the first buffer layer is gallium sulfide. 6. The pseudo-crystalline high electron mobility with a double-layer channel structure as described in item 1 of the scope of patent application. Rate transistor, The material of the first buffer layer is filled with indium. 7. The quasicrystalline high electron mobility transistor having a double-layer channel structure as described in item 1 of the scope of patent application, wherein the thickness of the first buffer layer is between Between 0.1A and 5.0 // m. 8. The quasi-crystalline high electron mobility transistor having a double-layer channel structure as described in item 1 of the scope of patent application, wherein the material of the second buffer layer is (Please read the precautions on the back first, then this page). · Τ #. This paper size is applicable to China National Standard (CNS) A4 (210 × 297 mm) 557567 ABCD VI. Patent application scope Indium gallium phosphide (InG.49Ga () .51P). 9. The quasicrystalline high electron mobility transistor having a double-layered channel structure as described in item 1 of the scope of the patent application, wherein the material of the second buffer layer is aluminum gallium arsenide (AlxGa! _xAs), and X is between 0.1 and 1.0. 10. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 1 of the scope of patent application, wherein the material of the second buffer layer It is a scaled-type gallium (Al〇5Ga〇5P). 1 1. It has A pseudo-crystalline high electron mobility transistor with a double-layered channel structure, in which the material of the second buffer layer is Shi Shenhua Ming Indium (Al048lnG 52As). 12. It has a double-layered channel as described in item 1 of the scope of patent application. Structure of a pseudo-crystalline high electron mobility transistor, in which the thickness of the second buffer layer is between 200 A and 5000 A. Fan Wei Li specially requested to print the binding structure of the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The layered bilayer doped layer has two items described in the above description. The volume of the bulk crystal electricity and the high-speed crystallinity of the mover should be provided for one sub-101 -V3 X. This should be m to the degree of concentration. 〇 # 间 之 之 层 2 Miscellaneous-cm Doped with 13 sides 10 Flat X Yujie \ — / + N 20 This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 557567 A8 B8 C8 D8 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economy Application for patent scope 1 4. As described in item 1 of the patent scope Layered channel structure pseudo-crystalline high electron mobility transistor, wherein the first channel structure further includes at least: an undoped second isolation layer on the first planar doped layer; an undoped first A channel layer is located on the second isolation layer; and an undoped third isolation layer is located on the first channel layer. 1 5. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 14 of the scope of the patent application, wherein the material of the second isolation layer is filled with steel (Ino 5iP). 16. The quasicrystalline high electron mobility transistor having a double-layered channel structure as described in item 14 of the scope of patent application, wherein the material of the second isolation layer is aluminum gallium arsenide (AlxGabXAs), and X Between 0.1 and 1.0. 1 7. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 14 of the scope of the patent application, wherein the material of the second isolation layer is indium aluminum phosphide (AlO5In0.5P ). 1 8. The pseudo-crystalline high electron mobility transistor having a double-layer channel structure as described in item 14 of the scope of the patent application, wherein the material of the second isolation layer is Shi Shenhua, Lu Indium (AlO, 48ln 0.52As). 21 This paper size is in accordance with China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before this page) 557567 ABCD Six Intellectual Property Bureau of the Ministry of Economy Staff Consumer Cooperatives Scope of application for patents 1 9. The quasicrystalline high electron mobility transistor having a double-layered channel structure as described in item 14 of the scope of the patent application, wherein the thickness of the second isolation layer is between 30 and 80 people. 20. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 14 of the scope of the patent application, wherein the material of the first channel layer is indium gallium (InxGa) -xAs, and X is between 0.05 and 0.3. 2 1. The quasicrystalline high electron mobility transistor having a double-layered channel structure as described in item 20 of the scope of the patent application, wherein the thickness of the first channel layer is between 50 A and 150 A. 22. The quasicrystalline high electron mobility transistor having a double-layered channel structure as described in item 14 of the scope of the patent application, wherein the material of the first channel layer is InxGai_xAs, and X is between Between 0.3 and 0.7. 23. The quasicrystalline high electron mobility transistor having a double-layered channel structure as described in item 22 of the scope of patent application, wherein the thickness of the first channel layer is between 100 A and 300 persons. 24. The pseudo-crystalline high electron mobility transistor having a double-layered channel structure as described in item 14 of the scope of the patent application, wherein the material of the third isolation layer is gallium arsenide. (Please read the precautions on the back first, and then this page.) Packing # This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ABCD 557567 VI. Application for patent scope 25. Such as the scope of patent application No. 14 The pseudo-crystallized high electron mobility transistor having a double-layered channel structure is described, in which the material of the third isolation layer is scaled indium. 26. The pseudo-crystalline high electron mobility transistor having a double-layered channel structure as described in item 14 of the scope of the patent application, wherein the thickness of the third isolation layer is between 30 A and 80 A. 27. The pseudo-crystalline high electron mobility transistor having a double-layered channel structure as described in item 1 of the scope of the patent application, wherein the second planar doped layer is a carrier supply layer and the second planar doped layer The doping concentration δ (N +) is between 1 X lO ^ cnT2 and 5x 1013 cm · 2. (Please read the precautions on the back before filling this page.) Fan Wei Li specially requested to apply the structure to the junction, the structure, the junction, and the double-pass. There are two items in the description, and the 1-body crystal rate. The high-level crystal structure of the transferor is similar to the upper and lower layers. 〇The upper and upper doped layers are separated from the channel by two-fourth-second Xuanhaihaishi | 口 φφ = 口 于 于 位 位 砠 ㉟ Separation of X1 · ^ 0 0 S of 11th of 11th of 225th: Sampling and printing is not included, but it is printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. There are four items in the through layer of the material path, which are described in the above description. The 8 S 2 spectrum crystallographic rate shifter is highly crystallized. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297). (Mm) ABCD 557567 6. The scope of patent application is gallium arsenide. (Please read the precautions on the back before filling this page) 3 0. The pseudo-crystallized high electron mobility transistor with double-layer channel structure as described in item 28 of the scope of patent application, in which the material of the fourth isolation layer For filling indium. 3 1. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 28 of the scope of patent application, wherein the thickness of the fourth isolation layer is between 30 A and 80 A. 3 2. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 28 of the scope of patent application, wherein the material of the second channel layer is InxGa and XAs, and X is between 0.05 and 0.3. 3 3. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 32 of the scope of patent application, wherein the thickness of the second channel layer is between 50 A and 150 A. 34. The pseudo-crystalline high electron mobility transistor having a double-layered channel structure as described in item 28 of the scope of patent application, wherein the material of the second channel layer is InxGai-xAs, and X Between 0.3 and 0.7. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 35. The pseudo-crystalline high electron mobility transistor with a double-layer channel structure as described in item 34 of the scope of patent application, wherein the thickness of the second channel layer is applicable to this paper Chinese National Standard (CNS) A4 specification (210X297 mm) 557567 ABCD 々, patent application range is between 100 A to 300A. 3 6. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 28 of the scope of patent application, wherein the material of the fifth isolation layer is filled with indium gallium (Ino.49Gao.51P). 3 7. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 28 of the scope of patent application, wherein the material of the fifth isolation layer is aluminum gallium arsenide (AlxGa ^ xAs), and X is between 0.1 and 1.0. 3 8. The pseudo-crystallized high electron mobility transistor having a double-layered channel structure as described in item 28 of the scope of patent application, wherein the material of the fifth isolation layer is aluminum indium phosphide (Al0.5.In.0.5P ). 39. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 28 of the scope of the patent application, wherein the material of the fifth isolation layer is Shi Shenhua in Lu Yin (Al〇48ln〇.52As ). (Please read the precautions on the back before filling out this page) Shenru, Intellectual Property Bureau, Ministry of Economic Affairs, Employee Consumption Cooperative, printed electrical high-quality C day 0a3, the plan is to pass from A to A structure, and there are five layers separated from each other. With the items mentioned in this description, 28 体 晶 第 电 围 率 傻 勤 # A Requisition Room A Fan Li specially applies for the items described in the construction of the road through the double layer 5 2 This paper scale Applicable to China National Standard (CNS) A4 specifications (210X297 mm) 557567 A8 B8 C8 --- D8 VI. Application scope of patents (please read the notes on the back before filling this page) Crystal, wherein the third plane doped layer is a carrier supply layer and the impurity doping concentration of the third plane doped layer (5 (N +) is between 1 X 1〇Η (: πΓ2 to 5x 1013em- 2. Between 42. The pseudo-crystalline high electron mobility transistor having a double-layered channel structure as described in item 1 of the scope of the patent application, wherein the Schottky contact layer is made of indium gallium (InG.eGao) 51P >. 43 · Double layer as described in item 1 of the scope of patent application The pseudo-crystalline high electron mobility transistor of the channel structure, in which the Schottky contact layer is made of aluminum gallium arsenide (AlxGabxAs), and X is between 0.1 and 1.0. 4 4. The pseudo-crystalline high electron mobility transistor having a double-layer channel structure as described in the first item of the patent scope, wherein the material of the Schottky contact layer is indium aluminum phosphide (Al0.5InQ 5P). 4 5 · 如The pseudo-crystalline high electron mobility transistor with a double-layered channel structure described in item 1 of the scope of the patent application, wherein the material of the Schottky contact layer is aluminum indium arsenide (AlG.48In () 52As). Printed by the Intellectual Property Bureau's Consumer Cooperatives 4 6 · Pseudocrystalline high electron mobility transistor with double-layer channel structure as described in item 1 of the scope of patent application, where the thickness of the Schottky contact layer is between 100A and 1 000A. 26 This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) ABCD 557567 6. Scope of patent application (please read the precautions on the back before filling this page) 47. Pseudocrystallinity with double-layer channel structure as described in item 1 Electron mobility transistor, in which the doping concentration 5 (N +) of the fourth plane doped layer is between 1 × ΙΟ11. !!! · 2 and 5x 1013cm · 2. The pseudo-crystallized high electron mobility transistor having a double-layer channel structure, wherein the material of the first isolation layer is a filled indium (Ino.49Gao.51P). 49. The pseudo-crystalline high electron mobility transistor having a double-layered channel structure as described in item 1 of the scope of the patent application, wherein the material of the first isolation layer is aluminum gallium arsenide (AlxGabxAs), and X Between 0.1 and 1.0. 50. The pseudo-crystalline high electron mobility transistor having a double-layered channel structure as described in item 1 of the scope of the patent application, wherein the material of the first isolation layer is aluminum indium phosphide (Al0.5.In.5P) . 5 1. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 1 of the scope of the patent application, wherein the material of the first isolation layer is Shi Shenhua Shao Indium (Al0.48ln. 52As). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5 2. The quasi-crystalline high electron mobility transistor with a double-layer channel structure as described in item 1 of the scope of patent application, wherein the thickness of the first isolation layer is on the paper scale Applicable to China National Standard (CNS) A4 specification (210X297 mm) ABCD 557567 々, patent application range is between 30 A to 80A. (Please read the notes on the back before filling this page) 5 3. The quasicrystalline high electron mobility transistor with double-layer channel structure as described in item 1 of the scope of patent application, where the material of the ohmic contact layer is GaAs. 54. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 1 of the scope of the patent application, wherein the material of the ohmic contact layer is Shishenhua Yingsu (Ino.53Gao.47As). 5 5 · The quasi-crystalline high electron mobility transistor with a double-layer channel structure as described in item 1 of the scope of the patent application, wherein the thickness of the ohmic contact layer is between 200 A and 5000 people. 56. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 1 of the scope of patent application, wherein the doping concentration of the ohmic contact layer is between lx 1018 cm · 2 and lx 1019 cm_2 . Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 57. The pseudo-crystalline high electron mobility transistor with a double-layer channel structure as described in item 1 of the scope of patent application, wherein the source and drain materials are gold (Au) / Ge (Ge) / Ni (Ni) stack. 5 8. Double-layer channel structure as described in item 1 of the scope of patent application 28 This paper size applies to China National Standard (CNS) A4 (210X 297 mm) 557567 I pseudomorphic south electron A i-mobility transistor, wherein the material of the gate electrode is selected from the group consisting of aluminum, titanium (Th, pin (Mo), uranium (Pt), gold and its alloy titanium / gold, (Please read the notes on the back before filling out this page) 59. —Special pseudo-crystalline high electron mobility f crystals with a double-layered channel structure, including at least : A substrate; an unmodified one ^ first ^ λ ^. 〇 brother buffer layer is located on the substrate; one undoped 筮 -Laye a, a brother buffer layer is located on the first buffer layer; a plane The doped layer is located on the second buffer layer; a double-layered channel structure is located on the first planar doped layer, wherein the double-layered channel structure includes at least: a first channel structure, including at least: an undoped first An isolation layer is located on the first planar doped layer; a non-doped first channel layer is located on the first isolation layer; and a non-doped second isolation layer is printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Located on the first channel layer; a second planar doped layer is located on the first On an isolation layer; and a first channel structure, at least comprising: an undoped third isolation layer on the second planar doped shoulder; an undoped second channel layer on the third isolation layer; 》 29 This paper size applies to China National Standard (CNS) A4 specification (210X297 public love) 557567 ABCD 6. Scope of patent application and (Please read the precautions on the back before filling this page) One of the undoped fourth isolation layer is located On the second channel layer; a second planar doped layer on the fourth isolation layer; an undoped Schottky contact layer on the third planar doped layer; a fourth planar doped layer on A part of the Schottky contact layer is exposed, and another part of the Schottky contact layer is exposed; an undoped fifth isolation layer is located on the fourth plane doped layer; an ohmic contact layer is located on the fifth On the isolation layer; a source and a drain are located on part of the ohmic contact layer; and a gate is located on the exposed Schottky contact layer. Layer crystal structure An electron mobility transistor, in which the substrate is a semi-insulating substrate and the material of the substrate is selected from the group consisting of gallium arsenide and indium phosphide. Printed by Jue Gong Consumer Cooperative, Bureau of Intellectual Property, Ministry of Economic Affairs 6 1 · The pseudo-B-type southern electron mobility transistor having a double-layered channel structure as described in item 59 of the scope of the patent application, wherein the material of the first buffer layer is selected from the group consisting of gallium arsenide and indium phosphide Form a group, and the thickness of the first buffer layer is between 0.01 and 5.0 # rn. 62. The quasi-crystalline high-electron movement with a double-layered channel structure as described in item 59 of the scope of patent application Rate transistor, in which the material of the second buffer layer is in accordance with China National Wood Standard (CNS) A4 specification (210x297 public love) 557567 ABCD 6. Scope of patent application (please read the precautions on the back before filling this page) It is selected from the group consisting of indium gallium indium (In〇49Ga0.5iP), aluminum gallium arsenide (AixGai · xAs), x between 0.005 and 10, aluminum gallium phosphide (Ai〇5 () a〇5p), and a group of Albino nAs, and the second The thickness of the buffer layer is between 200 and 5000 people. 63. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 59 of the scope of patent application, wherein the first planar doped layer is a carrier supply layer, and the first planar doped layer The doping concentration 5 (N +) is between 1 X 1011 cnT2 and 5x loBcm-2. 64. The pseudo-crystalline high electron mobility transistor having a double-layered channel structure as described in item 59 of the scope of the patent application, wherein the material of the first isolation layer is selected from the group consisting of indium gallium phosphide (In〇49Ga. 51p), aluminide I Lu Ga (AixGai · xAs), X between 〇 · ι to 丨 〇, indium aluminum phosphide (A1 05ln〇5p), and Shi Shenhua Ming indium (Alo.qlno 52As) A group, and the thickness of the first isolation layer is between 30 A and 80 A. Printed by the Employees ’Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs 65. The pseudo-crystalline high electron mobility transistor with a double-layered channel structure, as described in item 59 of the scope of patent application, where the material of the first channel layer is a thick dielectric InxGaAs xAs at 50 A to 150A, and X is between 0.05 and 0.3. 66 · Double-layer channel structure as described in item 5 and 9 of the scope of patent application 31 This paper size applies to China National Standards (CNs) A4 (210X297 mm) 557567 6. The date of application for the scope of the patent application: the birth of the same electron mobility transistor, in which the material of the first channel layer is a deified indium gallium (lnxGaixAs) with a thickness of 100A to 300A, and χ introduces Between 0.3 and 0.7. 67. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 59 of the patent scope of Shenyin, wherein the material of the second isolating layer is self-made by gallium arsenide and indium phosphide Forming a group, and the thickness of the second isolation layer is between 30 A and 80 A. 68. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 59 of the scope of patent application, wherein the second planar doped layer is a carrier supply layer and the second planar doped layer The doping concentration 5 (N +) is between 1 × 10 ncnT2 and 5 × loUcmJ. 6 9. With double-layer passage as described in item 59 of the scope of patent application ......... 1® ^ ......... Order (Please read the precautions on the back before filling this page ) A pseudo-crystalline high electron mobility transistor printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, wherein the material of the third isolation layer is selected from the group consisting of gallium arsenide and indium phosphide, and the The thickness of the third isolation layer is between 30A and 80A. 70. The quasi-crystalline high electron mobility transistor having a double-layered channel structure as described in item 59 of the scope of patent application, wherein the material of the second channel layer is indium gallium arsenide (InxGaHAs) with a thickness of 50A to 150A. ), And X is between 0.05 and 0.3. 32 This paper size applies to China National Standard (CNS) A4 (210X297 mm) 557567 ABCD 6. Scope of patent application 7 1 · Pseudocrystalline high electron mobility transistor with double-layer channel structure as described in item 5 and 9 of the scope of patent application, in which the material of the second channel layer c, please read the note on the back first Please fill in this page again for the InxGahxAs with thickness between 100 A and 300A, and ^ X between 0.3 and 0.7. 72. The quasi-crystalline south electron mobility transistor having a double-layered channel structure as described in item 59 of the scope of the patent application, wherein the material of the fourth isolation layer is selected from the group consisting of indium gallium phosphide (In〇49Ga. .5iP), aluminum gallium arsenide (AlxGai xAs), X between 0 · ΐ to 丨 〇, indium aluminum phosphide (Al〇'5In0.5P), and Shi Shenhua indium (AlmlnouAs) A group, and the thickness of the fourth isolation layer is between 30 A and 80 A. 7 3 · The pseudo-crystalline high electron mobility transistor having a double-layered channel structure as described in item 5 of the scope of the patent application, wherein the third plane doped layer is a carrier supply layer, and the third plane doped layer The doping concentration 5 (N +) of the impurity layer is between JX 1011 cm · 2 and 5 × 1013cnr2. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 74. The pseudo-crystalline high electron mobility transistor with a double-layer channel structure as described in item 59 of the scope of patent application, wherein the material of the Schottky contact layer is selected from Indium gallium phosphide (In.49Ga0.5iP), aluminum gallium arsenide (AixGai_xAs), X is between 0.1 and ι · 〇, scaled aluminum indium (Al〇5In〇5p), and arsenic A group of aluminum indium (eight 10.4 8 111 (). 5 2 eight 3), and this Schottky contact 33 This paper size applies to China National Standard (CNS) A4 (210X297 mm) 557567 A8 B8 C8 D8 The thickness of the patent application layer is between 100A and ιοοοΑ f Please read the notes on the back before filling out this page} 7 5 · Double-layer channel structure as described in item 5 of the patent application scope A pseudo-crystalline high electron mobility transistor, in which the doping degree (5 (N +)) of the fourth planar doped layer is between 1x10llcm-2 and 5x10i3cm-2. 76. If applied The pseudo-crystalline high electron mobility transistor having a double-layer channel structure as described in item 59 of the patent scope, wherein the fifth isolation layer The material is selected from the group consisting of indium gallium phosphide (Ino.oGao.siP), aluminum gallium arsenide (AlxGai 'X between 0 "to 10), indium aluminum phosphide (Ai〇5ln〇5p), and stone A group consisting of Shenhua Shao Indium (Albino · 52 As), and the thickness of the fifth isolation layer is between 30A and 80A. 77. The double-layered channel structure as described in item 59 of the scope of patent application Pseudocrystalline high electron mobility transistor, in which the material of the ohmic contact layer is selected from the group consisting of Shishenhualu with doping concentration between lx 1018cnT2 and lx l〇i9cm-2, and indium gallium (InG ηGaG οAS) ), And the thickness of the ohmic contact layer is between 200A and 5000A. Printed by the Consumer Consumption Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs 7 8 · Double-layered as described in item 5 of the scope of patent application Quasicrystalline high electron mobility transistor with channel structure, in which the source and the drain are made of gold / germanium / nickel stack. 34 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) 557567 A8 B8 C8 D8 patent application scope The pseudo-crystalline high electron mobility transistor of the channel structure, wherein the material of the gate electrode is selected from the group consisting of aluminum, titanium, molybdenum, platinum, gold and its alloys titanium / gold, and You / gold. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210X297 mm)