TW557492B - Method for correcting optical proximity effect - Google Patents

Abstract

A kind of method for correcting optical proximity effect is disclosed in the present invention and is applied in photolithography process. The photolithography process is applied in manufacture of integrated circuit. The invented method includes the following steps: providing an integrated circuit design figure that has a line-width value and a pitch value; obtaining a corresponding relationship between the exposed line-width and the exposure value as well as the defocus value under the line-width and the pitch; finding the process window of the IC design figure according to the corresponding relationship and the permitted upper limit and the lower limit of the exposed line-width; finding the line-width exposed at the center point of process window based on the corresponding relationship; using the line-width exposed at the center point of process window as the target and using the conventional optical proximity effect correction method to correct the IC design figure; and transferring the corrected IC design figure to the mask.

Description

557492 Five 'invention description (1) The present invention is related to a method of optical proximity effect correction, in particular, a new method of optical proximity effect correction & The exposures of the center points of the process windows of the graphics are all the same, then the largest common process window will be obtained. As the size of semiconductor devices shrinks, the exposure tolerance xposure latitude and depth of focu ^ decrease simultaneously, and the control capability of the semiconductor lithography process becomes increasingly important. In order to expose a photoresist pattern with a precise line width, a stepper or sCanner must be able to accurately focus (this includes controlling the imaging lens group ..., the distance and the distance between the imaging lens group and the wafer Distance) and the large exposure control 2 1 If the focus is not accurate or the exposure is changed during exposure, the exposed line width of the photoresistor will change. The line width can be obtained through simulation or experiment according to the exposure or defocus. As shown in the i-th graph, plot the line-exposure and defocus (contour map), and give the line width specification value ^ difference "°, then corresponding, the line width. ⑽ and w.-". The area surrounded by the defocus plane of the curve is defined as the allowable exposure amount = small and defocus range (actually, in Figure 丨 (the same is true for Figures 2, 3, 4, and 5)), we The line width is different from the selected image intensity threshold Or ^ ens / ty threshold; that is, when the intensity of the image exceeds the threshold, the two agricultural exposures: the image will be developed. The selected image will be developed. Image strength III ^ Meat: the reciprocal of the required exposure) and defocus mapping). Generally, the bounding rectangle within the range is defined as the process window of the feature graphic W =): That is, if the exposure amount or defocus is only within the range of the process window 1, the exposed line width must conform to the process specification. Especially worth it

557492 5. Description of the invention (2) Note that the shape of this area is not symmetrical up and down, so the line width value corresponding to the center point of process window 1 is not equal to its specification value%. And for the characteristic patterns of different periods, the shape of this area is also very different. Take the copper process metal wire as an example (damascene pr0cess, the metal wire forms a trench for photoresistance after development). For dense lines with a small period, the shape of this area is slightly curved, so in the process window " The line width value of the center point is smaller than the line width specification value, as shown in Figure 1. For sparse lines with a larger period, the shape of this area is extremely curved (even with the sub-resolution assist feature, When using off-axis illumination to increase the focal depth of the main graphics, please refer to K. Wong, Resolution Enhancement Techniques in Optical Lithography, SPIE Press, pp. 97 (2001)) The same is true), so the line width value at the center point of process window 1 is greater than the line width specification value, as shown in Figure 2. For the characteristic pattern of a specific period, when the line width on the mask is changed, the shape of this area does not change significantly, but it is only shifted up and down in the exposure level-defocus plane (please compare the difference between Figure 2 and Figure 4) ). In terms of the most advanced lithography process at present, the wavelength of the light source used is smaller than the line width to be exposed (for example, the lithography of the 0. 18 micron generation is currently performed using a 0.28 micron light source. The process uses 0.13 micron light source for 0.13 micron and 0.10 micron generation lithography process), so the optical proximity effect (OPE) is very significant. That is, the feature patterns with the same line width but different periods on the reticle have different line widths exposed on the wafer. In order to make the characteristic patterns of different periods

0503-6378TW; TSMC2001-0272; Vincent.ptd Page 5 557492

Under the same exposure, the same line width is exposed, and optical proximity correction (oPC) must be performed on the photomask. That is, 'change the line width of the feature patterns on the photomask at different periods so that the photoresistance line widths of these feature patterns exposed on the wafer are equal. 5 There are currently two ways to correct optical proximity effects, one is rule-based and the other is model-based. Regardless of whether it is regular or model, a test mask must first be designed. The test mask includes a representative test pattern that is as complete as possible under the semiconductor generation. Taking a one-dimensional graph as an example, the test pattern contains various combinations of line widths under different periods. The pattern on the test mask is exposed on the wafer, and then the photoresistance line width under a certain exposure and a certain defocus is measured to find the photomask required to expose the photoresistance specification line width in each cycle. Line width size. Based on this experimental negative material, a lookup table is established. Regular optical proximity effect correction is based on this lookup table and CAD tools (for example: Mentor Graphics

Calibre or Hercules of Avant!) For correction of graphics on product masks. The disadvantage of regular correction is that if the mask pattern to be corrected is not in the look-up table, it will cause omission, and it can only consider the effect of the nearest pattern. Based on this, there is a model-type optical proximity effect correction. The model optical proximity effect correction also needs to use the experimental results of the test mask, but he is

The experimental results are used to correct a model. After correction, the model can predict the imaging of various patterns on the photoresist of various products on the photoresist. Therefore, when the optical proximity effect is corrected, the model calculates the size of the correction required for each pattern. To be corrected. With today's increasingly difficult to control semiconductor processes,

557492 V. Description of the invention (4) It is not possible to guarantee the same exposure and defocus for each exposure during the filming process. Therefore, the size of the common process window is very important, it has a direct impact on the yield of the product. The main job of a lithography process engineer is to maximize the common process window for each lithography level. ^ The traditional method of correcting the optical proximity effect is to expose the characteristic patterns of different periods with the same line width as the original design (usually, the minimum line width allowed by the design rules is the main consideration). From the above analysis, it is known that the upper and lower limits of the line width of the feature patterns in different periods are different in the shape of the area surrounded by the exposure amount_defocus plane. If the line width on the reticle is adjusted so that the line widths of the center points of the process windows of the feature graphics in different cycles are the same, then the common process window of the feature graphics in different cycles (the upper and lower limits of the line width of the feature β graphics in each cycle) The enclosing rectangle inside the common area) will become smaller: the common process window 5 shown in Figure 5. In order to solve the above problem, the present invention provides a new correction method. If the line width on the mask is adjusted so that the exposure of the center point of the feature pattern in different periods is the same, the largest common process will be obtained. Window υ 〇 The first object of the present invention is to provide a method for correcting optical proximity effects, including the following steps: providing an integrated circuit design pattern 2-exposing the upper and lower limits of the line width, the integrated circuit design The graphic has a line width value and a space value; obtained under the line width value and the space value, an output width value and an exposure amount and _ away from the first ,,,, and the matching line allowable upper limit of the exposed line width and Find a process window of the integrated design graphic at the lower limit; find out the process window based on the corresponding relationship

Hi Page 7 0503-6378TW; TSMC2001-0272: Vincent.ptd 557492

Water exposure t: the exposed line width value of the point; provide a lookup table; according to the lookup table, a correction value _ corresponding to the exposed line width value of the center point of the process window is used to correct the product with the correction value The bulk circuit design pattern; and transferring the modified integrated circuit design pattern to a photomask. The second object of the present invention is to provide a 6ΐ 丄 of optical proximity effect correction, including the following steps: providing an integrated circuit design pattern and an exposure, wide allowable upper limit and lower limit value, the integrated circuit design pattern has a line The width and spear spacing value, to obtain an exposure line under the line width value and the spacing value. ^ Value, one of the corresponding relationship between the exposure setting and a defocus value; according to the corresponding relationship, "a" the exposed line Wide allowable upper limit and lower limit to find the integrated circuit design _ design pattern-process window σ; according to the corresponding relationship to find the exposed line width value at a center point of the process window; provide a query table and a Experimental model; use the lookup table to modify the experimental model; bring the exposed line width value of the center point of the process window to the modified experimental model to obtain the _corrected value; use the corrected value to modify the integrated circuit design Graphics; and transferring the revised integrated circuit design graphic to a photomask. "The third object of the present invention is to provide a method for optical proximity effect correction, including the following steps: providing an integrated circuit design graphic An exposed upper and lower limit of the line width is allowed. The integrated circuit design graph has a line width value and a complex spacing value. Obtain an exposure _ = line width value and Correspondence between -exposure amount and -defocus value; find out the multiple process windows of the integrated circuit design graphic according to these correspondences with the allowable upper and lower limit of the exposed line width; adjust each interval value The product.The line width value of the circuit design graph makes the complex center points of the process windows

557492 V. Description of the invention (6) " --- The corresponding exposure amounts are aligned with each other; according to the corresponding relations, find out the exposure line width values of the center points of the windows and the systems; provide a A lookup table; according to the lookup table, a plurality of correction values corresponding to the exposed line width values of the center points of the process windows are found; the integrated circuit design graphics are corrected with the correction values; and the corrected The integrated circuit design graphics are transferred to a photomask. A fourth object of the present invention is to provide a method for correcting an optical proximity effect, including the following steps: providing an integrated circuit design pattern and an exposed upper and lower limit value of a line width, the integrated circuit design pattern having a complex line width Values and complex spacing values; get the corresponding relationship between an exposed line width value and an exposure amount and a defocus value at each line width value and each spacing value; the lines that are matched or exposed according to these correspondence relationships Wide allowable upper limit and lower limit value to find the complex process window of the integrated circuit design pattern; adjust ^ a distance value = each line width value of the integrated circuit design pattern makes the complex center points of the process windows correspond to the The exposure amounts are aligned with each other; the line width values of the exposures at the center points of the process windows are found according to the corresponding relationships; a look-up table and an experimental model are provided, and the look-up table is used to modify the experimental model; The exposed line width values of the center points of the process windows are brought into the modified experimental model to obtain a complex correction value; the integrated circuit design graphic is corrected with the correction values; and After the correction of the integrated circuit design pattern transferred onto a reticle. Embodiment FIG. 6 is an integrated circuit design pattern used in this embodiment. The integrated circuit design pattern includes a main pattern 61 and a sub-analysis auxiliary pattern 62. Main picture

0503-6378TWF; TSMC2001-0272; Vincent.ptd Page 9 557492 V. Description of the invention (7) Shape 61 contains dense graphics (top left) and shape (bottom right) with smaller periods. The sub-analysis auxiliary graphics 62 will not be exposed to increase the focal depth of the main graphics 61 (when using off-axis illumination optics = Ϊ The result is taken as an example to illustrate this-new, when consistent. Here we want to The line width is 〇13. The micron groove trench-trench maximizes the common process window in all cycles. The degree is + -10%, that is, the line thickness of the founding officer is unexpected. The allowable line width of half ^ ^ ^ jin is from 0.117 micrometers to 0143 micrometers. For the sake of simplicity, only consider grooves with a period of 〇 · = 嶋 (sparse pattern). For the period ', groove, right The line width on the reticle is 0.30 micron (ιχ, the actual line width on the light is 4,5X, which is 4 * 〇 · 13〇 = 〇 · 520 microns or 5 * 0 · ^^ microns, in order For simplicity, the following lines are used to indicate the lines on the photomask. The manufacturing window is shown in Figure 1. From Figure 1, it can be seen that the threshold energy value (threshold, and The exposure is related to ^ 36. Under the energy corresponding to this critical value, the line width on the photomask with a width of 0.1 micron is exposed on the wafer as 0. · 1 2 6 microns, less than its specification value. For grooves with a period of 1 000 microns, add a line width of 0 · 270 m from the main pattern (the center point of the main pattern to the center point of the auxiliary pattern). ^) 0 micron sub-analysis auxiliary graphics, in order to align the critical value of the energy at the center point of the process window with the 0.240 micron groove, the line width on the photomask must be changed from 0.13. Micron increased to 0.144 micron, at this time his co-process window with 0.240 micron will reach the maximum, as shown in Figure 3

557492

In the 0th step of the graph: select the line width on the wafer, the line width is the boundary value, and change the table. Then you want to expose

The same process window 3, at this time, the line width exposed on the wafer with a line width of 144 μm is 0.136 μm, which is greater than its specification value. At this time, the procedure for correcting the optical proximity effect can be divided into The following steps ^ exposure amount, using simulation or experimental methods to find out the line width of each cycle (as in the example above, when the cycle is 024 microns, on the wafer is 0.126 microns, when the cycle is 0.224. For micron, it is 0.136 micron on the wafer.) Make the energy of the center point of the process window of each cycle correspond to the selected exposure, and create a __ lookup table accordingly. According to the original mask size (this is the pattern to be formed on the wafer), the conventional optical proximity effect correction method can be used to find the mask size corresponding to the size on the wafer. For grooves with a period of 0.240 microns, when the line width on the photomask is 130 μm, if a groove of 0.13 μm is to be exposed on the wafer, the critical value must be equal to 0. 35 energy exposure. For the period of 1000 micrometers, the grooves, if the conventional optical proximity effect correction method is used, if in this exposure 1 still want to expose a groove with a depth of 0.3 μm on the wafer, then The line width on the reticle must be corrected to 0.136 microns instead of the aforementioned 44 microns. At this time, the process window is as shown in process window 4 in FIG. 4. Although the width on the wafer is aligned at the selected exposure, the two process windows have a relative offset, causing their common manufacturing window to be smaller than the above situation, as shown in Figure 5. The common process window 5. In other words, using the traditional optical proximity effect correction method has a statistically greater chance to expose line widths that do not meet the specifications. ΰ Figure 7 shows the optical proximity effect correction method in an embodiment of the present invention.

557492 V. Description of Invention (9), Flowchart of Law. In step 71, an integrated circuit design pattern and an exposed upper and lower line width allowable upper limit and lower limit value are provided. The integrated circuit design pattern has multiple line width values and multiple spacing values, and also includes a main graphic and a secondary value. Analyze subsidy graphics. In step 72, the correspondence between the exposure line width value, the exposure amount, and the defocus value is taken at each line width value and each interval value. -In step 73, the process window of the integrated circuit design pattern is found according to each of the above-mentioned corresponding relationships and the upper and lower limits of the exposed line width are provided. 〇 〇

In step 74, each line width value of the integrated circuit design pattern under each space value is adjusted so that the exposures corresponding to the center points of each process window are aligned with each other. In step 75, the value of the exposed line width at the center point of each process window is found according to each correspondence. In step 76, the line width of the integrated circuit design pattern at the center point of the corresponding process window at each pitch value is used as the standard, and the integrated circuit design pattern is modified by the conventional optical proximity effect correction method. In step 77, the modified integrated circuit design pattern is transferred to a mask. In the above-mentioned conventional optical proximity model correction method. To establish both methods, you must first design an example that is as complete as possible for this semiconductor generation. The test pattern contains an effect correction method, which can be regular or a query table must be provided first. This lookup table represents a representative test pattern contained in the test mask. In a one-dimensional graph

557492 Will test the photomask at a certain defocus line width required. Use the center point of the rule mouth to modify the integrated circuit to obtain the correction value of an experimental process window. It has been disclosed in a preferred embodiment such as' Any person who is familiar with this skill can make a few changes and retouching if improper. The pattern of the photoresist line and the mask line correction method of the pattern defined on the patent scope are exposed to the circuit design drawing model, so that the center point is used to modify the exposure to the crystal width, and when the width is found, the width value is matched. However, use the query to expose the positive value of the line for rounding, and then use the table according to one of the checks to modify the wide band to correct the product. V. Description of the invention (10) The combination of line widths. For a certain exposure amount and the photoresistance profile to be exposed, a look-up table is established with each process window, and when this correction value is used to normalize, if necessary, each experimental model is then graphed. Although the present invention is limited to the scope of the present invention, the range of protection is measured and the correction value is found in this experiment information table under a measurement period. The model repair experiment model is incorporated into the modified body circuit setting, but it is not used. Without departing from the spirit of the invention, the warranty of the invention shall prevail.

557492

In the following, an embodiment of the optical neighbor method of the present invention will be explained with reference to the drawings. The line width of the square process f should be modified to G. The distance between the main line and the main line plus the second line of the second line of the groove of the cycle meter 24Q microns The width is 0.444 microns, and the period is 丨. 〇〇〇 micro pattern 0.270 micron (the center point of the main pattern to the auxiliary opening; the groove (analysis of the auxiliary pattern at the line width of 0.1 μm)) Figure 3 shows the common process window of the above two process windows .... Figure 4 shows a line width of 0.136 micron period for h

Graphic 0.270 micron (system of the main graphic center point to the auxiliary groove (analyze the auxiliary graphic at a line width of 0.100 micron)). Figure 5 is not shown in the process window of Figure 1 and Figure 4. The common process window, which shows the integrated circuit design pattern used in the example = Optical proximity effect correction in the embodiment [Symbol] 1, 2, 3, 4 ~ process window; 5 ~ common process window;

6 1 to main graphics; 6 2 to sub analysis graphics.

Claims (1)

557492 VI. Application for Patent Scope 1 · A method for correcting optical proximity effect 'includes the following steps: Provide an integrated circuit design pattern and an exposed upper and lower line width allowable upper limit value. The integrated circuit design pattern has a line width value And a distance value; obtain the corresponding relationship between an exposed line width value and one of an exposure amount and a defocus value under the line width value and the distance value; according to the corresponding relationship, cooperate with the upper limit of the exposed line width allowance And a lower limit value to find a process window of the integrated circuit design graphic; to find the exposed line width value at a center point of the process window according to the corresponding relationship; to provide a lookup table; to find out and The exposed line width value at the center point of the process window corresponds to a correction value; the integrated circuit design pattern is corrected with the correction value; and the corrected integrated circuit design pattern is transferred to a photomask. 2. The method of optical proximity effect correction as described in item 1 of the scope of patent application, which is applicable to the lithography process in a semiconductor process. 3. The method of optical proximity effect correction according to item 1 of the scope of the patent application, wherein the integrated circuit design pattern includes a main pattern and an auxiliary pattern. 4 · The method of optical proximity effect correction according to item 1 of the scope of patent application, wherein a test mask is used, and the test mask contains a plurality of representative test patterns, the representative test patterns having a plurality of numbers under a plurality of cycles. The combination of line width values exposes a representative test pattern on the test mask on a wafer, and measures the complex photoresistance line width under complex exposure and complex defocus. 0503-6378TWF; TSMC2001-0272; Vine ... II --- ent * ptd page 15 557492 6. Application for patent range value 'to obtain the mask line width value required to expose the photoresistance line width value at these periods Size, build the lookup table. 5 · A method for correcting optical proximity effects, including the following steps: Provide an integrated circuit design pattern and an exposed upper and lower allowable line width allowable upper limit and lower limit value 'The integrated circuit design pattern has a line width value and a space value; Obtain a corresponding relationship between an exposed line width value and an exposure amount and a defocus value under the line width value and the distance value; * According to the corresponding relationship, cooperate with the upper limit and lower limit value of the exposed line width Find a process window of the integrated circuit design graphic; find the exposed line width value at a center point of the process window according to the corresponding relationship; provide a lookup table and an experimental model; use the lookup table to modify the experiment Model; bringing the exposed line width value of the center point of the process window into the modified experimental model to obtain a correction value; using the correction value to correct the integrated circuit design graphic; and the modified integrated product The circuit design graphics are transferred to a reticle. 6. The method of optical proximity effect correction as described in item 5 of the scope of patent application, which is applicable to a lithography process in a semiconductor process. 7. The method for correcting optical proximity effect as described in item 5 of the scope of patent application, wherein the integrated circuit design pattern includes a main pattern and a supplementary pattern. 8. The method of optical proximity effect correction as described in item 5 of the scope of the patent application, wherein a test mask is used, and the test mask contains a plurality of 0503-6378TW; TSMC2001-0272; Vincent.ptd Page 16 557492 VI. Patent Application Representative Test Patterns The representative test pattern has a combination of complex line values in a complex cycle. A representative test pattern is exposed on a wafer, and the multiple photoresistance line width values under the multiple exposure and complex defocus are measured to obtain the photomask line required to expose the photoresistance line width value at these periods. Wide value size to build the lookup table. 9. · A method for correcting optical proximity effect, comprising the following steps: providing an integrated circuit design pattern and an exposed upper and lower allowable line width allowable upper limit and lower limit value 'the integrated circuit design pattern has a line width value and a complex spacing value; obtain Under the line width value and each spacing value, a corresponding relationship between an exposed line width value and an exposure amount and a defocus value; according to these correspondences, the upper limit and lower limit value of the exposed line width are matched Find the multiple process windows of the integrated circuit design pattern; adjust the line width value of the integrated circuit design pattern at each spacing value so that the exposures corresponding to the complex center points of the process windows are aligned with each other; The corresponding relationships find out the exposed line width values of the center points of the process windows; provide a lookup table; find out the exposed line width values of the center points of the process windows according to the lookup table Corresponding complex correction values; correcting the integrated circuit design pattern with the correction values; and transferring the corrected integrated circuit design pattern to a photomask. 10 · The method of optical proximity effect correction as described in item 9 of the scope of the patent application, which is applicable to a lithography process in a semiconductor process. 557492 VI. Patent Application Range '· 11 · The method of optical proximity effect correction as described in item 9 of the patent application range', wherein the integrated circuit design pattern includes a main pattern and an auxiliary pattern. 1 2 · The method of optical proximity effect correction as described in item 9 of the scope of patent application 'wherein a test mask is used, and the test mask contains a plurality of representative test patterns' The combination of the complex line width values exposes a representative test pattern on the test mask on a wafer, and measures the complex exposure and the complex photoresistance line width values under the complex defocus to obtain these periods. The size of the mask line width required to expose the line width of the photoresist is established, and the lookup table is established. 1 3-A method for correcting optical proximity effects, including the following steps: · Provide an integrated circuit design pattern and an exposed upper and lower allowable line width allowable, the integrated circuit design pattern has a line width value and a complex spacing Get the corresponding relationship between an exposed line width value and an exposure amount and a defocus value under the line width value and each interval value; 配合 Match the exposed upper limit of line width allowance according to these correspondence relationships Find the multiple process windows of the integrated circuit design pattern with the lower limit; ^ Adjust the line width value of the integrated circuit design pattern at each spacing value so that the exposures corresponding to the complex center points of the process windows Align with each other; find out the exposed line width values of the center points in the process windows according to the corresponding relationships; provide a query table and an experimental model; use the query table to modify the experimental model; 0503-6378TWF; TSMC2001-0272; Vincent.ptd $ 18 pages " " " " " ---- 557492 / Bring the exposed line width values of the center points of the process windows into the revised after-test model to obtain a complex correction value; correct the integrated circuit design graphic with the correction values; and modify the correction The subsequent integrated circuit design graphic is transferred to a photomask. 1 4 · The method for correcting optical proximity effect as described in item 9 of the scope of patent application ', which is applicable to a lithography process in a semiconductor process. 1 5 · The method for correcting the optical proximity effect as described in item 9 of the scope of the patent application ’, wherein the integrated circuit design pattern includes a main pattern and an auxiliary pattern. 0 16 · The method of optical proximity effect correction as described in item 9 of the scope of the patent application, wherein a test mask is used, and the test mask includes a plurality of representative test patterns, the representative test patterns having a plurality of cycles The combination of the complex f-width values exposes a representative test pattern on the test mask on a wafer to 'measure the complex exposure amount and the complex photoresistance line width value under complex defocus' to obtain these periods The size of the mask line width required to expose the line width of the photoresist is established, and the lookup table is established. 17. · A method for correcting the optical proximity effect, including the following steps: Provide an integrated circuit design pattern and an allowable upper limit of the exposed line width and Limit value, the integrated circuit design graphic has a complex line width value and a complex spacing value; obtaining that at each line width value and each spacing value, an exposed line width value corresponds to one of an exposure amount and a defocus value Relationships; find out the multiple process windows of the integrated circuit design pattern according to the corresponding relationships with the exposed upper and lower allowable line width allowances; 0503-6378TWF; TSMC2001-0272; Vincent.ptd Page 19 557492 VI. Patent Application Range 1-1 *-1-Adjust each line width value of the integrated circuit design pattern at each spacing value to make these process windows The exposures corresponding to the plural center points are aligned with each other; find out the exposure line width values of the centers in the process windows according to the corresponding relationships; ”Provide a query table; _ According to the query table Complex correction values corresponding to the eye-out line width values of the center points of the process windows; * correcting the integrated circuit design graphic with the correction values; and transferring the revised integrated circuit design graphic to a On the photomask. 18. The method for correcting the optical proximity effect as described in item 17 of the scope of the patent application, 'which is applicable to the lithography process in a semiconductor process. 1 9. As described in the scope of patent application, item 7 Method for correcting optical proximity effect, wherein the integrated circuit design pattern includes a main pattern and an auxiliary pattern. 2 0 · The method for correcting optical proximity effect as described in item 7 of the patent application scope 'Among them, a test mask is used, and the test mask includes a plurality of representative test patterns. The representative test pattern has a combination of a plurality of line width values under a plurality of cycles, and the representative test patterns on the test mask are exposed. On a wafer, measure the multiple photoresistance line width values under multiple exposures and multiple defocus, and obtain the mask line width value required to expose the photoresistance line width value at these periods, and establish the 2 1 · —A method for correcting optical proximity effect, including the following steps: Provide an integrated circuit design pattern and an exposed upper limit of the line width 0503-6378TWF; TSMC2001-0272; Vincent.ptd 557492 6. Scope of patent application-limit value, the integrated circuit design graphic has a complex line width value and a complex spacing value; under each line width value and each spacing value, one exposure line width value and one exposure line and one distance Correspondence of one of the focal values; According to these correspondences and the upper limit and lower limit of the exposed line width allowance, find out the complex process window of the body circuit design graphic; /,… adjust the product at each interval value Each line width value of the circuit design pattern makes the exposure amounts corresponding to the plurality of center points of the manufacturing windows aligned with each other; according to the corresponding relationships, find the exposure line width values at the center points of the manufacturing windows ; Ο provide a look-up table and an experimental model; use the look-up table to modify the experimental model; bring the exposed line width values of the center points of the process windows into the modified experimental model to obtain a complex correction Value; correcting the integrated circuit design pattern with the correction values; and transferring the corrected integrated circuit design pattern to a photomask. 2 2 · The method of optical proximity effect correction as described in item 17 of the scope of patent application, which is applicable to the lithography process in a semiconductor process. 2 3 · The method for correcting optical proximity effect as described in item 17 of the scope of patent application, wherein the integrated circuit design pattern includes a main pattern and a supplementary pattern. 2 4 · The method of optical proximity effect correction as described in item 17 of the scope of patent application, wherein a test mask is used, and the test mask contains a 0503-6378TW; TSMC2001-0272; Vincent.ptd Page 21 557492 6. Representative test pattern of patent application number, the representative test pattern has a combination of complex line width values under multiple cycles, A representative test pattern is exposed on a wafer, and the multiple photoresistor line width values under the multiple exposure and complex defocus are measured, and the photoresistor line width required to expose the photoresistor line width value at these periods is obtained Value size, build the lookup table. 0503-6378TWF; TSMC2001-0272; Vincent.ptd page 22