556321 A7 B7 五、發明説明（ 發明 本發月疋有關於—種半導體元件的製造方法，係有關 鑲嵌内連線的製造方法，且特別是有關於一種銅 金屬插塞的製造方法。 發明背i 當半導體元#，例如積體電路的積集度增力口，使得晶 的=面無法提供足夠的面積來製作所需的内連線時，為 了配&金氧半導體（meta丨。xide semicQ_咖，m〇s)電 所增加的内連線需求，兩層以上的金屬層設 计’便逐漸的成為許多積體電路所必需採用的方式 金屬内連線（M_evel lnterc〇nnects)的製作，是在金氧半 (metal ox丨de semic〇nduct〇「，_)電晶體的主體已完成 之士才開始的，它的目的是在獨立導通的金屬層之間，建 立-些連接系統，使得這些金屬内連線，可 達成彼此相連串的目的，, L心 (Circ_。 的—個積體電路的完整迴路 不同層之金屬内連線之間，係藉由位於 中介層窗内的插塞進行電$a，&#&#♦、 "電層556321 A7 B7 V. INTRODUCTION TO THE INVENTION (This invention relates to a method for manufacturing a semiconductor device, which relates to a method for manufacturing inlaid interconnects, and in particular to a method for manufacturing a copper metal plug. 发明 背 i When the semiconductor element #, for example, the integration degree of the integrated circuit, makes the crystal surface unable to provide enough area to make the required interconnects, in order to match the metal oxide semiconductor (meta 丨 .xide semicQ) _Ca, m0s) Increased demand for interconnects in power plants, and the design of two or more metal layers has gradually become the method necessary for many integrated circuits. Metal interconnects (M_evel lnterc〇nnects) production , Began when the body of the metal ox 丨 de semic〇nduct〇 ", _ transistor has been completed, its purpose is to establish independent connection between the metal layers, some connection systems, This makes these metal interconnects achieve the purpose of connecting each other. The metal interconnects on different layers of the complete circuit of the L core (Circ_.) Are connected by interposers located in the interposer window. Plug in electricity $ a, & am p; # &# ♦, " Electrical layer
T电逆恕，而形成插塞的材質可以A 銅金屬。由於銅金屬對於低介電材質和氧化石夕均有相μ 的穿透性，因此需在介層窗的内㈣形成—層 = 避免銅金㈣散穿透至周邊时電材㈣1知形^阻二 2 556321T electricity is reversed, and the material forming the plug can be A copper metal. Because copper metal has low-permeability to both low-dielectric materials and oxidized stones, it is necessary to form it in the interior of the dielectric window—layer = to prevent copper and gold from scattering and penetrating into the surrounding area. Tuesday 2 556321
五、發明説明（） 層的材質為鈕、鈦、氮化鈕和氮化鈦。 當製程的尺庚不斷下降時，習知的阻障材質的阻值會 大幅增加元件的RC遲延（RC de|av、 m ^ 雙、（κυ delay)，更嚴重的是，由於製 程裕度（Window)不斷的下降，阻障層需要越來越薄，此 時阻障層會產生可靠度（Re丨iabnity)的問題。因為集積 度增加而使阻障層產生的可#度問題會使漏電流增加，隨 時間而致之介電崩潰（Time_Dependent Dje|ectric5. Description of the invention The material of the () layer is button, titanium, nitride button and titanium nitride. As the scale of the process continues to decrease, the resistance value of the conventional barrier material will greatly increase the RC delay of the component (RC de | av, m ^ double, (κυ delay), and more seriously, due to the process margin ( Window) keeps falling, and the barrier layer needs to be thinner and thinner. At this time, the barrier layer will have a problem of reliability (Re 丨 iabnity). Because of the increase in the degree of integration, the problem of the degree of obstruction of the barrier layer will cause leakage Increase in current, dielectric breakdown over time (Time_Dependent Dje | ectric
Breakdown，TBBD )生命週期和（B丨於丁啊抑_ Stress BTS )也會隨之大幅縮短。為解決阻障層可靠度的 問必須引人新的材質來形成阻障層。目前解決阻障層 可靠度的問題是以碳氧切（SiQC)材質層代替習知的 鈦氮化组或氮化鈦阻障層，以增加阻障層的可靠度 降0 、當製程的尺度降至〇_1微米以下時，製程裕度也隨著 ^幅下降，碳氧化矽材質阻障層使製程的困難度大幅的提 幵:睛參照第1圖，第1圖係繪示習知形成碳氧化石夕材質 阻障層所發生的缺陷。在一基底（未繪示於圖上）上具有 介電層10及介電層12,在介電層12中具有一金屬導線 14。金屬導線14和介電層1〇和12的交界處有一阻障層 (未繪示於圖上）。形成介電層16於介電層12之上。其中θ， 形成金屬導線14的材質為銅金屬，而形成介電層12〃 . 質為碳氧化石夕。 * 凊繼續參照第1圖，以一微影蝕刻製程，蝕刻介電層 16以形成一介層窗18於介電層16之中並暴露出金屬導ς 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) 訂· 經濟部智慧財產局員工消費合作社印製Breakdown (TBBD) life cycle and (B 丨 于 丁 啊啊 _ Stress BTS) will also be greatly shortened. To solve the problem of the reliability of the barrier layer, a new material must be introduced to form the barrier layer. At present, the problem of the reliability of the barrier layer is to replace the conventional titanium nitride group or titanium nitride barrier layer with a carbon-oxygen cut (SiQC) material layer in order to increase the reliability of the barrier layer and reduce the scale of the process. When it falls below 0_1 micron, the process margin also decreases with ^. The silicon carbide oxide barrier layer greatly increases the difficulty of the process: refer to Figure 1 for details. Defects in the formation of a barrier layer made of oxycarbonite. A dielectric layer 10 and a dielectric layer 12 are provided on a substrate (not shown), and a metal wire 14 is provided in the dielectric layer 12. A barrier layer (not shown) is provided at the boundary between the metal wire 14 and the dielectric layers 10 and 12. A dielectric layer 16 is formed on the dielectric layer 12. Among them, θ, the material forming the metal wire 14 is copper metal, and the dielectric layer 12〃 is formed. The material is carbon oxide. * 凊 Continuing to refer to Figure 1, using a lithographic etching process, the dielectric layer 16 is etched to form a dielectric window 18 in the dielectric layer 16 and the metal conductors are exposed. This paper applies the Chinese National Standard (CNS) A4 Specifications (210X297 mm) (Please read the notes on the back before filling out this page) Order · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
556321 五、發明説明（） 陆“中形成；|電層12的材質為多孔性含秒低介電常數 材質。形成碳氧化矽阻障層20於介層窗18的側壁上，再 於介層窗18填入金屬層22而形成插塞結構2心另外可形 =一薄金屬層（未緣示於圖上）於金屬層22及碳氧化石夕阻 =20以做為-黏著層之用，其中，形成金屬層22的材 質為鋼金屬。由於製程的尺度已經降i Q1微米以下而碳 氧化石夕材質層會降低後續材料的製程裕度，因此，在形 成金屬層22時會形成孔洞（via) 26於金屬層22之内广 孔洞26會造成插塞結構24的阻值上升及電性改變，而降 低製程的良^減少碳氧化梦材質層的厚度可以緩解這種 緊張，但阻障層可靠度的問題卻無法徹底解決。如何在〇」 微米以下的製程中解決阻障層可靠度的問題成為—個重要 的課題。 發明目的邀概砵 因此本發明的目的就是在提供一種金屬插塞的製造方 法’用以解決阻障層可靠度的問題。 本發明的另一目的是在提供一種金屬插塞的製造方 法，可以改善隨時間而致之介電崩潰生命週期，增進電子 遷移（Electro_migrati〇n，EM)生命週期。 本發明的又一目的是在提供一種金屬插塞的製造方 法，在插塞底部不需要阻障層，而避免因阻障層產生的極 大片電阻（Sheet Resistance)值，可大幅降低Rc遲延。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閲讀背面之注意事項再填寫本頁) ，tr 線 經濟部智慧財產局員工消費合作社印製 556321 A7 B7 - ^ 五、發明説明（） 二本發明所提供一種金屬插塞的製造方法，以現有的機 台所提供的製程即可達成，無須更新設備。 根據本發明之上述目的，提出一種銅鎮嵌内連線的製 =方法’適用於一半導體製程之上，該方法係先形成第— "電層於基底上之内層介電層（丨nter Layer D|_e|ectrjc，丨LD) 接著形成第一介電層於第一介電層之上，再形成第 一二電層於第二介電層之上。以一微影蝕刻製程，蝕刻第 一2電層、第二介電層及第三介電層以形成一溝渠，溝渠 底2暴露出内層介電層。然後，形成共型的第四介電層於 溝渠内。以一銅金屬層填滿溝渠。 形成第五介電層覆蓋第三介電層、第四介電層和銅金 屬層。形成第六介電層於第五介電層之上，形成一介層窗 於第五介電層與第六介電層之中並暴露出銅金屬層。形成 一薄阻障金屬層於介層窗之側壁，再以銅金屬填滿介層窗 而形成插塞。在此之薄阻障金屬層並非必要的，亦可以省 略不做。 一非均向回蝕，移除第六介電層、第五介電層及第三 介電層。形成共型的第七介電層覆蓋第二介電層、第四介 電層和插塞的側壁，最後，形成第八介電層覆蓋第七介電 層。 本發明所提出的銅鑲嵌内連線的製造方法，係以介電 材質，例如碳氧化矽來取代傳統的金屬阻障材質，以擗強 阻障層對銅金屬擴散之阻障能力。另外，為了能形成^續 且有效的阻障層，不採取習知先將阻障層形成於介層窗内 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公楚) (請先閲讀背面之注意事項再填寫本頁) -訂· 線 經濟部智慧財產局員工消費合作社印製 556321 A7 B7 五、發明説明（） 的作法，而疋在銅金屬插塞完成後，移除插塞周圍之介電 層，再於插塞側壁上形成阻障層，這樣可以大幅提高製輕 裕度，而使半導體元件製程的良率大幅增加。除了上述之 優點外，即使介電層已因銅擴散而改變電性，也因為銅金 屬插塞周圍之介電材質隨後被移除而不受影響。新形成的 介電層的電性會依設計而定，不再受到銅金屬擴散的影響。 本發明不只適用於銅鑲嵌内連線的製造方面的製程， 亦可適用於形成-種無阻障埋入式金屬結構，本發明所提 出的製造方法，係形成於所提供一結構之上，先形成至少 -第-介電層於結構之上，圖案化第一介電層以形成一開 口，開口暴露出部分結構或是結構的頂面，開口具有側壁 及底部。可以在開口的側壁及底部形成一共型的姓刻保護 層，但此步驟並非必要的，將視需要加入製程之中。以一 金屬材質填滿開口而形成一金屬結構於開口之内，此一金 屬結構係為-插塞，金屬結構具有側邊、底面和頂面 著，移除第-介電層，移除第一介電層的方法包括 製程’而蝕刻製程係以氮和氫為氣體源之選擇性電漿蝕 刻，不使用氧氣的原因係為避免電浆會和金屬結構產生 化作用而所傷到金屬結構。再來，形成共型的一介電 層覆蓋結構和金屬結構，形成介電阻障層的材質係為_石山 氧化石夕材質。最後再形成一第二介電層覆蓋介電阻障層反 其中介電阻障層可避免金屬結構的金屬材質擴散: 電層。 一 本發明所提出的無阻障埋入式金屬結構的製造方法， 6 ^紙張尺度適用中國國家標準(CNS)A4規格(210X297公楚) ~ " *- (請先閲讀背面之注意事項再填寫本頁) 訂. 線一 經濟部智慧財產局員工消費合作社印製 556321 五、發明説明（） G真====:用阻障層’而是㈣電 _對銅金屬擴散之::::的 ==的成知先將阻障層形成於介層窗内 再於插塞㈣上形成介電層， :而吏丰導體元件製程的良率大幅增力”除了上述之優 構周圍擴散而改變電性，也因為金屬結 Μ 仏後被移除而不受影響。新形成的介電 曰的電性曰依設計而^，不再受到銅金屬擴散的影響。 邏^式之簡單説明 為讓本發明之上述和其他目的、特徵、和優點 顯易懂，下文特舉一較佳實施例，並配合所附圖式 細說明如下： 卞 第1圖係繪示習知形成碳氧化石夕材質阻障層所發生的 缺陷； 第2圖至第4圖係繪示依照本發明較佳實施例 揭露之插塞的製造方法；以及 叮 第5圖至第6圖係繪示依照本發明較佳實施例 揭露之插塞的製造方法。 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 556321 A7 B7 五、發明説明（） 圖式之標記說明 10、100 :内層介電層 12、16、102、104、110、114、116、126、128、200、 204、206、218、220 :介電層 14、202 ··金屬導線 108 :溝渠 112、122、214 :銅金屬層 18、118、210 :介層窗 120、212 :金屬阻障層 124、216、24 ·•插塞 20 :碳氧化矽阻障層 22 :金屬層 26 :孔洞 發明之詳細說明 實施例1 第2圖至第4圖係繪示依照本發明一較佳實施例的所 揭露之插塞的製造方法。 請參照第2圖，在一基底（未緣示於圖上）上具有内 層介電層100,先形成介電層102於内層介電層10Q之上， 8 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂· 線- 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 接著形成介電層104於介電層102之上。 ，的材質包括以化學氣相沉積形的：：内層 質，形成介電層102的材質包括以化學氣相 :切材質以及形成介電層104的材質=的碳 積形成的多孔性切低介電常 匕:：相沉 性所致。Ϊ，的厚度約介於2。。埃二::擇 U &影餘刻製程，蝕刻介電層1 04及八兩a :形成一溝渠108’溝渠1〇8底部暴露出内層介;；曰1〇:〇2 二'後’形成共型的介電層11〇於溝渠曰二 屬層m填滿溝渠⑽；銅金 介電声110 _併— 中’形成共型的 質。曰 #貝匕括以化學氣相沉積形成的碳氧化石夕材 銅金屬層112係為一位於介電層内的金屬内連線，妒 一銅金f層的方法係為一習知的製程，其中可以包括先以 。物理氣相a積形成銅晶種層，再以電鑛法沉積銅金屬， ^後=以一化學機械研磨製程進行平坦化。介電層110為 一阻障層，係取代習知的金屬阻障層以阻撑銅金屬層川 的銅金屬材貝在後績製程中擴散入周圍的介電層之中。介 電層11〇的厚度約介於50埃至細埃之間。以例如碳氧 化石夕介電材質取代習知的金屬材質而形成銅金屬阻障層雖 然會提高金屬導線的阻抗值，但卻可以大幅減少金屬導線 間的電容值，因此RC遲延可大幅降低。 凊參照第3圖’形成介電層m覆蓋介電層1〇4、介 本紙張尺度適ji]巾關家標準(CNS)A4規格(21〇χ297公爱） 556321 A7 B7 五、發明説明（） 電層110和銅金屬層112。接著，形成介電層116於介電 層114之上。然後，再形成一介層窗118於介電層114與 介電層116之中並暴露出銅金屬層112,其中，介層窗 的寬度小於銅金屬層112的寬度。形成介電層114θ的材質 包括以化學氣相沉積形成的碳化矽材質或是以化學氣相沉 積形成的多孔性含矽低介電常數材質，而形成介電層116 的材質包括以化學氣相沉積形成的多孔性含矽低介電常數 材質或是以化學氣相沉積形成的碳化矽材質。介電層114 的厚度約介於300埃至1 〇〇〇埃之間。 請繼續參照第3圖，形成一薄金屬層]2〇於介層窗）巧8 之側壁，再於介層窗118填入金屬層122而形成插^124, 金屬層122的材質可以為銅、鋁銅合金、鎢金屬等材質。 本實施例中係使用銅金屬形成金屬層122，形成銅金屬層 122和前述形成銅金屬層112的方法相同。薄金屬層wo 的材質係選自於组、鈦、氮化组、氮化鈦和其任意組和所 組成之族群。本實施例中係以鈕金屬形成阻障金屬層彳2〇, 鈕金屬層的厚度約介於20埃至1〇〇埃之間。薄金屬^層12〇 係做為一黏著層之用，亦可以在後續的蝕刻製程中保護形 成於其内側的銅金屬層122。薄金屬層12〇並不是本發明 中必要的材質層，是否形成係依需求而定。 請參照第4圖，以一非均向選擇性蝕刻，以介電層1〇2 為蝕刻終止層，移除介電層116、介電層114及介電層彳〇4。 非均向選擇性蝕刻係選擇氮氣和氫氣為蝕刻製程氣體，其 目的在避免钱刻過程中暴露出的銅金屬《112會被钱刻劑 10 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閲讀背面之注意事項再場寫本頁) -訂· 線_ 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印1 556321 A7 __B7 五、發明説明（） 所氧化。接著，形成共型的介電層126覆蓋介電層102、 介電層110和插塞124的侧壁。形成介電層126的材質包 括以化學氣相沉積形成的碳氧化矽材質，介電層126為一 阻障層’係取代習知的金屬阻障層以阻擋銅金屬層122的 銅金屬材質在後續製程中擴散入周圍的介電層之中。再形 成介電層128覆蓋介電層126，形成介電層128的材質包 括以化學氣相沉積形成的多孔性含矽低介電常數材質。最 後，以平坦化製程移除高於插塞124之介電層128及126 至插塞124的頂面暴露出來為止。 相較習知碳氧化矽阻障層以r内填」的方式形成，本 叙明係採用「外圍」的方式來形成碳氧化石夕阻障層12〇， 因此製程的裕度可以大幅提高。 實施例2 第5圖至第6圖係繪示依照本發明另一較佳實施例的 所揭露之插塞的製造方法。 睛參照第5圖，在一基底（未繪示於圖上）上介電層 200及介電層204中具有一金屬導線202。金屬導線202 和介電層200和204的交界處有一阻障層（未緣示於圖 上），此一阻障層的材質可以為金屬、金屬氮化物或碳氧化 矽。其中，形成介電層200的材質包括以化學氣相沉積形 成的氧化矽或氮化矽，形成介電層204的材質包括以化學 氣相沉積形成的碳氧化矽材質。 11 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁)556321 V. Description of the invention ("Lu"); | The material of the electrical layer 12 is a porous low second dielectric constant material. A silicon carbide barrier layer 20 is formed on the sidewall of the dielectric window 18 and then on the dielectric layer. The window 18 is filled with a metal layer 22 to form a plug structure. 2 The core is also shaped = a thin metal layer (not shown in the figure) on the metal layer 22 and the oxycarbonite resistance = 20 as an adhesive layer. Among them, the material forming the metal layer 22 is steel. Because the dimensions of the process have been reduced to less than 1 μm and the carbon oxide material layer will reduce the process margin of subsequent materials, holes will be formed when the metal layer 22 is formed. (Via) 26 The wide holes 26 in the metal layer 22 will cause the resistance of the plug structure 24 to increase and change the electrical properties, and reduce the quality of the process ^ reducing the thickness of the carbon oxide dream material layer can reduce this tension, but the resistance The problem of barrier layer reliability cannot be completely solved. How to solve the problem of barrier layer reliability in a process below 0 ″ microns has become an important issue. SUMMARY OF THE INVENTION The purpose of the present invention is to provide a method for manufacturing a metal plug 'to solve the problem of the reliability of the barrier layer. Another object of the present invention is to provide a method for manufacturing a metal plug, which can improve the life cycle of dielectric breakdown caused by time and the life cycle of Electron Migration (EM). Another object of the present invention is to provide a method for manufacturing a metal plug, which does not require a barrier layer at the bottom of the plug, thereby avoiding an extremely large sheet resistance value due to the barrier layer, and can greatly reduce the Rc delay. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page), printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 556321 A7 B7-^ V. Description of the invention (2) The manufacturing method of the metal plug provided by the present invention can be achieved by the manufacturing process provided by the existing machine, and there is no need to update the equipment. According to the above purpose of the present invention, a method for manufacturing copper-embedded interconnects is proposed, which is applicable to a semiconductor process. The method is to first form an "inner dielectric layer on the substrate" Layer D | _e | ectrjc (LD), and then forming a first dielectric layer on the first dielectric layer, and then forming a first two dielectric layer on the second dielectric layer. In a lithographic etching process, the first 2 electrical layer, the second dielectric layer and the third dielectric layer are etched to form a trench, and the bottom 2 of the trench exposes the inner dielectric layer. Then, a conformal fourth dielectric layer is formed in the trench. Fill the trench with a copper metal layer. A fifth dielectric layer is formed to cover the third dielectric layer, the fourth dielectric layer, and the copper metal layer. A sixth dielectric layer is formed on the fifth dielectric layer, a dielectric window is formed in the fifth dielectric layer and the sixth dielectric layer and the copper metal layer is exposed. A thin barrier metal layer is formed on the sidewall of the via, and the via is filled with copper metal to form a plug. A thin barrier metal layer is not necessary here and can be omitted. An anisotropic etchback removes the sixth dielectric layer, the fifth dielectric layer, and the third dielectric layer. A seventh dielectric layer is formed to cover the sidewalls of the second dielectric layer, the fourth dielectric layer, and the plug. Finally, an eighth dielectric layer is formed to cover the seventh dielectric layer. The manufacturing method of copper inlaid interconnects proposed by the present invention is to replace the traditional metal barrier material with a dielectric material, such as silicon oxycarbide, and use a strong barrier layer to prevent the diffusion of copper metal. In addition, in order to form a long-lasting and effective barrier layer, the barrier layer is formed in the interlayer window without prior knowledge. This paper applies the Chinese National Standard (CNS) A4 specification (210X297). (Please read the back Please fill in this page again)-Order · Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 556321 A7 B7 V. Method of Invention (), and after the copper metal plug is completed, remove the surrounding media An electrical layer and a barrier layer are formed on the side wall of the plug, so that the light-weight margin can be greatly improved, and the yield of the semiconductor device process can be greatly increased. In addition to the advantages described above, even if the dielectric layer has changed its electrical properties due to copper diffusion, the dielectric material surrounding the copper metal plug is subsequently removed without being affected. The electrical properties of the newly formed dielectric layer will depend on the design and will no longer be affected by copper metal diffusion. The present invention is not only applicable to the manufacturing process of copper inlay interconnects, but also applicable to forming an unobstructed buried metal structure. The manufacturing method proposed by the present invention is formed on a provided structure. Forming at least a first dielectric layer on the structure, patterning the first dielectric layer to form an opening, the opening exposing a portion of the structure or the top surface of the structure, and the opening having a sidewall and a bottom. It is possible to form a conformal protective layer on the side and bottom of the opening, but this step is not necessary and will be added to the process as needed. A metal material is used to fill the opening to form a metal structure within the opening. The metal structure is a plug. The metal structure has side edges, a bottom surface, and a top surface. The first dielectric layer is removed, and the first A method of a dielectric layer includes a process, and the etching process is selective plasma etching using nitrogen and hydrogen as a gas source. The reason for not using oxygen is to avoid damage to the metal structure caused by the plasma and the metal structure. . Then, a dielectric layer covering structure and a metal structure are formed to form a common type, and the material forming the dielectric barrier layer is _shishan oxidized stone material. Finally, a second dielectric layer is formed to cover the dielectric barrier layer. The dielectric barrier layer can prevent the metal material of the metal structure from diffusing: the electrical layer. A method for manufacturing an unobstructed embedded metal structure proposed by the present invention, 6 ^ paper size is applicable to China National Standard (CNS) A4 specification (210X297). &Quot; *-(Please read the precautions on the back before filling This page) Order. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by 556321 V. Description of the invention () G true ====: using a barrier layer ', but a galvanic _ for copper metal diffusion :::: The == Chengzhi first formed the barrier layer in the interlayer window and then formed the dielectric layer on the plug ，, and the yield of the Lifeng conductor element process has greatly increased. In addition to the above-mentioned diffusion around the superior structure, Changing the electrical properties is also not affected because the metal junction M is removed. The electrical properties of the newly formed dielectric are designed according to the design, and are no longer affected by the diffusion of copper metal. The simple explanation of the logic formula is To make the above and other objects, features, and advantages of the present invention comprehensible, a preferred embodiment is exemplified below and described in detail with the accompanying drawings as follows: 卞 Figure 1 shows the conventional formation of carbon oxide stone Defects that occur in the material barrier layer; Figures 2 to 4 show the invention according to the invention The manufacturing method of the plug disclosed in the preferred embodiment; and Figures 5 to 6 show the manufacturing method of the plug disclosed in accordance with the preferred embodiment of the present invention. This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 556321 A7 B7 V. Description of the invention () Symbol description of the drawings 10, 100: Inner dielectric layer 12, 16, 102, 104, 110, 114, 116, 126, 128, 200, 204, 206 , 218, 220: Dielectric layers 14, 202. Metal wires 108: Channels 112, 122, 214: Copper metal layers 18, 118, 210: Interlayer windows 120, 212: Metal barrier layers 124, 216, 24. • Plug 20: SiC barrier layer 22: Metal layer 26: Detailed description of the hole invention Embodiment 1 Figures 2 to 4 show the disclosed plug according to a preferred embodiment of the present invention. Manufacturing method: Please refer to Figure 2. On a substrate (not shown in the figure), there is an inner dielectric layer 100. First, a dielectric layer 102 is formed on the inner dielectric layer 10Q. Standard (CNS) A4 specification (210X297mm) (Please read the precautions on the back before filling this page) Order · Thread-Warp Printed by the Consumer Cooperative of the Ministry of Economic Affairs of the Ministry of Economic Affairs of the People's Republic of China. 5. Description of the invention () Next, a dielectric layer 104 is formed on the dielectric layer 102. The material of the material includes chemical vapor deposition :: inner layer to form the dielectric layer The material of 102 includes a porous cut low dielectric constant formed by a chemical vapor phase: a cut material and a material of carbon that forms the material of the dielectric layer 104: due to the settling property. Well, the thickness is about 2. . I2 :: U & shadow etching process, etching the dielectric layer 104 and 82a: forming a trench 108 'the bottom of the trench 108 is exposed to the inner interlayer dielectric ;; 10: 02 2' after ' A conformal dielectric layer 11 is formed in the trench. The second layer m fills the trench; the copper-gold dielectric sound 110 _ and-in the middle forms a conformal mass.贝 # 匕 甲 的 The carborundum copper metal layer 112 formed by chemical vapor deposition is a metal interconnect located in a dielectric layer. The method of envying a copper-gold layer is a known process. , Which can include first. The physical vapor phase a is formed to form a copper seed layer, and then the copper metal is deposited by the electric ore method, and the post-planarization is performed by a chemical mechanical polishing process. The dielectric layer 110 is a barrier layer, which replaces the conventional metal barrier layer to support the copper metal layer and diffuses into the surrounding dielectric layer during the later production process. The thickness of the dielectric layer 110 is between about 50 angstroms and about 30 angstroms. For example, the formation of a copper metal barrier layer by replacing a conventional metal material with a dielectric material such as carboxidite will increase the resistance value of the metal wires, but it can greatly reduce the capacitance value between the metal wires, so the RC delay can be greatly reduced.凊 Refer to Fig. 3 'Formation of the dielectric layer m covering the dielectric layer 104, the size of the paper is appropriate] Standard (CNS) A4 (21〇297297) 556321 A7 B7 5. Description of the invention ( ) Electrical layer 110 and copper metal layer 112. Next, a dielectric layer 116 is formed on the dielectric layer 114. Then, a dielectric window 118 is formed in the dielectric layer 114 and the dielectric layer 116 and the copper metal layer 112 is exposed. The width of the dielectric window is smaller than that of the copper metal layer 112. The material forming the dielectric layer 114θ includes a silicon carbide material formed by chemical vapor deposition or a porous silicon-containing low dielectric constant material formed by chemical vapor deposition, and the material forming the dielectric layer 116 includes a chemical vapor phase. Porous silicon-containing low dielectric constant materials formed by deposition or silicon carbide materials formed by chemical vapor deposition. The thickness of the dielectric layer 114 is between about 300 angstroms and 1,000 angstroms. Please continue to refer to FIG. 3 to form a thin metal layer] 20 in the sidewall of the interlayer window) Q8, and then fill the interlayer window 118 with a metal layer 122 to form an insert 124, and the material of the metal layer 122 may be copper , Aluminum copper alloy, tungsten metal and other materials. In this embodiment, the metal layer 122 is formed using copper metal, and the method for forming the copper metal layer 122 is the same as the method for forming the copper metal layer 112 described above. The material of the thin metal layer wo is selected from the group consisting of group, titanium, nitride group, titanium nitride, and any group and group thereof. In this embodiment, the barrier metal layer 彳 20 is formed by a button metal, and the thickness of the button metal layer is between about 20 angstroms and 100 angstroms. The thin metal layer 12 is used as an adhesive layer, and the copper metal layer 122 formed on the inner side can be protected during the subsequent etching process. The thin metal layer 120 is not a necessary material layer in the present invention, and whether it is formed depends on the requirements. Referring to FIG. 4, the dielectric layer 116, the dielectric layer 114, and the dielectric layer 104 are removed by using a non-uniform selective etching and using the dielectric layer 102 as an etch stop layer. The non-uniform selective etching system uses nitrogen and hydrogen as the etching process gas. The purpose is to avoid the copper metal "112 will be etched by the money engraving agent 10" in the process of money engraving. 210X297 mm) (Please read the precautions on the back before writing this page)-Order · Thread _ Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the Consumers ’Cooperatives of the Ministry of Economics and Intellectual Property Bureau 1 556321 A7 __B7 () By oxidation. Next, a conformal dielectric layer 126 is formed to cover the sidewalls of the dielectric layer 102, the dielectric layer 110, and the plug 124. The material for forming the dielectric layer 126 includes a silicon oxide carbon material formed by chemical vapor deposition. The dielectric layer 126 is a barrier layer. The copper metal material 122 replaces the conventional metal barrier layer to block the copper metal layer 122. Diffusion into the surrounding dielectric layer in subsequent processes. The dielectric layer 128 is further formed to cover the dielectric layer 126. The materials for forming the dielectric layer 128 include a porous silicon-containing low dielectric constant material formed by chemical vapor deposition. Finally, the dielectric layers 128 and 126 higher than the plug 124 are removed by a planarization process until the top surface of the plug 124 is exposed. Compared with the conventional method of forming a silicon carbide barrier layer by “infilling”, this description uses the “peripheral” method to form the carbon oxide barrier layer 120, so the margin of the process can be greatly improved. Embodiment 2 Figures 5 to 6 illustrate a method for manufacturing a disclosed plug according to another preferred embodiment of the present invention. Referring to FIG. 5, a metal wire 202 is provided in the dielectric layer 200 and the dielectric layer 204 on a substrate (not shown). A barrier layer (not shown in the figure) is provided at the boundary between the metal wire 202 and the dielectric layers 200 and 204. The material of this barrier layer may be metal, metal nitride or silicon oxycarbide. The material for forming the dielectric layer 200 includes silicon oxide or silicon nitride formed by chemical vapor deposition, and the material for forming the dielectric layer 204 includes silicon carbon oxide material formed by chemical vapor deposition. 11 This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page)
556321 A7 B7 五、發明説明（） 形成介電層206於介電層204之上，形成介電層206 的材質包括以化學氣相沉積形成的多’孔性含矽低介電常數 材質。 請繼續參照第5圖，以一微影蝕刻製程，蝕刻介電層 206以形成一介層窗21〇於介電層2〇6之中並暴露出金屬 導線202 ’其中，介層窗21〇的寬度小於金屬導線2〇2的 寬度。形成一薄金屬層212於介層窗210之側壁，再於介 層窗210填入金屬層214而形成插塞216,金屬層214的 材質可以為銅、鋁銅合金、鎢金屬等材質。薄金屬層212 係做為一黏著層之用，亦可以在後續的蝕刻製程中保護形 成於其内側的金屬層214。薄金屬層212並不是本發明中 必要的材質層，是否形成係依需求而定。 在本實施例中，係使用銅金屬形成金屬層214，形成 銅金屬層214和實施例1中形成銅金屬層112的方法相 同。薄金屬層212的材質係選自於鈕、鈦、氮化鈕、氮化 鈦和其任意組和所組成之族群。本實施例中係以鈕金屬形 成薄金屬層212,鈕金屬層的厚度約介於2〇埃至100埃之 間。 、 睛參照第6圖，以一非均向選擇性蝕刻，以介電層2q4 為蝕刻終止層，移除介電層206。非均向選擇性蝕刻係選 擇氮氣和氫氣為蝕刻製程氣體，其目的在避免蝕刻過程中 暴露出的銅金屬層202會被蝕刻劑所氧化。接著，形成共 型的介電層218覆蓋介電層204和插塞216。形成介電層 218的材質包括以化學氣相沉積形成的碳氧化矽材質，介 12 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) 、τ 經濟部智慧財產局員工消費合作社印製 556321 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 電層218為一阻障層，係取代習知的金屬阻障層以阻擋銅 金屬層214的鋼金屬材質在後續製程中擴散入周圍的介電 層之中。再形成介電層22〇覆蓋介電層218及插塞216, 形成介電層220的材質包括以化學氣相沉積形成的多孔性 含矽低介電常數材質。最後，以一平坦化製程移除高於插 塞216之介電層218及220至插塞124的頂面暴露出來為 止。 線一 由上述本發明較佳實施例可知，本發明所提出的銅鑲 嵌内連線的製造方法，係以介電材質，例如碳氧化矽來取 代傳統的金屬阻障材質，以增強阻障層對銅金屬擴散之阻 障能力。另外，在製程裕度大幅下降的現今製程中，想要 在一個介層窗内形成足夠厚度的阻障層且要維持後續金屬 填入的製程裕度是相當的困難的，為了能形成連續且有效 的阻P平層，不採取習知先將阻障層形成於介層窗内的作 法，而是在銅金屬插塞完成後，移除插塞周圍之介電層， 再於插塞側壁上形成阻障層，這樣可以大幅提高製程裕 度’而使半導體元件製程的良率大幅增加。 經濟部智慧財產局員工消費合作社印製 除了上述之優點外’即使介電層已因銅擴散而改變電 性，也因為銅金屬插塞周圍之介電材質被移除而不受影 響。新形成的介電層的電性會依設計而定，不再受到銅金 屬擴散的影響。 本發明當然不只適用於銅金屬插塞的製程或銅金屬内 連線的製程，任何需要在金屬層周圍形成阻障層的製程均 可依本發明所揭露的製造方法來形成金屬層周圍的阻障 13 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 556321 A7 _B7_ 五、發明説明（） 層。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不’脫離本發明之精神 和範圍内，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 (請先閲讀背面之注意事項再填寫本頁) 、可. % 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)556321 A7 B7 V. Description of the invention () The dielectric layer 206 is formed on the dielectric layer 204. The material for forming the dielectric layer 206 includes a multi-porous silicon-containing low dielectric constant material formed by chemical vapor deposition. Please continue to refer to FIG. 5. In a lithographic etching process, the dielectric layer 206 is etched to form a dielectric window 21 in the dielectric layer 206 and the metal wires 202 are exposed. The width is smaller than the width of the metal wire 202. A thin metal layer 212 is formed on the sidewall of the interlayer window 210, and a metal layer 214 is filled in the interlayer window 210 to form a plug 216. The material of the metal layer 214 may be copper, aluminum-copper alloy, tungsten metal, or the like. The thin metal layer 212 is used as an adhesive layer, and the metal layer 214 formed on the inner side of the thin metal layer 212 can be protected in the subsequent etching process. The thin metal layer 212 is not a necessary material layer in the present invention, and whether it is formed depends on the requirements. In this embodiment, the metal layer 214 is formed using copper metal, and the method for forming the copper metal layer 214 is the same as the method for forming the copper metal layer 112 in the first embodiment. The material of the thin metal layer 212 is selected from the group consisting of buttons, titanium, nitride buttons, titanium nitride, and any combination thereof. In this embodiment, the button metal is used to form a thin metal layer 212, and the thickness of the button metal layer is between 20 angstroms and 100 angstroms. Referring to FIG. 6, a non-uniform selective etching is performed, and the dielectric layer 2q4 is used as an etch stop layer, and the dielectric layer 206 is removed. The non-uniform selective etching system uses nitrogen and hydrogen as the etching process gases. The purpose is to prevent the copper metal layer 202 exposed during the etching process from being oxidized by the etchant. Next, a common dielectric layer 218 is formed to cover the dielectric layer 204 and the plug 216. The material for forming the dielectric layer 218 includes silicon carbide oxide material formed by chemical vapor deposition. The paper size of this paper applies to China National Standard (CNS) A4 specification (210X297 mm). (Please read the precautions on the back before filling in this Page), τ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 556321 A7 B7 V. Description of the invention () (Please read the precautions on the back before filling this page) Electrical layer 218 is a barrier layer, which replaces the conventional one The metal barrier layer is made of a steel metal material that blocks the copper metal layer 214 and diffuses into the surrounding dielectric layer in a subsequent process. A dielectric layer 22 is formed to cover the dielectric layer 218 and the plug 216. The material for forming the dielectric layer 220 includes a porous silicon-containing low dielectric constant material formed by chemical vapor deposition. Finally, the dielectric layers 218 and 220 above the plug 216 are removed by a planarization process until the top surface of the plug 124 is exposed. Line 1 According to the above-mentioned preferred embodiments of the present invention, it is known that the manufacturing method of the copper inlaid interconnects proposed by the present invention is to replace the traditional metal barrier material with a dielectric material, such as silicon carbon oxide, to enhance the barrier layer. Barrier to copper metal diffusion. In addition, in today's processes where the process margin has decreased significantly, it is quite difficult to form a barrier layer of sufficient thickness in a via window and to maintain the process margin of subsequent metal filling. An effective P-leveling layer does not take the practice of forming a barrier layer in the dielectric window first, but after the copper metal plug is completed, the dielectric layer surrounding the plug is removed and then formed on the sidewall of the plug. The barrier layer can greatly increase the process margin and increase the yield of the semiconductor device process. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In addition to the above advantages, ’even if the dielectric layer has changed its electrical properties due to copper diffusion, it is not affected because the dielectric material around the copper metal plug is removed. The electrical properties of the newly formed dielectric layer will depend on the design and will no longer be affected by copper metal diffusion. Of course, the present invention is not only applicable to the process of copper metal plugs or the process of copper metal interconnects. Any process that requires the formation of a barrier layer around a metal layer can be used to form a barrier around the metal layer according to the manufacturing method disclosed in the present invention. Barrier 13 This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 556321 A7 _B7_ V. Description of the invention () layer. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page), OK.% Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210X297 mm)