TW556300B - Direct determination of interface traps in MOSFET's - Google Patents

Abstract

A low leakage charge pumping (CP) method has been implemented for direct determination of the interface traps in ultra-short gate length MOSFET's with ultra-thin gate oxide in the direct tunneling regime (< 30 Å). The leakage current even in a 12 Å to 16 Å gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has been demonstrated successfully for various ultra-thin RTNO-grown and RPN-treated gate oxides in CMOS devices. Moreover, it can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relation to the interface trap generation.

Description

556300 V. Description of the invention ο) Field of the invention The present invention refers to a semiconductor wafer test method, especially an accurate and fast calculation of gate oxide interface defects in metal-oxide-semiconductor field-effect transistor (MOSSFET) elements. (Interface traps) number method. This method can provide-such as the measurement of the number of gate oxide interface defects, the gate oxide film quality monitoring, the effective physical channel length of the device, the evaluation of the reliability of ultra-small components, etc. Detection and analysis. Background In recent years, semiconductor process technology has advanced MOS device technology from sub-micron and deep sub-micron to nanometer scale. According to the International Semiconductor Technology Guidelines (ITRS roadmap) proposed by the American Semiconductor Industry Association (SI A), by the year 2002, the gate line width of the device will be less than 0.1 micron '. The thickness is about 1 2 to 15 Angstroms (A, angstrom). However, a tricky problem occurs with the gate oxide layer at this size-interface traps (Ni0 occur in the gate oxide layer, which will cause carriers to pass through the channel). Defect scattering reduces the carrier's scrolling law (mobi 1 it ty), which affects the operation speed of digital circuits. However, in this thin gate oxide layer, there is no feasible method to accurately D Calculate the number of interface traps (Nit), '556300 V. Description of the invention (2) and used to evaluate the quality of ultra-thin (generally less than 30 Angstroms) gate oxide layer It is known to those skilled in the art that when the thickness of the gate oxide layer of a MOSFET device drops below 30 angstroms, two common effects will occur during the electrical analysis of the device-the direct tunneling gate leakage current (Direct

Tunneling Gate Leakage (DTGL) and quantum mechanical effect. This makes it extremely difficult to accurately perform component electrical analysis and measurement changes. The traditional method used to analyze the amount of defects at the interface of a component is the Capacitance-Voltage (CV) method, which was proposed by Lewis M. Termaη in 1962 (Solid-State Electronics, Vol. 5 (5), ρ · 2 8 5-1 9 9, Lewis M · Terma η, 1 9 6 2). However, this traditional CV method cannot be applied when the above-mentioned DTGL and quantum effects occur seriously. That is, when the thickness of the gate oxide layer is reduced to less than 16 angstroms, the quality of such an element having an ultra-thin gate oxide layer cannot be accurately evaluated by the conventional CV method. In addition, the disadvantages of this traditional CV method include that it must adopt a large-area capacitance test structure; and the measurement results of ultra-small components (especially nanometer components) have poor resolution and accuracy. Another familiar method that can be used to analyze the number of component interface defects is the Charge-Pumping (CP) method.

556300 V. Description of the invention (3) method), this method has been disclosed in many journals, such as I EEE T-ED, Vol. 36, p. 1318-1335, P. Heremans et al., 1989; Proc. SSDM, p. 841-843, SS Chung et al., 1993; IEEE T-ED, Vol. 45, No. 2, p. 512-519, C. Chen et al., 1999; IEEE EDL, Vol. 20 , No. 2, p. 92-94, P. Masson et al., 199. However, this method will still be affected by DTGL. When the thickness of the gate oxide layer is reduced to the direct tunneling range (t qx &lt; 30 angstroms), especially for the measurement of 16 angstroms of ultra-thin gate oxide interface defects, there is no CP method that can accurately, Get satisfactory results quickly and effectively; not to mention ultra-thin gate oxides below 2 angstroms. Therefore, as semiconductor technology advances toward nanometer generation, for ultra-thin gate oxide process technology, it is urgent to find a method that can accurately reduce, quickly and effectively count the number of interface defects, which is used to evaluate the gate Oxide layer growth process / quality of oxide layer. SUMMARY OF THE INVENTION Accordingly, the main purpose of the present invention is to provide an accurate, fast, and effective way to obtain the gate-oxide interface defects (referred to as the channel-gate interface) defects and gate oxide test results of MOSFET devices. .

IH Page 7

556300 V. Description of the invention (4) In short, in order to achieve the above-mentioned object, the present invention provides a method for determining the number of interface defects of the gate oxide layer of a MOSFET element. This method is improved based on the traditional "fixed base (gate pulse) levei CP measurement" method. At the same time, the DTGL leakage current value and the correct CP current value have different frequencies. To obtain a reasonable measurement result. In the process of the method, it mainly includes two steps: (1) construct a measurement interval suitable for low leakage current; (2) remove the parasitic wear through the low leakage current CP method Tunnel leakage current. Among them, the first step is only to find a suitable interval for the gate pulse bias (vg ^ Vgh), and the second step is (a) T% low-frequency CP Measurement method or (b) frequency-increased CP measurement method. The combination of the two can more accurately measure the CP current in the gate oxide layer with a thickness of i 2-6 Angstroms, which is used to calculate the number of interface defects. ; Even gate oxide layers smaller than 12 angstroms are also proven to be feasible on some component samples. In order to allow your reviewers to better understand the features and technical contents of the present invention, please refer to the following about this Detailed description and drawings of the invention. The drawings are for reference and explanation only, and are not intended to limit the present invention. Detailed Description of the Invention The present invention provides a direct and accurate calculation of interface traps between polar oxide layers between advanced M0 SFET elements. , Hereinafter referred to as

Page 8 556300

V. Description of the invention (5) N it) Quantity method. The so-called advanced MOSFET device generally refers to an ultra-thin gate oxide layer (e.g., having an extremely short channel length (eg, the inter-gate length (Lgate) can be less than 1 micron)) and a tunnel leakage current effect category. , T⑽ <30 Angstroms: Beginning to mean M0SFET devices with ultra-thin oxide layers with penetrating leakage current effect range. The drawings and related experimental data attached to the present invention are obtained by testing the nano-level MOS devices using the most advanced integrated circuit manufacturing technology in the contemporary. For example, the mOsfet element · gate oxide layer used here is a rapid high temperature oxygen nitride (Rapid Thermal '

Nitric Oxide (RTN0) process, with an oxide layer thickness of 12-16 angstroms. Among them, part of the 16 Angstrom thickness oxide layer was added with a remote plasma nitridation (RpN) treatment to reduce the tunnel leakage current of the order of 102-10. In order to make this: advanced nano-level components, photoresist exposure and removal technology is used, which makes the actual ·: gate length (Lgate) smaller than the mask exposure length (Lmask) by about 0.04 microns; the actual gate The pole length is designed in the range of 0.07-0. 18 microns. (Note: Of course, this method can also be applied to components with actual gate length greater than 1 micron.)-Please refer to Figure 1 (a). This figure discusses the structure of this low leakage current CP measurement = intention and its leakage current generation. . On the cp measurement architecture, the source and drain are connected to ground, the base is grounded, and a pulse is given on the gate. Here is a description of the given method of the gate pulse)-I fixed the lowest point of the pulse to the potential of Vg, and slowly increased the maximum, the point pulse potential vgh. The principle of the CP method is to pass the MOSFET device channel

556300 V. Description of the invention (6) (channel) switches to the accumulation area at one time and switches to the inversi ο η area at another time. If there is an interface defect between the oxide-channel It will contribute a recombi nation current during this switching process, this current is the charge help, latent (CP) current. Its general formula is: 丨 I cp ^ ax = f wood q * w * L 氺 Nit, I cp, ma is the maximum CP current, f is the gate pulse frequency 1 · 6 '1 0 -1 瘅 lun), W is the channel width, and L / '' 9 is the current channel length. Among them, the charge constant. In addition, this figure also shows that when pg ^ degrees, N! Is the number of interface defects and the thickness enters the category of direct tunneling effect. It will cause gate and gasification. Layer CP measurement accuracy. Electric ions, impact = see figure-(b) The figure below, this figure shows that it is possible to see the parasitic tunneling leakage current with the oxidation ^ measurement. 9 Thickness i Degree f:: Γ The measurement curve usually occurs at 3 ° Question above Angstrom. The CP measurement curves for Ju and Wei usually occur in the gasification layer below 30 Angstroms: 2: Among them, the tunneling leakage current will be serious below 20 Angstroms. "Extreme gasification &gt; What this figure shows is the 1% non-flammable flow. The main sentence is the two steps of the measurement area: (1) Construct a &amp;# ^ ^, 2) suitable for low 2 to remove the parasitic penetration through the low leakage current cp method. — I will follow this in the following discussion.

Page 10 556300 V. Description of the invention (7) Please refer to Figure 2. This figure shows the DC power measured under this CP measurement architecture. Since most gate-to-tunnel leakage currents are contributed by the source and drain terminals, and a small part by the base, the charge pump current can only be measured from the base terminal. Furthermore, in the region where the base terminal current is small (eg, I b &lt; 10-12-1 domain I Β &lt; &lt; 1 CP, max), the minimum V 妁 can be used to set the Vgl value and the maximum V ， Can be used to set V glii, (this area can be used to construct a measurement interval suitable for low leakage). As long as the pulse voltage is given in this range, the measured CP curve will not have too much leakage current. Please refer to Figure 3. This figure shows the CP curve measured under this CP measurement architecture. Among them, since we set the gate pulse bias voltage (V g and V gh) in the region where the base terminal current is very small, an accurate CP can also be obtained in a gate oxide MOSFET device with a thickness of 16 angstroms. Current value. Please refer to Figure 4. This figure shows the relationship between the size of the low base current region (measurement interval of low leakage) and the channel length. As the channel length becomes smaller, the base leakage current also becomes smaller, and this low base current region will become larger. That is, there is more opportunity to measure an accurate CP curve. Please refer to Figure 5. This figure shows the parasitic leakage current generated as the thickness of the oxide layer becomes thinner. Among them, the leakage current of the gate oxide layer treated with RPN is very small, but it causes more interface defects. Furthermore, as the thickness of the oxide layer becomes thinner, even if the aforementioned method of "'low leakage measurement interval'" is used, the CP curve measured in the gate oxide layer of 12 Angstroms is also severely affected.

Page 11 556300 V. Leakage current interference of invention description (8). In order to accurately measure the CP curve and use it to calculate the number of interface defects, we must try to eliminate this parasitic leakage current. Please refer to Figure 6 and Figure 7, which respectively describe two low leakage current CP methods that can remove parasitic tunneling leakage current. If there is a leakage current, either of the following two methods' can remove most of the leakage current. (1) High-low frequency CP method: As shown in Figure 6, the high-frequency (e.g_, high-f = 1MHz) and low-frequency (e · g ·, low-f = 1 〇KHz) CP current curve. The low-frequency CP current curve is completely regarded as the leakage current, and the two are interlinked to provide the correct high-frequency (lMHz) CP current curve. (2) Incremental frequency CP method: As shown in Figure 7, firstly measure the CP current curves of the two approximate frequencies (e · g ·, fi = 2MHz; f2 = 1MHz) (both contain leakage) Current), the two are interlocked to get the correct (ί = △ ff 1 f = 1MHz) CP current curve. As mentioned earlier, the CP current is proportional to f. Of these two frequencies (f and f 2, where f 1> f 2) are generally defined as (f r f 2) Η 1 &lt; &lt; 1.

If the curve 3 in Figure 6 is compared with the curve A in Figure 7, and the results measured at 1 MHz are taken as examples, it can be found that both methods can obtain good results. It is worth noting that due to the second method (increase frequency CPS

Page 12 556300 V. Description of the invention (9) method) The leakage current in the two near-frequency CP curves is more leaky ☆ 'Therefore the result obtained is higher than that of the low-frequency CP method. Figure 6 and Figure 7: Zero cp current value measured by the method, the result is more accurate when the frequency is at °. According to the experimental results of the method of the present invention, the thickness of the oxide layer of the gate electrode should be accurate and effective CP current value of 12A.彳 乃 j is paid Please refer to Figure 8. Here, the non-uniformly distributed interface defect hypothesis is used, and the interface defect between the long channel and short channel components is used. Offset length △ Approximate value. If the interface defects are distributed uniformly, the calculated value of ΔL · can be more accurate. The formulas on which this is based are listed in Table 1. (Note: After finding out △ L, it can effectively eliminate the variation of the effective channel length control error in the extremely small M0SFET caused by the manufacturing process, and the error of CP measurement. Because CP measurement is related to the actual effective area.) ^ Please refer to Figure 9'The maximum Cp current value measured by the frequency-increasing CP method. In five wafers with different oxide layer growth methods in the same lot, the calculated offset length ( 0ffset △ L 0. It is concluded from Figure 9: (1) thicker oxide layer of the gate, because thermal stress caused by thermal process time (thermal stress) is greater, interface defects are greater; (2) gate processed by RPN The oxide layer has a large number of interface defects; (3) The slope can be used to calculate the interface defect amount, and can be used to monitor each system.

556300 V. Description of the invention (ίο) The quality of the oxide layer grown by the process. To sum up, the present invention provides a new CP measurement method for ultra-short channels and ultra-thin gate oxide layer elements of 12 angstroms to 16 angstroms, which can quickly and easily calculate interface defects (N it) Quantity. Regardless of whether the high-low frequency CP method or the frequency-increased CP method mentioned above is used, satisfactory results can be obtained. What has been described above are merely examples of preferred implementations of the present invention. All equal changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

Page 14 556300 Revised diagrams Short and early explanation Figure 2 This measurement accurately measures 16 Angstroms of thickness under the cp measurement architecture Figure 4 shows the length of the element channel versus the length of the DC channel, I leakage current Figure 5 shows the influence of the thickness of the gate oxide layer on the element. It can be found here that the thickness of the ultra-thin oxide layer is reduced, and its leakage current is shown in Figure 6 as a high- and low-frequency CP measurement method—first = 1MHz) and low-frequency (e · g ·, i〇w-f curves (both contain Leakage current), and the line is completely regarded as leakage current, the CP current curve of the two phases (lMHz). The above figure shows the current vs. frequency. The CP measurement curve obtained here. This architecture can interface the number of defects. State I leakage current is generated. With the composition of the gate oxide layer of the parasitic tunneling current in the OCP measurement curve, it will become larger and larger with the composition.

Measure the high-frequency (eg, hi gh-f = lOKHz) CP current separately. The low-frequency CP current can be twisted to get the maximum CP measured by the correct high-frequency measurement. Get two CP current curves (eg, f = 1MHz; f 丨 = 80 0KHz) close to the frequency (both contain 'leakage current'), and the two can be correctly interlocked. (F = △ f = 2OOKHz) CP current curve. The figure above shows the measured maximum CP current versus frequency. Figure 8 is an approximation of the offset length (offse1: length) A L &amp; using the assumption that non-uniform interface defects are generated in the channel region of the MOSFET element. If the interface defect distribution is uniform, the calculated value of ΔL can be more accurate. Figure 9 shows the offset lengths calculated from the measured maximum CP current values (ICP, max) 'in five wafers with different oxide growth methods in the same batch (lot). 〇ffset length)

Page 16 556300 _Case No. 91112024_Year Month Day Amendment Brief description of the drawing △ L〇. Among them, the slope can be used to calculate the oxygen of each process growth

Claims (1)

556300 6. Application scope 1. A measurement method for calculating the number of interface defects in the gate oxide layer of a M0SFET element 'The M0SFET element includes a source, an electrode, a base, and a gate' The gate The oxide layer is located below the gate. The measurement method includes: (1) the two ends of the M 0 SFE element-source, &gt; and pole, base, ground, given pulse of the gate-the pulse is fixed at the lowest Point potential V gl, gradually increase the highest point potential vgh; and (2) perform the low-frequency CP method, remove the CP to measure the leakage current-measure the high-frequency and low-frequency CP curves, take the low frequency as the leakage current, and subtract the leakage current The CP curve of low leakage current is obtained. 2. The measurement method according to item 1 of the scope of patent application, wherein the low-frequency CP current curve is approximately equal to the measured leakage current value. 3. The measurement method as described in item 1 of the scope of patent application, wherein the thickness of the gate oxide layer is less than 30 angstroms. 4 · The measurement method as described in item 1 of the scope of patent application, wherein the thickness of the gate oxide layer is in a direct tunneling regime. For example, if the leakage current is sufficient to affect the thickness range of traditional CP measurement, This is the scope of the present invention. 5. The measurement method described in item 1 of the scope of patent application, wherein the frequencies of the high-frequency and low-frequency pulses vary depending on the M0SFET process, so only the high-frequency frequency P.18 5563 〇 ... The scope of the patent application electricity = to, the CP current measured is mainly contributed by the normal CP current and leakage IL, which is the high-frequency pulse range defined in the present invention, namely The low-frequency pulse range defined by the present invention is as low as the low-frequency frequency. The measured CP current is mainly contributed by /, 1., ..., ..... "M &amp; A 疋 $ / belongs to the current 6 · The measurement method described in item 1 of the scope of patent application, wherein the frequency of the ancient eight τ is greater than 100KΗζ, and the low frequency is less than 100kΗζ. The measurement method described in the scope of application 1 The method can be changed to-the pulse fixes the maximum point potential V gh 'gradually decreasing is /, the two-point lightning gl potential is 8 · — a measurement method for calculating the number of deniers of interface defects in the gate oxide layer of M0SFET elements, the The M 0 SFET element includes a source, an electrode, a back electrode, and a gate. The gate oxide layer is located directly below the gate. The earth test method includes: Λ S (1) Three ends of the M0SFET element- Source, Drain, Base, Ground Gate Fixed pulse-the lowest point potential V gl of the pulse is fixed, and the orientation point potential Vgh is gradually increased; and (2) CP is removed according to the frequency-increasing CP method to measure the leakage current-two CP curves close to the frequency are measured, both The leakage current value is close, and the CP curve of the low leakage ☆ can be obtained by interlocking. 9. The patented method of measuring the voltage of 8 households in this patent 556300 6. Scope of patent application The thickness of the oxide layer is less than 30 Angstroms. 10. The measurement method as described in item 8 of the scope of the patent application, wherein the thickness of the gate oxide layer is in a direct tunneling regime. For example, if the leakage current is sufficient to affect the thickness range of traditional CP measurement, All are within the limits of the present invention. 1 1. The measurement method as described in item 8 of the scope of patent application, where the definition of two close frequencies varies depending on the MOSFET process, so as long as two frequencies are close enough to effectively remove the parasitic leakage current in CP measurement, It is the range of two close frequencies defined by the present invention. 1 2. The measurement method as described in item 8 of the scope of patent application, wherein the two close frequencies are both greater than IKZ. 1 3. The measurement method as described in item 8 of the scope of the patent application, wherein the two approximate frequencies (f and f 2 where fi &gt; f 2) are defined, (f "f 2) / f 丨 &lt; & lt 1 to regulate. 1 4. The measurement method described in item 8 of the scope of patent application, wherein the gate pulse method can be changed to-this pulse fixes the highest point potential V gh and gradually decreases the lowest point potential Vgl. Page 20