TW554288B - Method of single CPU simulator kernel frame technique and its device thereof - Google Patents

Abstract

The present invention provides a simulating device for simulating the operation of any single CPU kernel. The simulating device includes: a register set device having a register set for storing and updating various status values; a decode unit device having a decide unit for analyzing instructions to generate instruction codes based on those status values; an instruction set device having an instruction set for executing corresponding instruction functions based on the instruction codes; a flow control device having a flow control module for controlling the operation flow of the register set, the decode unit and the instruction set. In addition, the present invention also provides a method for simulating the operation of any single CPU kernel. The method comprises: a pre-processing step using the flow control module to execute the processing task before executing the actual task, and if there is an interrupt, checking whether it is a power-off; a fetching instruction step using the flow control module to fetch an instruction for decoding from the memory; a decoding step using the decode unit to decode the instruction fetched from the memory and generate am instruction code; an illegal instruction processing for triggering an illegal instruction interrupt processing if the flow control module decodes the instruction code and determines a failure in decoding; an executing instruction step using the instruction set to execute the instruction function corresponding to the instruction code if the flow control module decodes the instruction code and determines a success in decoding; an interrupt processing step in which the flow control module performs an interrupt service processing based on a predefined interrupt service routine if an interrupt is occurred in executing an instruction; a subsequent process in which the flow control module performs a reset process after completing the execution of the instruction if no interrupt is occurred in executing an instruction.

Description

554288 V. Description of the invention (1) Background of the invention The present invention relates to a method for simulating the operation status of any single central processing core (single CPU) and its use. It uses a common organizational structure and a common workflow framework. The two technologies' cooperate with each cross-platform capability (ava computer language, the architecture can be used as the core framework of any single cpu molding cry.), When developing new computer 0 or 0 or combined language applications, due to the The CPU has not yet been developed or it is not easy to obtain the original project. During the development stage, the helmet method = prove the correctness of the new product. At this time, it is often necessary to first calculate the existing simulation process-the simulator is called the simulator. First generation to help test and verify new product performance. When the application is planned, the core architecture and peripheral debugging tools must be redesigned for the 4-inch nature of the model lake. This process is not only time consuming, economically inefficient, but also complicated, and it is not easy to be correct. Realize the model on the twenty-thousands of shells Therefore, one object of the present invention; should! Program. The core operating status of the single CPU is intended to be processed centrally. The FM is provided-a type to simulate any single-central processing early (Single _ core operating status ^ is a series of similar CPU simulators) The invention is particularly a device for simulating any i (Single cm core operating state k central processing unit register set) device, registered and military. The device includes: responsible for saving and updating various state values; Decode register module 'for value, Decodeunit (Decodeunit) 襞 554288 V. Description of the invention (2) Set' include decoder module, used to parse instructions based on these status values, generate Instruction code; instruction set module (instructioon) device, which contains an instruction set module 'for executing corresponding instruction functions according to the instruction code; flow control module (FlowControl) device, which contains a process control module, Control the register process (RegisterSet), the decoder module (DecodeUnit), and the instruction set module (instructioOnW) with negative shells. The method includes the following steps: Processing (Prepr cess), benefit ^ The process control module executes the processing work before the actual execution of the instruction is started. At this time, if an interruption occurs, the subsequent processing steps are directly performed. · The instruction is fetched and the process control module is used to remove the instruction from the memory. One for extraction and decoding = order; Decode 1 uses the decoder module to interpret the fingers extracted from the memory: Xi ί i :? order code; illegal instruction processing, if the process control module solution = the U code judgment Illegal instruction interrupt processing will be triggered when decoding fails; The flow control module interprets the instruction code and determines that it is decoded into a process interrupt. § HAI instruction set module executes the instruction function corresponding to the instruction code: root two. If the instruction When an interruption occurs during execution, the process control module executes the interrupt service routine for interrupt processing; * continuous processing, if it is in the line, it is broken: the process control module completes the instruction processing

Motorola 68, AMD, Kelly Li, 妗 "# 2 General organizational structure and general work, ϋ ϋ After summarizing their prayer characteristics, based on the entire Java category (clase), Cheng Bei made the unit components and the kinetic energy Work: Λ M proposed a variety of single CPU static built-in and tragic workflow 'can be on page 6 V. Invention description (3) type core universal framework method, using the present invention !: "Set two of this core framework Both the device and its operating device architecture are troubled, i = va, 'remove the redesign of the mold, and the repetition of six days, manpower, and money

^ Quickly implement any single CPU simulator, especially S series of similar simulators. 1. The narrow and special illustration of the diagram is simple and easy to make. The other purposes, features, and advantages can be described in more detail as follows: Schematic diagram of the internal and peripheral devices of the CPU; The figure is a diagram showing the general organizational structure of the present invention; the time is: 3 Intent: According to the general architecture of the present invention, it is preferred to display the relevant modules of each device. work flow chart. The detailed description of the example of flat-clamping K-yoke is not possible. In the application of "processor", the CPU and memory use ΛΓ such as V to store the required phase M information for CPU operation. Two hard disks ::: 部In the program of the memory), there is a piece of two numbers meeting. When the xy is first known, the instruction ADD and the data x and y are temporarily crying;) ri) Interpret and place the relevant result in the data; know that this is an addition instruction After '⑶ will be taken out of the main memory, Beckham, y father to the ALU operation and post-operation; 554288 V. Description of the invention (4) Return to the main memory or back to the hard disk via the main memory for storage. The invention is based on the above-mentioned operating principle, and further develops the device and method of the common framework of the core of the CPU simulator. The description of 'He Dan 4 test Figure 2' The general organizational structure of the present invention can clearly describe any ::-cpu composition . This general organizational structure is divided into process 3 =, register module device, decoder module assembly two control two = Beiyuan and # as the process according to function. Register mode assembly various mimic core various state values. Solution, it has 4 instructions. It has the instruction list: the group Pei Zhi is responsible for parsing the instructions. To point to all legal instructions. Instruction set module device negative multiple ΐ: Γ and V by computer language has no index. And therefore the general object-oriented language (oop) is simple, and 'this, in use ;: C two Irrespective of the type, it can work across platforms due to programs. Use the heart to send; the module of each device of the present invention has a slope of ~ ". . Abstract class mechanism for abstract classes, DecodeUnit abstract classes, others. : IΪ: ί Group: Corresponds to the process control module device, which belongs to the cpu abstract class tfaCeC_and () r; n: —The two members and the decoder point to the boat Λ Γ ^ Γ to the register module, and become the decoder module and Directly pointing to the instruction set module, borrowing 554288 V. Description of the invention (5) Therefore, this category controls the simulated cry on behalf of the entire simulator core; x = all resources. External ’This category is the behavior between modules. 〇Inside, the method traceCommandO rules and refers to the set of modules: For example, the f-process control module will call the decoder module to make the instruction 隼; ^ β # w; its own reference value is passed to the instruction set module The register ^ group uses the resources of the process control module, for example, the temporary storage benefit module: corresponding to the register module device, each of which is the core of the device # & 能 # Use this category to save and update Simulate nuclear rape. The various status values of the CPU enable the CPU to control the module. Each pair is decoded into a core group and fingers are grouped into a Γ horse ί group :: ecodeUnit abstract category. This category has a list of instructions, pointing to all legal instructions, only to decode the Code parameter and return the decoded instruction (e-Code). The group can get the decoded instruction by the above method; K test 'process control module Instruction set module: Instruction abstract _ μ, L orders and executes each instruction represents ... category. Each category definition refers to Fig. 4 '. This is a general working flow chart for generating various devices according to the present invention. This diagram summarizes the general workflow of the inventions, where ',', and ^ inventions, in which the present j = sample CPU is drawn as preprocessing, fetching instructions, decoding, non- ^] workflow rules, interrupt processing, and There are seven parts of the follow-up process, and the second part: 2: management and execution refers to the work to form a general work unit as shown in Figure 4. Describe each part of the pre-processing: the implementation corresponds to the program < 554288 V. Invention description (6) preProcess (). This part is responsible for necessary processing before actually starting to execute the instruction, for example, checking whether an external interrupt occurs. Fetch instruction: Implement the method f etch (Code) corresponding to the program. This part is responsible for extracting an instruction from the cache memory or main memory. 0% code: implement the corresponding method decoder. Do__decode (code). This section is responsible for parsing the instructions.

Illegal instruction processing: The method corresponding to the program in practice i 1 legal Instructi〇Trap (). This part is responsible for triggering an illegal instruction interrupt when the decoding unit cannot decode. Execution command: Implement the method corresponding to the program ins t · exe cut ion (code, this). This part is responsible for executing the resolved instructions and transmitting the resource reference value controlled by the process control module to the instruction set module of the instruction set module device. Interrupt handling: Implement the method corresponding to the program interruptHandler (intrNum). This part is responsible for setting the program counter to the start address of the interrupt routine provided by the computer system when the interrupt signal occurs.

Continue processing: The method corresponding to the program postPr〇cess () is implemented in practice. This part is responsible for necessary processing after the instruction is executed, for example, resetting the flag register. Referring to the flowchart in FIG. 4, in step S41, the process control module ^ first uses a process control module (referred to as a control module) built in a Java program to perform a pre-processing action of the instruction. s42) can be divided into three

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The above-mentioned general workflow is based on the use of non-overridable techniques in the object-oriented program (〇〇p) language, which makes the method traceCommand () in the flow control module used to control the entire CPU 〃1L process cannot be inherited by any The override 'mandatoryly regulates all those who apply the simulator workflow of the present invention. The above-mentioned combination of the device of the present invention and the work flow creates a complete CPU core module ... including a static internal organization and a dynamic execution program. Applying the simulator core program designed by the present invention, a unified framework program is used as the interface between the simulator core and peripheral debugging tools. The unified interface can be increased.

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= Simulator core program and debugging work and a new core program came; when the debugging tool was upgraded, the original although the present invention has a better to limit the invention 'within the spirit and scope of any well-known , It can be regarded as more scope as the compatibility and reusability between the attached patent applications. When the old debugging tools can be linked together, the core programs can also be used directly. The embodiment is disclosed as above, but it is not a person who uses technology, and does not depart from the present invention. Therefore, what is defined by the protection scope of the present invention shall prevail.

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Claims (1)

554288 6. Scope of patent application &, 丨 · A simulation device for simulating the core operating conditions of any single central processing unit (single CPU), including: f Register device (RegisterSet) device, including a register module To save and update various status values with negative shells; use an α-state module (DeCodeunit) device, which contains a decoder module and ^ these status values, parse the instructions, generate instruction codes, and use it to group (InStrUCti 〇n) The device contains an instruction set module to execute each instruction function according to the deduction order code; 'Includes the process control module, the register set, the decoding unit, and the instruction Control module ⑴ 一 ⑽) Control 2 mold circumference = the module is intended to be installed, where 'this process ^ V dagger temporary state object to point to the temporary cry grip two iT code object' is used directly Point to the decoder module, and then point to the instruction set module indirectly, so use the C device core and its operation flow. A simulation device that pulls the chess player model, in which the exhaustion is used to point to all legal instructions, and the order set = w system module can be pointed indirectly through the decoder module. The "4. Such as the patented item} of the simulation device, which is a program written with object-oriented program twister r nnD, Gu Ji Hongshou J 枉 style buckle a (OOP), the program can benefit 554288 6. Scope of patent application It is executed by a computer. 5 · A method for simulating the operation of any single central virtual core, such as: t ^, single CPU, to avoid the situation, including the following steps: s pre-processing, use this process to control the model The group executes the processing work before the execution of the instruction. At this time, if any order actually starts to check whether it is off; if an external interruption occurs, the instruction is fetched, and one of the instructions is used by the process control module; The decoding and decoding are extracted from the hidden body, and the decoder module is used to interpret the command from the memory to generate an instruction code; 丨 ~ k in the body refers to illegal instruction processing. When the decoding module fails, the process control module will Trigger an illegal instruction interrupt; when the instruction code determines that the execution instruction is interpreted by the process control module, it is necessary to use this instruction set module to execute; = is set as the solution function; the instruction interrupt processing corresponding to 7 horses, if the instruction execution When it happens, the group performs interrupt processing according to the preset interrupt service routine; the & process control module 'controls the subsequent processing of the memory system. If no intermediate results occur during the execution of the instruction, and after the instruction processing is completed, Perform reset processing. 6. The method of claim 5 in the scope of patent application, wherein the purpose is a flash memory (CACHE) or main memory in the computer. ’The source of the interruption This method is further advanced. • The method of item 5 in the scope of the patent application, its rotation, and internal triggering when decoding fails. 8 · If the method of applying for the scope of patent No. 5, its application, page 14, 554288 The scope of the process of applying for the scope of patenting, this step determines the shutdown of the entire process, then U; =: =: =: Weiqi: Industrial module (-1 ClaSSh takes this to make the method of the terminal category process of 20 = 1 will not be controlled by any successor, the whole cpu invention simulation device architecture, has Consistent ^ ,,,, and 'functions' to achieve the purpose of the consistent work flow. Page 15