經濟部智慧財產局員工消費合作社印制π 554286 • - A7 *' V - -------：--- B7___ — 五、發明說明（1 ) 【本發明之領域】 本發明係關於一種位元組順序自動轉換裝置，尤指— 種適用於《裝g與週邊界面之位元組順序自動轉^ 置。 【本發明之背景】 隨著資訊產業的發展，電腦裝置與週邊裝置之界面發 展出許多種，例如：小型電腦系統介面（SmallPrinted by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs π 554286 •-A7 * 'V--------: --- B7___ — V. Description of the invention (1) [Field of the invention] The present invention relates to a Byte sequence automatic conversion device, in particular-a type of byte sequence automatic conversion suitable for "g" and peripheral interface. [Background of the Invention] With the development of the information industry, many types of interfaces between computer devices and peripheral devices have been exhibited, such as small computer system interfaces (Small
Computer System Interface，SCSI )、通用串列匯流 排（USB ) 、IEEE 1 3 94、及PCMCIA等週邊界面。其中 PC MCI A卡已被廣泛地使用在筆記型電腦、個人數位助理 裝置（PDA)、後入式系統（Embedded System)。 PCMCIA卡除了可以作為主記憶體的擴充，例如：快閃記 憶體（Flash卡）等，還可設定為輸入輸出界面（1/〇 Interface )，以提供電腦和其他週邊界面進行溝通，例 如·無線網路卡或是藍芽之應用。 然而電腦裝置利用PCMCIA卡和週邊界面進行溝通 時，會發生位元組順序不合之情形，此種情況在嵌入式系 統中更為常見。例如在嵌入式系統中所採用之微處理器為 低位元組優先，但透過PCMCIA卡連接的週邊界面所傳送 之資料流為高位元組優先，此即位元組順序不合之問題。 目前解決即位元組順序不合之之做法為在硬體驅動程 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — I — · I------^---- ί請先閱讀背面之注意事項再填寫本頁) 線·· 554286 經濟部智慧財產局員工消費合作社印製 A7 *' ----：---------- 五、發明說明（二） 在接收資料時必須再增加多餘的指令週期（instructi〇n C y c 1 e )，使得微處理器之效能大大地降低。 發明人爰因於此，本於積極發明之精神，亟思一種可 以解決上述問題之「位元組順序自動轉換裝置」，幾經研 究實驗終至完成此項嘉惠世人之發明。 【本發明之概述】 本發明之主要目的係在提供一種位元組順序自動轉換 裝置，俾能解決微處理器與週邊裝置之位元組順序不符之 問題。 本發明之另一目的係在提供一種位元組順序自動轉換 裝置，俾能減少微處理器處理多餘的指令週期，以提高微 處理器之效能。 為達成上述之目的，本發明之位元組順序自動轉換裝 置係配合一週邊裝置與一電腦裝置，該電腦裝置具有一微 處理器與一第一暫存器，第一暫存器用以暫存微處理器所 要存取之資料，週邊裝置具有一第二暫存器，第二暫存器 用以存取週邊裝置之資料，電腦裝置係以資料訊號、位址 訊號、以及控制訊號來存取週邊裝置，該位元組順序自動 轉換裝置主要包括：一位址解碼器，係接收電腦裝置所發 出之位址訊號來進行解碼，以判斷電腦裝置所要存取之位 址是否在至少一預設之記憶體空間；以及一位元組順序轉 換器’連接於電腦裝置之第一暫存器與週邊裝置之第二暫 存器’以供將第一暫存器之資料寫入第二暫存器，或將第 --------^-------- (請先閱讀背面之事項再填寫本頁)Computer System Interface (SCSI), Universal Serial Bus (USB), IEEE 1 3 94, and peripheral interfaces such as PCMCIA. The PC MCI A card has been widely used in notebook computers, personal digital assistant devices (PDAs), and rear-entry systems (Embedded Systems). The PCMCIA card can be used as an expansion of the main memory, such as: flash memory (Flash card), etc., can also be set as the input / output interface (1 / 〇Interface) to provide communication between the computer and other peripheral interfaces, such as wireless Network card or Bluetooth application. However, when a computer device uses a PCMCIA card to communicate with the peripheral interface, the byte order may occur, which is more common in embedded systems. For example, the microprocessor used in an embedded system has the low byte priority, but the data stream transmitted through the peripheral interface connected by the PCMCIA card has the high byte priority. This is the problem that the byte order is out of order. At present, the method to resolve the out-of-order byte order is to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) to the paper size of the hardware driver. — I — · I ------ ^ --- -ί Please read the notes on the back before filling out this page) Line ·· 554286 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 * '----: ---------- V. Description of Invention (2) When receiving data, an extra instruction cycle (instructioon C yc 1 e) must be added, which greatly reduces the performance of the microprocessor. Because of this, the inventor, based on the spirit of active invention, urgently thought of an "byte sequence automatic conversion device" that can solve the above problems. After several research experiments, he finally completed this invention that benefits the world. [Summary of the present invention] The main purpose of the present invention is to provide an automatic byte order conversion device, which can solve the problem that the microprocessor and peripheral devices do not have the same byte order. Another object of the present invention is to provide a byte order automatic conversion device, which can reduce the unnecessary instruction cycle of the microprocessor to improve the performance of the microprocessor. In order to achieve the above-mentioned object, the byte order automatic conversion device of the present invention is matched with a peripheral device and a computer device. The computer device has a microprocessor and a first register. The first register is used for temporary storage. For the data to be accessed by the microprocessor, the peripheral device has a second register. The second register is used to access the data of the peripheral device. The computer device uses the data signal, address signal, and control signal to access the peripheral device. Device, the byte sequence automatic conversion device mainly includes: an address decoder, which receives the address signal sent by the computer device to decode to determine whether the address to be accessed by the computer device is at least one preset Memory space; and a tuple sequence converter 'connected to the first register of the computer device and the second register of the peripheral device' for writing the data of the first register to the second register , Or the first -------- ^ -------- (Please read the items on the back before filling this page)
本紙張尺度聊中國國家標準（CNS)A4規格(210 X 297公分 A7 * 經濟部智慧財產局員工消費合作社印製 、發明說明（3二暫存器之資料寫入第一暫 斷電腦奘菩、“士 暂存詻其中，如位址解碼器判 =裝f所要存取之位址係在至少-預設之記憶體空間 存哭、—存《同、低位元組資料分別寫入第二暫 时又低、向位元組，或將第二暫存料分別寫入第-暫存器低、…广“位兀組資 左M 一 $仔純㈤位兀組，否則，係將第—暫 7^、低位元組資料分別寫人第二暫存器之高、低位 輕户叩ί將第—暫存高、低位S組資料分別寫入第-ΐ存咨向、低位元組。 、由於本發明構造新穎，能提供產業上利用，且確有增 進功效，故依法申請發明專利。 為使查委員能進一步瞭解本發明之結構、特徵 及其目W，㈣以圖示及較佳具體實施例之詳細説明如后： 【圖式簡單説明】 第1圖係頌示使用本發明之位元組順序自動轉換裝置之系 統架構圖。 第2圖係本發明中電腦裝置與週邊界面之示意圖。 第3Α圖係本發明中記憶體與週邊界面之存取位址。 第3Β圖係本發明中位元組順序轉換與不轉換之示意圖。 第4圖係本發明之位元組順序轉換器之功能示意圖。 【圖號説明 電腦裝置 微處理器 11This paper scale talks about Chinese National Standard (CNS) A4 specification (210 X 297 cm A7) * Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the description of the invention (32 The information in the temporary register is written in the first temporary computer "Shishi temporary storage, where, for example, the address decoder determines that the address to be accessed is stored in at least-the default memory space,-" the same, low byte data is written to the second temporary Time, low byte, or write the second temporary stock to the-register low, ... wide "bit group group left M one $ Zi pure bit group, otherwise, the first- Temporary 7 ^, low byte data is written to the high and low light households of the second temporary register, and the first-temporary high and low group S data is written to the -storage reference and low byte respectively. Because the present invention has a novel structure, can provide industrial use, and indeed has an enhanced effect, it has applied for an invention patent in accordance with the law. In order to enable the investigating committee to further understand the structure, characteristics, and purpose of the present invention, it is illustrated and better specific The detailed description of the embodiment is as follows: [Simplified illustration of the figure] Figure 1 shows the use of the present invention System architecture diagram of byte order automatic conversion device. Fig. 2 is a schematic diagram of a computer device and peripheral interfaces in the present invention. Fig. 3A is an access address of a memory and a peripheral interface in the present invention. Fig. 3B is a version Schematic diagram of byte sequence conversion and non-conversion in the invention. Figure 4 is a functional diagram of the byte sequence converter of the present invention. [Figure number illustrates computer device microprocessor 11
--------^----- (請先閱讀背面之注意事項再填寫本頁) 線擎 五 、發明說明（+) 週邊界面 位址解碼器 第一切換單元 第三切換單元 第—暫存器 12 第二暫存器 21 位元組順序轉換器4 第二切換單元 42 第四切換單元 44 【較佳具體實施例之詳細説明】 為關本發明 <位隸順序自動轉換裝置之—較佳實系 例’敬請參照第I圖顧示徒用μ 一 之…… 組順序自動轉換裝濯 广木構圖，其係由電腦裝置〗、週邊裝置2、位址解碟 處理哭f序轉換器4等組成。其中電腦裝置1具有微 器2二與弟-暫存器12，週邊裝置2亦具有—第二暫存 上述之電腦裝^於本例中較佳地為一後入式系統之 廷腦裝置，週邊裝置2於本例中較佳地為一 ρ_ΐΑ之乙 太網路卡。微處理器u係與第—暫存器12相連接，位址 解碼器3係位於電腦裝置1與週邊裝置2之間。位元組順序 轉換器4則分別與第—暫存器12及第二暫存器川目連接。 第2圖顯示電腦裝置丨與週邊裝置2進行溝通之示意 $週k裝置2與電腦裝置i進行溝通（即存取）時係經由 ^二暫存器21 ’使得微處理S11能藉由資料匯流排存取 第二暫存器21内所暫存之資料。 、當微處理器11以資料訊號、位址訊號、以及控制訊號 對週邊裝置2進行存取動作時，微處理器工工或週邊裝置2 本纸張尺度適用中國國豕標準(Chlb)A4規格-------- ^ ----- (Please read the precautions on the back before filling this page) Line Engine V. Invention Description (+) Peripheral Interface Address Decoder First Switching Unit Third Switching Unit The first register 12 the second register 21 byte sequence converter 4 the second switching unit 42 the fourth switching unit 44 [detailed description of the preferred embodiment] is related to the present invention < automatic conversion of bit sequence Device—Better Realization Example 'Please refer to Figure I. Gu Shitu used μ one of ... The group sequence automatically converts the decoration of the wide wooden structure, which is processed by the computer device, the peripheral device 2, and the address discarding process. Cry sequence converter 4 and other components. Among them, the computer device 1 has a microcomputer 22 and a brother-temporary register 12, and the peripheral device 2 also has a second temporary storage of the above-mentioned computer device ^ In this example, it is preferably a court-type device of a post-entry system. The peripheral device 2 in this example is preferably an Ethernet card with ρ_ΐΑ. The microprocessor u is connected to the first register 12, and the address decoder 3 is located between the computer device 1 and the peripheral device 2. The byte order converter 4 is connected to the first register 12 and the second register Kawame, respectively. Figure 2 shows the schematic diagram of the communication between the computer device and the peripheral device 2. The communication (ie, access) between the device 2 and the computer device i is performed through the two registers 21 ', so that the micro-processing S11 can be streamed by the data. Rows of data temporarily stored in the second register 21 are accessed. When the microprocessor 11 accesses the peripheral device 2 with a data signal, an address signal, and a control signal, the microprocessor worker or the peripheral device 2 applies the paper standard of China (Chlb) A4.
------ίιτ---------^ . (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 554286 ----1_；___B7 -------—— 五、發明說明（5 )------ ίιτ --------- ^. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 554286 ---- 1_; ___B7- ---------- V. Description of invention (5)
係將資料暫存於第一暫存器12或第二暫存器21，並將位 址訊號與控制訊號送至位址解碼器3以進行解碼處理。該 控制訊號用以對週邊裝置2致能動作。若解碼後之位址位 於一預設之記憶體空間，例如記憶體位址 0x02020000〜0x02040000 (併請參照第丨圖與第3A 圖），由於此一記憶體區塊為PCMCIA之輸出輸入資料 (I/O Read Write)空間，而PCmciA卡在做I/O讀寫 所使用的位元組順序與微處理器丨丨不相符，故位址解碼器 3發出一訊號至位元組順序轉換器4，以對暫存於第一暫存 器1 2或第二暫存器2 1之暫存資料進行位元組順序轉換， 其中該預設之1己憶體空間為對應至P C M C J A卡之輸出輸入 資料空間。如當解碼後之位址位於記憶體空間 0x02000000〜0x02020000，由於此一記憶體區塊為 PCMCIA之組態（Configuration)空間，其位元組順序 與微處理器11相同，故不對暫存於第一暫存器12或第二 暫存器2 1之暫存資料進行位元組順序轉換。 4 第3 B圖則顯示位元組順序轉換器4對資料進行位元組 轉換與不轉換之示意圖，當位元組順序轉換器4進行轉換 時即將高位元組中資料存取於低位元組中，低位元組中資 料則存取於咼位元組中。而位元組順序轉換器4不進轉換 時，則高位元組中資料存取於高位元組中，低位元組中資 料則存取於低位元組中。 第4圖則更進一步顯示位元組順序轉換器4之功能示意 圖，位元組順序轉換器4於本例中較佳為採用複雜型可程The data is temporarily stored in the first register 12 or the second register 21, and the address signal and the control signal are sent to the address decoder 3 for decoding processing. The control signal is used to enable the peripheral device 2 to operate. If the decoded address is in a preset memory space, such as the memory address 0x02020000 ~ 0x02040000 (please refer to Figures 丨 and 3A), because this memory block is the input and output data of PCMCIA (I / O Read Write) space, and the order of bytes used by the PCmciA card for I / O reading and writing does not match the microprocessor 丨 丨, so the address decoder 3 sends a signal to the byte order converter 4 To perform byte order conversion on the temporarily stored data temporarily stored in the first register 12 or the second register 21, where the preset 1 memory space is the output input corresponding to the PCMCJA card Data space. For example, when the decoded address is in the memory space 0x02000000 ~ 0x02020000, since this memory block is the configuration space of PCMCIA, its byte order is the same as that of the microprocessor 11, so it is not temporarily stored in the first place. The temporary data of one register 12 or the second register 21 performs byte order conversion. 4 Figure 3B shows the byte sequence converter 4. The byte conversion and non-conversion of the data is shown. When the byte sequence converter 4 converts, the data in the high byte is accessed to the low byte. The data in the middle and low bytes are accessed in the high byte. When the byte order converter 4 does not perform conversion, the data in the high byte is accessed in the high byte, and the data in the low byte is accessed in the low byte. Fig. 4 further shows the functional schematic diagram of the byte sequence converter 4. The byte sequence converter 4 in this example preferably uses a complex programmable process.
本紙張尺度適用宁關家標準（CNS)A4 ⑵G χ挪公爱） 554286 A7 B7 五、發明說明（6 ) =邏輯元件（c〇mplex ProgrammaMe lThis paper size applies the Ningguan Family Standard (CNS) A4 ⑵G χ Norwegian public love) 554286 A7 B7 V. Description of the invention (6) = logic element (complex ProgrammaMe l
DeViCes，CPLD)。其内部具有第一切換單元* 二 訂' 切換單TC42、第三切換單元43、以及第四切換單元 ^等效之切換單元。其中，第—切換單㈣連接於第— 暫存:1_2乙高位元組與第二暫存器21之高位元組；第二 =換單元42連接於第—暫存器12之低位元組與第二暫存 态2^1乏低位兀組；第三切換單元“連接於第—暫存器η 之高位元組與第二暫存器21之低位元組；第四切換單元 44連接於第一暫存器12之低位元組與第二暫存器21之高 位元組。當位址解碼器3將所接收到之位址訊號解碼後: 若該解碼後之位址位於預設之記憶體空間 yx02020000〜〇x0204〇〇〇〇則發出一位元组順序轉換訊 唬至位元組順序轉換器4，此時，第一切換單元4丨與第二 切換單元42將斷路，第三切換單元43與第四切換單元= 則導通，以使知第二暫存器2 i之低位元組資料能寫入第一 暫存器12之高位元組中，且第二暫存器21之高位元組資 料能寫入第-暫存器12之低位元組中，以完成位元組順序 轉换。 當位元組順序轉換器4不進行轉換動作時，則第一切 換單元41與第二切換單元42將導通，第三切換單元y與 第四切換單元44將斷路，使得第二暫存器2丨之低位元組 負料忐寫入第一暫存器12之低位元組中，第二暫存器2^ 之向位元組資料能寫入第一暫存器1 2之高位元組中。 本紙張尺度適用中關家標準（CNS)A4規格⑵Q x 297公发「 Β7 Β7 五 、發明說明（7) 由以上之説明可知，*政n 解碼後之位址是否需進奸位址_器判別 組順序轉換器來切換::::：，並利用-位元 =:T時所發生之位元組順序不符之問題， 吾微處理器花費過多指令週期於轉換位元組順序， 而可大幅提高微處理器之效能。 一 τ、尸斤陳本發明播論就目的、手段及功效，在在均 ^ττ其1Q異於習知技術之特徵，為實為—極具實用價値之 :明’懇％ #審查委員明察，早日賜准專利，俾嘉惠社 曰，，實感德便。惟應注意的是，上述諸多實施例僅係為了 更方、尤月而舉例而已，本發明所主張之權利範圍自應以申 叩專利範圍所述為準，而非僅限於上述實施例。 經濟部智慧財產局員工消費合作社印製DeViCes, CPLD). It has a first switching unit * two order switching unit TC42, a third switching unit 43, and a fourth switching unit ^ equivalent switching unit. Among them, the first-switching unit is connected to the first-stage buffer: 1_2 high-order byte and the high-order byte of the second register 21; the second = change unit 42 is connected to the low-order byte of the first-stage register 12 and The second temporary storage state 2 ^ 1 lacks a low-order group; the third switching unit is “connected to the high-order byte of the first register η and the low-order byte of the second register 21; the fourth switching unit 44 is connected to the first The low byte of a register 12 and the high byte of a second register 21. When the address decoder 3 decodes the received address signal: if the decoded address is in a preset memory The body space yx02020000 ~ 〇x0204〇〇〇 will send a byte order conversion message to byte order converter 4, at this time, the first switching unit 4 丨 and the second switching unit 42 will be disconnected, the third switching Unit 43 and the fourth switching unit = are turned on, so that the low byte data of the second register 2 i can be written into the high byte of the first register 12 and the high bit of the second register 21 The byte data can be written into the lower byte of the-register 12 to complete the byte order conversion. When the byte order converter 4 does not When the switching operation is performed, the first switching unit 41 and the second switching unit 42 will be turned on, and the third switching unit y and the fourth switching unit 44 will be disconnected, so that the low byte of the second register 2 will be negatively written. Into the low byte of the first register 12, the byte data of the second register 2 ^ can be written into the high byte of the first register 12. The paper standard applies the Zhongguanjia standard (CNS) A4 specifications ⑵Q x 297 publicly issued "Β7 Β7 V. Description of the invention (7) From the above description, we can know whether the decoded address needs to be entered into the address_device discrimination group sequence converter to switch: ::::, and taking advantage of the problem that the byte order does not match when -bit =: T, our microprocessor spends too many instruction cycles to convert the byte order, which can greatly improve the performance of the microprocessor. A τ, corpse Chen, the present invention on the purpose, means and effects, in the mean ^ ττ 1Q is different from the characteristics of the conventional technology, it is practical-very practical: '' 明 ％ #auditing member Mingcha As soon as the quasi-patent was granted, the Jiahui Society said, "I have a real sense of morality. But it should be noted that many of the above Example In order to more side only and, in particular month and example only, the scope of the appended claims to apply the present invention to be self-tapping patentable scope of the subject, not limited to the above embodiments. Economic Intellectual Property Office employee printed consumer cooperatives