TW550808B - Bi-directional fn tunneling flash memory - Google Patents

Abstract

A low-voltage nonvolatile memory array including a substrate is disclosed. A cell well of first conductivity type is provided in the substrate. Columns of buried bit lines of second conductivity type are formed within the cell well, wherein the columns of the buried bit lines are isolated from each other, and each of which is further divided into plurality of sub-bit line segments with deeply doped source wells of first conductivity type connected to the cell well of first conductivity type. A plurality of memory cell blocks are serially arranged over one of the columns of buried bit lines, wherein a memory cell block corresponds to a sub-bit line segment, and each of the memory cell blocks comprises at least one memory transistor having a stacked gate, a source and a drain. A local bit line overlying the memory cell blocks and is electrically connected to the drain of the memory transistor via a contact plug short-circuiting the drain and the subjacent buried bit line.

Description

550808

In the field of the invention, the present invention provides a non-volatile (nonvolatile) memory, especially a low-voltage bidirectional (flo-directional) write-erase flash memory. With low power consumption and compatible operation mode, it can be integrated on a single chip to produce high-speed code flash memory (code flash) and high-density data flash memory (data flash). Background: In recent years, as the demand for portable electronic products has increased, flash memory (f 1 ash) or electrically erasable programmable read-only memory (electrically erasable programmable read-only memory, (Referred to as EEPROM) technology and market applications are also increasingly mature and expanded. These portable electronic products include digital camera negatives, mobile phones, video game apparatus, personal digital assistant (PDA) memory, telephone χ recording devices, and programmable ICs. Flash memory system is a kind of non-volatile memory (non_volatile memory), and its operating principle is to change the threshold voltage of the transistor or memory cell (threshold voltage) to control the opening or closing of the corresponding gate channel to achieve memory data The purpose is to prevent the data stored in the memory from disappearing due to power interruption. — &Amp; @ 言, flash memory can be divided into N0R type and NAND type architecture, of which N0R type flash memory is fast to read, suitable for program conversion to ^

550808 V. Description of the invention (2) Code flash memory (Ccode f lash) products, and NAND flash memory has high density, which is suitable for data flash memory (data f1 ash) ) ° Please refer to FIG. 1, which is a schematic cross-sectional view of a conventional NAND-type EEPROM 10. As shown in FIG. 1, the NAND-type EEPR0M 10 includes an N-type semiconductor substrate 12 and a P-type semiconductor well 14, which are disposed in the N-type semiconductor substrate 12 and a plurality of NAND memory string blocks (NAND cel 1 bloclOBp B2 ~ BN, They are arranged in the same column (column) and formed on the P-type semiconductor wells 14 and a local bit line (local bi t 1 ine) BLi, which are set in a plurality of NAND memory string blocks B2 to B. Note that It is to be noted that the NAND-type EEPROM 10 further includes other rows of NAND memory string blocks arranged in parallel with the plurality of NAND memory string blocks B2 to B in the row, and is also formed on the common P-type semiconductor well 14. Each The NAND memory string blocks B !, B2 ~ B are connected in series with a plurality of floating gates with N M 0 S memory cells (mem 〇ryce 1 1) Μ 〇 ～ Μ n. Each memory cell Μ 〇 ~ M n is It has a stacked gate structure, that is, an upper control gate 20 and a lower floating gate 22. Each end of each NAND memory string block B r B 2 ~ B & A bit line selects the transistor SGB and a source line selects the transistor SGS, where One terminal of the transistor SGB is electrically connected to the bit line Bh, and one terminal of the transistor SGS is electrically connected to a source line SL. For the aforementioned NAND-type EEPROM 10, when an edit mode is performed , You must apply a high voltage (such as 20 V) to the selected word line square t

550808 V. Description of the invention (3)

d? ΐ y. On the same day temple, for the non-selected character line, it also requires two or more small voltages (such as 12V) to channel (channe I port j: the encoding speed will also appear slow and inefficient. In addition ,: ^ Ask about the existence of voltage, and there may be problems in reliability. Second, junction breakdown and excessive erasure of H2 f, due to the conventional ΝΑ〇 flash memory and _ type flash, memory The operation methods are different, so it is difficult to integrate the two in a single flash. ^ Since the NAND flash memory is used for data flash memory, it is mainly used fn when encoding. With the coding method, Ushi is used, and the flash memory is used for code flash memory (except code ，, it is known that the coding is mainly performed by hot carrier coding method. This flash memory occupies more Wafer area, so the production cost is high. SUMMARY OF THE INVENTION Therefore, too α

Ah, but the operation under the voltage can extend the life of the portable electronic device. The main purpose of the present invention is to reduce the use time of the low-red +, ice-consuming field non-volatile memory pool.

Page 8 550808

Another object of the present invention is to provide an electronically erasable and codeable memory that can simultaneously integrate a high-density NAND-type flash memory and a Jing-speed NOR-type flash memory on a single chip, thereby reducing production-male, Degrees. -Another object of the invention is to provide an electrically erasable and programmable memory with an independent buried area bit line, which can perform fast bidirectional FN tunneling and writing erasing. Action (bi-directional FN write / erase). Another object of the present invention is to provide an integrated single chip, bidirectional FN tandem (Bi AND) electronically erasable codeable read-only memory, and a dual transistor-bidirectional FN parallel type (2T-BiNOR). It can be electronically wiped, coded and read, and has a compatible operating mode. " In order to achieve the above-mentioned object, the present invention provides a low-voltage array, including a substrate; 'a first conductive type memory cell "doped; (cell well) formed in the substrate; a plurality of rows second A conductive type buried bit line is formed in the memory cell common doping well. 1 The second conductive type buried bit line is isolated from each other and ^ one buried = one conductive type deeply doped source electrode. The segment is a plurality of human-bit lines & wherein the first conductive type deeply doped source electrode and the first conductive type memory cell share a doping well electrical connection; a plurality of string blocks are formed in a single line. The plural lines of embedded bit lines have =

Page 9 550808

5. Description of the invention (5), each of the plurality of memory blocks corresponds to one of the plurality of sub-bit line sections, and each of the plurality of memory blocks includes at least one memory transistor, and the memory transistor includes There is a stacked gate, a source and a drain, and a region bit line is parallel across the plurality of serially arranged memory blocks, and is electrically connected to the drain of the memory transistor through a contact plug. Are connected, and the beta contact plug causes an electrical short circuit between the remote electrode and the buried bit line below it. • The present invention provides a non-volatile memory element, which includes a base =: = the first conductive type memory cell shares a doped well formed in the substrate; = 仃 the second conductive type buried bit line is formed in The memory cells share an imagination well, in which the plurality of rows of the second conductivity type buried bit lines are isolated from each other, and each buried bit line is further doped by a plurality of first conductivity type deeply doped sources. The pole segmentation is a plurality of sub-bit line regions. The source is shared with the first conductive memory cell. J A series of memory blocks arranged in a shame, formed on a single row and embedded in the plurality of lines, where each of the plurality of memory blocks corresponds to one of several sub-line sections, and each The plurality of memory blocks each include a second memory transistor. The memory transistor includes a control gate, a floating gate below the control gate, a source, and a drain; Each of the plurality of character lines is connected to a corresponding gate of the f transistor; an area bit line is arranged across the memory block of the plurality of non-columns in parallel, via a contact The plug is electrically connected to the memory electrode 4 and the pole, and the contact plug makes the drain electrode and the electrode below it

Page 10 550808 V. Description of the invention (6) The embedded bit line forms an electrical short; and a plurality of rows of main bit lines. The plurality of rows of the second-conduction-type buried bit lines are isolated from each other by using a shallow trench insulation (sh a 1 110 w trench isolation). According to a preferred embodiment of the present invention, the first conductive type deep doped source well system is used as a source of the memory transistor. Also, according to another preferred embodiment of the present invention, each of the plurality of memory blocks further includes a selection transistor having one end electrically connected to a source of the memory transistor, and the first conductive type is deep. The doped source is used as the source of the selective transistor. In addition, according to another preferred embodiment of the present invention, each of the plurality of memory blocks includes a plurality of memory transistors, which are connected in series to form a NAND memory array. In order to make your reviewers understand the features and technical contents of the present invention more closely, please refer to the following detailed description and accompanying drawings of the present invention. However, the drawings are for reference and description only, and are not intended to limit the present invention. Detailed description of the invention Please refer to FIG. 2 (a). FIG. 2 (a) is a partial cross-sectional structure diagram of the EEPR0M 100 according to the first embodiment of the present invention. As shown in Figure 2, EEPR0M 100 is a low-voltage bidirectional FN write / erase NAND-type flash memory array architecture, which includes a P-type semiconductor deep well (hereinafter referred to as deep P-wel)

550808 V. Description of the invention (7) DPW) 'A memory cell with N-type wells (ce 1 1 N-we 1 1, hereinafter referred to as CNW)' A plurality of rows arranged in parallel and isolated from each other by a shallow trench insulation area A P-well (shal low P-wel 1, hereinafter referred to as SPW) is used as a buried bit line. In Fig. 2 (a), only one of the plurality of lines SPW is displayed: SPW1. A plurality of NAND memory string blocks (NAND cel 1 block) are arranged in a same row (coiumn) and formed on SPW1, and a local bit line (hereinafter referred to as LBL) is provided in a plurality of Above the NAND memory string block. To facilitate the description of the present invention, only the NAND memory string block Bp B 2 is shown in Fig. 2 (a). Those skilled in the art know that η-2 N A N D memory string blocks can of course be inserted between B and B A on the same line, where η is generally 16. Still referring to FIG. 2 (a), each NAND memory string block B ρ Β information includes a plurality of floating gates connected to the NMOS memory cells M0 ~ M15. In other words, according to the first preferred embodiment of the present invention, the NAND memory application block B ρ B includes 16 memory transistor units or memory cells M 0 to M 5. Each memory cell M0 ~ M! 5 has a stacked gate structure, that is, the upper word line W L0 ~ W L i and the lower floating gate (f 1 0 a t i n g gate). Since the structure of the memory transistor unit is not the focus of the present invention, its detailed structure will not be described again. NAND memory string block B & — one end is a source line selection transistor SGS and one end of the source line selection transistor SGS1 is electrically connected to the source of the NAND memory string block NM0S memory cell L, and the other end is connected to a The source line SL is electrically connected to control the read voltage. At the other end of the NAND memory string block, a contact plug 102 and NAND memory

Page 12 550808 V. Description of the invention (8) The string block B1 ^ NMOS memory_cell M (^ drain 106 is electrically connected. As shown in the dotted circle in Figure 2 (a), the 'contact plug 102 extends downwards into And contact with SPW1, even if NM0S memory cell drain 106 and SPW1 form an electrical short state. The contact plug 102 is electrically connected to a regional bit line lbl upward. The regional bit line LBL passes through a contact plug 2 0 2 It is electrically connected to one terminal of a main bit line selection transistor. Among them, the main bit line selects a transistor and a body SGB grandson as a control switch for controlling whether the main bit line MBL voltage is transmitted to the regional bit line. Similarly, NAND memory The string block BA-end is a source line selection transistor SGS 2. One end of the source line selection transistor SGS 2 is electrically connected to the N Μ 0 S memory cell Μ & source of the NAND memory string block b 2, The other end is electrically connected to a source line sB, which can be used to control the read voltage. At the other end of the NAND memory string block B, a contact plug 104 and the NMOS memory cell m15 of the NAND memory string block B are drawn. The pole 108 is electrically connected. The contact plug 104 extends downward and contacts the SPW1, even if the NMOS memory cell ^ Drain 108 and SPW1 form an electrical short circuit state. Please refer to Figure 2 (b) and Figure 2 (c), where Figure 2 (b) is an enlarged top view of a portion of EEPROM 100 in Figure 2 (a) 'Figure 2 (C) is a schematic cross-sectional view of FIG. ^ (B) along the tangent line AA ′. The EEPROM 100 of the present invention further includes a plurality of N AND memory string blocks B Γ B 2 arranged in parallel with the row (C 1). The other rows (C 2 and C 3) NAND memory string blocks are formed on the non-common SPW 2 and SPW3, respectively. Please refer to Figure 3 (a) and Figure 3 (b), of which Figure 3 (a) is the basis The hair

Page 13 550808 V. Description of the invention (9) Partial cross-sectional schematic diagram of the second embodiment E E P R 0 Μ 3 0 0 is shown. Figure 3 (^) is an equivalent circuit diagram of Figure 3 (a). As shown in Figure 3 (a), EEPR0M 300 is a low-voltage bidirectional FN write / erase NAND flash memory array architecture. It includes a DPW, a CNW, a plurality of rows arranged in parallel and insulated by a shallow trench. The isolated SPWs of a region, a NAN D memory_block B, are arranged in the same column (column) and formed on the SPW, and a regional bit line (LBL) is provided above the NAND memory string block. The NAND memory string block B includes a plurality of serially connected NM0S memory cells (memory cel 1) M0 ~ M7 with floating gates. In other words, according to the second preferred embodiment of the present invention, the NAND memory string block b contains 8 memory transistor units or memory cells M 0 to M 7. Each of the memory cells M ′ and M ′ has a stacked gate structure, that is, upper word lines WL0˜WLf 乂 and lower floating gates. One end of the NAND memory string block B is a source line selection transistor SGS 'which has a structure similar to each memory cell M0 ~ M7', that is, it also has a control gate and a floating gate. However, the source line selects the control gate and floating gate of the transistor SGS for electrical connection. One end of the source line selection transistor SGS is electrically connected to the NM0S memory cell source of the NAND memory_block B, and the other end is electrically connected to a source line SL, which can be used to control the read voltage. At the other end of the NAND memory string block B, a contact plug 302 is electrically connected to the NM memory cell M of the NAND memory string block B like a drain. The contact plug 3 2 extends downward and contacts the SPW, even if the NM drain of the NMOS memory cell and the SPW form an electrical short-circuit state. The contact plug 3 0 2 is electrically connected to a regional bit line LBL. The area bit line LBL is electrically connected to a main bit line selection transistor SG Β & via a contact plug 202, wherein the main bit line selects the transistor SGB / series as the control main bit line 0L voltage Whether to pass in regional bit lines

Page 14 550808 V. Description of the invention (ίο) '---- Control switch. As shown in Figure 3 (b), by using ^^ ΐ 仞 ΐ 仞, ΐ 仞, ®, 仏 Tj 70 lines to select the transistor SGB control theme το line Λbl, the source line selects the transistor signal, this Invented EEPROM 30. The FN write / erase action type line that can perform low voltage operation through the pole (ie SPW) is shown in Figure 4u) and Figure 4 (b). Figure 4 (3) is a memory cell operation of the present invention. A schematic cross-sectional view, and Fig. 4 (b) shows the operating conditions of the single memory cell of Fig. 4 (a) according to the present invention in various modes. It should be noted that the operating conditions listed in Figure 4 (b) are only the operating conditions of the selected memory cell, and the operating conditions of the unselected memory cell are not listed. As mentioned above, the NAND $ fe cell line of the present invention is formed on a separate spw, which acts as an embedded bit line. The regional bit line LBL is electrically connected to the SPW through a plug extending into the substrate. With this architecture, the BiAND-EEPROM of the present invention can perform low-voltage FN tunneling write / erase operations. As shown in Figure 4 (a), during operation, the control gate 4o of the memory cell 400 applies the -word line voltage V WL, and the drain 4 0 3 of the memory cell 4 0 applies a bit. Element line voltage VBL. Since the SPW and the drain electrode 40 3 are electrically shorted by a plug 40 5, the potential of the SPW is the same as the drain electrode 40 3. The source 404 of the memory cell 400 applies a source voltage V SL, and the DPW of the memory cell 400 applies a well voltage V dpw. The floating gate 4 2 of the memory cell 4 0 remains floating (f 1 0 a t i n g). As shown in Figure 4 (b), during the erasing operation, v bl is in a floating state, v n: 1 0 V, V SL 2-8 V, and V DP -8 V. Under this condition, the floating gate 4 2 will be injected with electrons through the F N tunneling mechanism, so that the memory cell 4 00 is adjusted to have a relatively high starting voltage state (higher VTH). For example,

Page 15 550808 V. Description of the invention (11) For example, 1.5V < VTH < 3.5V. When writing or 5V, VWL =-10V, VSL is floating state, v —, v ,,. In idle, VBL = floating gate 40 2 will be thundered through the FN tunneling mechanism. Under this condition, the memory cell 40 0 is adjusted to have a relatively low initial strength, so that VTH is recorded). For example, VTH < -IV. Reading memory cells, forgive me (lower

= 〇V, VSL = 1 · 5V, VDP body 0V. "Ον, VWL Please refer to Figure 5 (a) to Figure 5 (c), Figure 5 (

The erase operation of BiAND-EEPROM memory and write to H (c) are schematic diagrams of fetch operation respectively. As shown in Fig. 5 (a), the erasing of wrestling and reading J NAND ^ ^ wl0 ^ wl7, 'Λ ^ Λ t voltage vn = 10V, the bit line BLA BL is in a floating state, the source line, -8V, the gate voltage of the bit line selection transistor SGB is _8v, 1 = the gate voltage of the selection transistor SGS is _6 v. Under the foregoing conditions, the f 1 will pass through the FN tunneling mechanism at the same time The electrons are injected into the floating ^ ft of each memory cell, so that the memory cell is adjusted to a state with a relatively high starting voltage (CVTH), for example, 1.5V < VTH < 3.5V. As shown in Figure 5 (b) It is shown that during the write = encode (encode) operation, the selected zigzag line WL shall not be applied with the f-yuan line voltage of 〇 ¥, and the other daughter cell lines WL of the memory cell that are not selected in the NAND memory string 〇 ～ WL and WL 4 to WL 7 both apply the word line voltage V WL = 0 v, the selected bit line BL defect plus a 5 V bit line voltage, and the unselected bit line BL i is grounded. The source line voltage v SL is in a floating state. The bit line selects the transistor 1 and the gate voltage of the body SGB is 7V, and the source line selects the transistor SGS and the gate voltage is 0 V. Under the aforementioned conditions, it is selected. memory Will pass through the fn pass-through mechanism page 16 550808 V. Description of the invention (12) At the same time, the electrons are pulled out of the floating gate of the memory cell, so that the memory cell is adjusted to have a relatively low starting voltage (v State, for example, v ^ < -1 V. As shown in Fig. 5 (c), when a read operation is performed, a word line voltage of 0V is not applied to the word line WL. The others are in the NAND memory string The word lines WLrWL and WL4 to WL7 of the unselected memory cells all apply a word line voltage VWL = 5V to open the channels below it. The source line voltage VsL is 1.5V. The selected bit line BL finely adds bit line voltage of 0 V, unselected bit line BL runs 1 · 5V bit line voltage, bit line select transistor SGB gate voltage is 5V, source line select transistor The gate voltage of the SGS is 5V. Please refer to FIG. 6 ′. FIG. 6 is a schematic cross-sectional view of the third embodiment of the low-voltage AND-EEPR0M bidirectional FN write / erase memory of the present invention. As shown in FIG. 6 丨 People 0- ££? Ruler 0 ^ 1 6 0 0 is a two-way? Do you want to insert / erase the NAND flash memory array architecture, including a dp W A CNW, a plurality of SPWs arranged in parallel in parallel and isolated from each other by a shallow trench insulation area, are used as buried bit lines. A plurality of NAND memory string blocks (n AND ce 1 1 block) Br β2 are arranged in The same row (column) is correspondingly formed on the SPW, and an LBL is provided above the plurality of NAND memory string blocks. Each NAND memory string block Br B contains a plurality of serially connected NM0S memory cells MG ~ M7 with floating gates. Each of the memory cells MG ~ M7 has a stacked gate structure, that is, the upper word line WL0 ~ WL Section and the lower floating gate. One end of the NAND memory string block B is a source line selection transistor SGS. One end of the source line selection transistor SGS1 is electrically connected to the source of the NM0S memory cell of the NAND memory string block B, and the other end is connected to a source. The line SL is electrically connected. Source line SL is one

Page 17 550808 V. Description of the invention (13) The N-doped region is electrically connected to the CNW below, and the SPW in the same row is divided into a plurality of blocks corresponding to each NAND memory string block%, SPW and SPWb. At the other end of the NAND memory string block B A, a contact plug is electrically connected to the NAND memory string block B < N M 0 S memory cell M &. Contacting the plug and extending downwards into contact with the SPW, even if the NMOS memory cell M like the drain and the SPW form an electrical short-circuit state. Please refer to FIG. 7 (a) and FIG. 7 (b), in which FIG. 7 (a) is a partial cross-sectional schematic diagram of EEPR OM 7 0 0 according to the fourth embodiment of the present invention, and FIG. 7 (b) is FIG. 7 ( a) Equivalent circuit diagram. As shown in Figure 7 (a), EEPR0M 70 0 is a low-voltage bidirectional FN write / erase double transistor N0R (2T-BiNOR) flash memory array architecture, which includes a DPW, a CNW, and multiple rows in parallel. An array of SPWs arranged and isolated from each other by a shallow trench insulation area, a plurality of electric double-transistor (2 τ) memory cells, arranged on the same row of SPWs, and an area bit line (LBL) 'not in a plurality of electric double-transistors Remember Zhuo Yuan. Each of the dual-transistor memory cells includes a memory transistor M (only M (Γμ3) is shown in the figure) and a selective transistor SG (only I shows SG 0 to SG 0 in the figure. In this embodiment, the memory transistor The structure of M and a selection transistor SG are similar, and both have a stacked gate structure, that is, the upper word line (only WLq ~ wl 3 is shown in the figure) and the lower floating gate FG. However, the selection of the transistor SG The control gate and the floating gate FG are electrically connected, that is, the same potential. The source of the memory transistor μ is connected in series with one terminal of the selection transistor SG, and the non-pole of the memory transistor 7 is inserted by one The plug penetrates to the SPW, so that the drain of the memory transistor M and the spw form an electrical short circuit. The source of the transistor SG is selected as a N-doped region.

550808 V. Description of the invention (14) Form a deep source line (DSL) and connect with cnw and below. As shown in the figure, the same row of SPWs are separated by the DSL into several SPWs corresponding to each dual crystal memory unit. As shown in FIG. 7 (b), the transistor SGB is used to control the main bit line signal by the main wire selection transistor, and the source line signal of the transistor s is selected. The EEPR0M 70 0 of the present invention can be uniquely embedded. The element line (ie, SPW) performs a low-voltage operation and is an FN write / erase operation of random access (random bit access). Please refer to FIG. 8U) and FIG. 8 (b), wherein FIG. 8 (a) is a schematic cross-sectional view of the operation of the transistor memory unit of the present invention, and FIG. 8 (b) shows the figure 8 (a) of the dual transistor memory unit A in various modes of 800. As described above, the 800-series electric double-crystal memory unit of the present invention is formed in one piece. On the SPW, the SPW is used as an embedded bit line. The cell is inserted into the substrate through a plug and is electrically connected to the spw. By using this frame g, the 2T-Bi NOR memory of the present invention can perform low-voltage random write / erase operations. As shown in FIG. 8 (a), during the operation, a voltage of one bit line voltage Vbl is applied to N = t pole 8 0 3. Since the spw and the drain electrode 803 are electrically shorted by a plug 805, the potential of the SPW is the same as the drain electrode 803. The memory transistor 804 is connected in series with the selection transistor%. The floating gate 802 of the memory transistor M remains floating. The control gate of the transistor SG is electrically connected to the floating gate & The control gate of the transistor SG is selected to apply a gate voltage v. The original pole 8 0 6 of the crystal 30 is a deep source line (1 ^ 1) and (: Guilian ^)

550808 V. Description of the invention (15) Add a source voltage VSL. Electric Double Crystal & Mouth Electric VDPW. As shown in Figure VIII, the DPW of 4 yuan early is applied with a well state, VWI = 10V, VSI-, 8V. During the erasing operation, Vbl is under the floating part, and the floating gate 80 2 passes through FN. ^ jV 'Vdp Corpse—8V. In this case, the memory transistor M is adjusted to a unitary state and electrons are injected into the state (hi ghe r V τη), for example, when 1 5 ν is operated with a relatively high initial voltage (coding), VBL = 5ν, ν = TH < 3.5V. In the process of writing = ov, vS (f = ον. Under this condition, WL W 'Vs is in a floating state, and the VDPW mechanism is used to pull out the electrons, so that the second electrode = f pole 802 will tunnel through FN relatively Low initial voltage state energy (two e% crystals M are adjusted to have one IV. When reading the memory transistor \, ν% = work ,: VTH < 5V, Vdp 0V, VS ( p 5V. V 5 V WL = 〇v ^ V SL = 1. Please refer to Figure 9 (a) to Figure 9 (c), Figure 9 2TBiN0R-EEPROM memory erasing operation,) to Figure 9 (0 respectively Schematic diagram of reading operation. As shown in Fig. 9 (a), enter-encode (code) operation and character lines with memory transistors (only I wipe = operation is shown, the line voltage Vn = 10V The bit line BL ^ BL is floating 7L3) All characters VSL is applied to -8V, the bit line selects the transistor SGB gate = ^ source line voltage line selects the transistor SG's gate voltage to -6V. In # For -8V, the source memory cells will simultaneously pass electrons through the FN tunneling mechanism in all moving gates, so that the memory cells are adjusted to have a floating voltage (VTH) state of each memory cell. , For example, 1.5V < VTH < ^ 5vT relatively high start instruction, when writing (encoding) operation, select to Erru, Jiu ("So son of the line Wushan applied

Page 20 550808 V. Description of the invention (16)--10 0V word line voltage > voltage, other word lines WL and WL of the unselected memory cell apply word line voltage VWL = 0V, The selected bit line BL applies a 5 V bit line voltage. The unselected bit line β l is 0 V, the source line voltage V SL is in a floating state, and the bit line selects the gate of the transistor SGb. The voltage is 7V, and the gate voltage of all source line selection transistors SG is 0v. Under the aforementioned conditions, the selected memory cell will simultaneously pull electrons out of the floating gate of the memory cell through the FN tunneling-breaking mechanism, so that the memory cell is adjusted to have a relatively low starting voltage (V TH) state, for example, V TH <-1 V. As shown in FIG. 9 (c), during the reading operation, the word line WLjJi of the selected bi-electric transistor memory cell is applied with a word line voltage of 0 V, and the selected transistor SG of the bi-electric transistor memory cell is selected. Apply a 5 V gate voltage. Word lines WL 〇, WL, and WL 3 of other unselected bi-crystalline memory cells are all applied with the word line voltage V WL = 〇 V 'selected transistor SG of un-selected bi-crystalline memory cells. , SG and SG defects plus a 0V gate voltage. 5 V。 Source line voltage vsl is 1.5 V. Select the bit line BL and add 0 V to the bit line voltage, unselected bit line BL to add 1 · 5 V bit line voltage, the bit line select transistor SGB gate voltage is 5 V. Please refer to FIG. 10 (a) and FIG. 10 (b), wherein FIG. 10 (a) is a partial cross-sectional schematic diagram according to the fifth embodiment of the invention EEPR0M 1 0 0 0 'FIG. 10 (b) is FIG. 10 (a) Equivalent circuit diagram. Compared with the fourth embodiment of the present invention, in the fifth embodiment, no selection transistor s G is provided in the memory array, which is suitable for being applied to a separate data flash product. As shown in Figure 10 (a), EEPROM 1 0 0 0 is a low voltage bidirectional FN write / erase NOR type

Page 21 550808 V. Description of the invention (17) (BiNOR) flash memory array architecture, including a DPW, a CNW, a plurality of SPWs arranged in parallel and isolated from each other by a shallow trench insulation area, a plurality of memory cells (Figure Only M0 ~ M 7) are shown, arranged on the same row of SPW, and a regional bit line (LBL) is set in the memory cells M0 ~ M earthwork. Each memory cell M 0 ~ M 7 has a stacked gate structure, that is, the upper word line (WL 0 ~ WL 0 and the lower floating gate f G. Each memory cell · M g ~ M A source is extremely N + Deeply doped regions constitute a deep source line (deeps urce 1 ine, DSL), which is connected to the CNW below. Each memory cell drain is penetrated by a plug to the SPW, so that the pole and s P w are formed. Electrical short circuit. As shown in the figure, the same row of SPWs are again divided by DSL to correspond to several SPWs of each memory cell MG ~ M ^. As shown in Fig. 10 (b), the electricity is selected by the main bit line The crystal sgb controls the main bit line signal. The EEPR0M 1000 of the present invention can perform low-voltage operation through a unique embedded bit line (ie, spw) and write FN for random access (random access). / Erase action. Please refer to Fig. 11 (a) and Fig. 11 (b), where Fig. 11 (a) B 1 NOR flash e-memory of the present invention, cross-section operation diagram of the memory unit, Fig. 10 -Rules; ·· 示 本 ， 明 图 11 (a) ⑽Flash memory memory 222: Z ^ Operating conditions. As mentioned before, the B i N0R flash memory of the present invention The memory unit is Tong Shi, # onw, ^ 4 A-A cargo is formed on a separate SPW, which is used as an embedded line. District test 7 4, is electrically connected to the SPW. Use ^ 疋The line [^ is inserted into the substrate through a plug to perform low-voltage random access. This Ft ^ sends ... 1 _ flash memory u), write / erase operation during operation. As shown in Fig. 11, the control gate 1 of the 5 body transistor 1 1 〇 〇 1 丨 〇 1

Page 22 550808 Department of the invention, description of the invention (18) Fang Baoli mouth starts with the word +, a bit is applied, the voltage V hole is applied, the N-level pole 11 0 3 of the memory transistor 11 0 3 plug is formed ΐίί? VBL. Since the SPW and the drain electrode 1103 are connected to each other through a plug-in memory, the potential of spw is the same as that of the immortal electrode 1103. The N source 1104 connected to the CNW widened 00 extension is a deep source line CDSU and a moving gate. N? Only one source voltage VsL. The memory transistor 1100 floats in the DP thief! R ^ sub-set state (f 1 o a 1 ing). . Transistor memory cell 'Erase' σ One-well voltage Vdp *. As shown in Figure 11 (b), the value of-=-10V. In this floating state,% = lov, 1 = -10V, V is injected into the thunder; under the condition, the floating interrogator 1 1 02 will pass through the FN follow-up mechanism to perforate the ancient night team to make the memory transistor. 11 0 0 is adjusted to have an initial voltage state (higher νΤΗ) with _H =, for example, 6V < νΤΗ. ίί v 入 — (Edit 0; "During operation, v- = 5V,-" ν 'VSL is floating L. In this condition, the' floating gate 1102 will pull out electrons through the tunnel 2J and make the memory The bulk transistor M is adjusted to < 2 V. When the memory transistor M is read, vk 1. 5 V 5 V Dp ^ 1 〇V °

Yimu · zi lower initial voltage state (1 ower v TH), for example, 1 v < V sr

〇V, 4V, V Please refer to Figure 12 (㈧ to Figure 12 (c), Figure 12 (a) to Figure 12 (c) for the BiNOR-EEPR0M memory erase operation, write (encoding ) Schematic diagram of operation and read operation. As shown in Figure 12 (a), when the erase operation is performed, the word lines of all memory cells (only WLg ~ WLt are shown in the figure) are applied with the sub-line voltage V WL = 1 OV, the bit lines BL and BL are in a floating state, the source line voltage VSL is ~ 8V, and the gate voltage of the bit line selection transistor SGB is -8V.

550808 V. Description of the invention (19) Under the foregoing conditions, all memory cells will have a starting voltage (VTH) state of Γ k through the ^ follow-through mechanism, for example, 6V < VTH. As shown in Fig. 11 (), when performing a write (encoding) operation, the selected character line Γ Xi Shi: w ?: word line voltage, other unselected memory cells το, L, WL and WL4 to WL apply word line voltage. Voltage Vwl = w, select the bit line BL and add 5 V bit line voltage, unselected bit line 2 is ον, source line voltage vSL For the floating state, the bit voltage of the bit line selection transistor SGB is 7V. Under the foregoing conditions, the selected memory cell will simultaneously pull electrons out of the floating gate of the memory cell through the FN tunneling mechanism, so that the memory cell is adjusted to have a relatively low starting voltage (v State, for example, 1V <% < 2V. As shown in FIG. 12 (c), when the read operation is performed, the word line WL of the selected memory cell is not applied with a word line voltage of 4V, and the other is not selected. The word line WLq ~ wl ^ WL4 ~ W of the memory cell to which the word line voltage VWL = ον is applied. The source line voltage Vsi ^ i · 5V. The selected bit line BL defect plus 0V bit line voltage, The unselected bit line BL applies a bit line voltage of 1 · 5V, and the bit line selection transistor SGB has a gate voltage of 7V. Please refer to Figure 13 and Figure 14, where Figure 13 shows a main bit line (MBL) corresponds to the layout of a regional bit line (lbl). Figure 14 shows the layout of a major bit line corresponding to two regional bit lines. First, as shown in Figure 13, the master bit The line MBL1 corresponds to an area bit line UL1, and the main bit line MBL 1 and the area bit line lbl 1 are selected by a main bit line

550808 V. Description of the invention (20) Selective crystal SGBM control \ main bit line MBL2 corresponds to a regional bit line LBL2, and a main bit line is connected between the main bit line MBL2 and the regional bit line LBL2 Select transistor SGB μ control. As shown in FIG. 14, the main bit line MBL corresponds to the regional bit line LBL1 and the regional bit line LBL2. The above description is only a preferred embodiment of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

Page 25 550808 Simple illustration of the diagram Simple description of the diagram Structure Schematic operation Operation Memory Part Surface mode Figure 1 Figure 2 Schematic Figure 2 Figure 2 Figure 3 Figure 3 Figure 4 Figure 4 Drawing bar Figures 5 and 五 Figure 6 mh body Figure 7 Section Figure 7 Figure 8 Figure 8 Figure 8 The figure below shows the cross section of the conventional NAND-type EEPR0M. A partial cross-section of EEPfOM according to the first embodiment of the present invention is shown in FIG. C) is a schematic cross-sectional view of FIG. 2 (㈧ along the tangent line AA.) A) is a partial cross-section of EEPROM according to the second embodiment of the present invention. (B) is an equivalent circuit diagram of FIG. 3 (a). ^ a) A schematic cross-sectional view of a single memory cell operation of the present invention. jb 埤 shows the present invention Figure 4 (& single memory cell in various modes (&) to Figure 5 ((:) respectively. Money 1) a £: £: 1 ^ 〇 on the memory (encoding) operation And a read operation schematic diagram. / ,,, The low voltage Bi AND-EEPR0M bidirectional FN write / erase third embodiment of the present invention is a cross-sectional schematic diagram. Spear, fa) is a second embodiment of the present invention 2TBiNOR -EEpR schematic diagram. (b) is the equivalent circuit diagram of 2TBiN0R-EEPR0M in Figure 7 (a). (a) The operation profile of the 2TBiN0R-EEPR0M memory unit of the present invention is shown in Fig. 8 (a), showing various operating conditions of the double transistor memory unit of the present invention.

Page 26 550808 Brief description of the diagrams Figure 9 (a) to Toshi γ, division operation, and appropriate; U) Wipe the memory of 2TBiN0R-EEPR0M, respectively Figure 10 is a schematic diagram of the operation and reading operation.份 段 Schematics' ,,,. The part of BiNOR-EEPROM of the fifth embodiment of the present invention; (10)) is an equivalent circuit diagram of Fig. 10 (a) BiNOR-EEPROM. Operation diagram. a) The cross section of the Bi N0R flash memory and body memory unit of the present invention. Body record = death 7 (b) shows the figure 11 (a) t BiN0R flash memory of the present invention. ^ Early = Operating conditions in each mode. Techniques No. 2 1 (a) to Figure 12 (c) are the schematic diagrams of the * ^ two write ^ (encoding) operation and read operation of the BiN0R-EEPR0M memory, respectively. ^ ϋτ: Twelve shows the layout of a major bit line (MBL) corresponding to a regional bit line (LBL). Figure 14 shows the layout of a main bit line corresponding to two regional bit lines. Schematic symbol description

10 NAND type EEPR0M 12 semiconductor substrate 14 semiconductor well 20 upper control gate 22 lower floating gate 100 EEPR0M 102 contact plug 104 contact plug 106 > and pole 108 sink 202 contact plug 300 EEPR0M

Page 27 550808 Brief description of the diagram 400 EEPROM ^ 401 Control gate 402 Floating gate 403 Drain 404 Source 405 Plug 600 BiAND-EEPROM 700 EERP0M 80 0 Dual transistor memory unit 801 Control gate 802 Floating gate 803 -Drain 804 Source 805 Plug 806 Source 1000 EEPROM 1101 Control Gate 1102 Floating Gate 1103 Drain 1104 Source 1105 Plug

Page 28

Claims (1)

550808 6. Scope of patent application 1. A low-voltage non-volatile memory array, comprising: a substrate; a first conductive memory cell sharing doped wells (ce 1 1 we 1 1) formed in the substrate; A plurality of rows of the second conductive type buried bit lines are formed in the memory cell common doping well, wherein the plurality of rows of the second conductive type · embedded bit lines are independently isolated from each other, and each of the buried type The bit line is further divided into a plurality of sub-bit line segments by a plurality of first-conductivity-type deeply-doped source wells, wherein the first-conductivity-type deeply-doped source well and the first-conductivity-type memory cell Commonly doped wells are electrically connected; a plurality of serially arranged memory blocks are formed on a single row of the embedded rows of bit lines, wherein each of the plurality of memory blocks corresponds to one of the plurality of sub-bits Line segments, and each of the plurality of memory blocks includes at least one memory transistor, the memory transistor includes a stacked gate, a source, and an electrode; and a region bit line is disposed across the region in parallel On a plurality of memory blocks arranged in series Via a contact plug connected electrically to the drain of the memory transistor and the contact plug so that the buried bit line to the drain and the underlying electrically shorted. 2. The low-voltage non-volatile memory array according to item 1 of the scope of the patent application, wherein the plurality of rows of the second conductive buried bit lines are isolated from each other by using shallow trench isolation. Page 29 550808 6. Application for patent scope 3. The low-voltage non-volatile memory array as described in item 1 of the scope of patent application, wherein the first conductivity type deeply doped source well system is used as the source of the memory transistor pole. 4. The low-voltage non-volatile memory array as described in item 1 of the scope of the patent application, wherein each of the plurality of memory blocks is separately packaged and contains a selection transistor having a source electrically connected to the memory transistor at one end Electrode, and the first-conductivity-type deeply-doped source well system serves as a source of the selection transistor. 5. The low-voltage non-volatile memory array according to item 4 of the scope of patent application, wherein the selection transistor includes a control gate and a floating gate below the control gate, and the control gate and The floating gate is electrically connected. 6. The low-voltage non-volatile memory array according to item 1 of the scope of the patent application, wherein the contact plug passes through the interface between the drain of the memory transistor and the embedded bit line to provide The buried bit line has a bit line voltage. 7. The low-voltage non-volatile memory array according to item 1 of the scope of patent application, wherein each of the plurality of memory blocks includes a plurality of memory electric crystals, which are connected in series to form a NAND memory array. 8. Low voltage non-volatile memory as described in item 7 of the scope of patent application Page 30 550808 VI. Patent Application Array, where each of the plurality of memory blocks contains n memory crystals, where n is an integer from 2 to 16. 9. The low-voltage non-volatile memory array according to item 1 of the scope of patent application, wherein the first conductivity type is N-type and the second conductivity type is P-type. 1 0. A non-volatile memory element comprising: a substrate; a first conductive memory cell sharing a doped well formed in the substrate; a plurality of rows of a second conductive type buried bit line to form In the memory cell common doping well, the plurality of rows of the second conductivity type buried bit lines are isolated from each other, and each buried bit line is further doped by a plurality of first conductivity type deeply doped sources. The polar wells are further divided into a plurality of sub-bit line sections, wherein the first conductive type deeply doped source well and the first conductive type memory cell share a doping well electrically connected; a plurality of memory blocks arranged in series , Formed on a single line of the plurality of embedded bit lines, wherein each of the plurality of memory blocks corresponds to one of the plurality of sub-bit line sections, and each of the plurality of memory blocks includes At least one memory transistor, the memory transistor including a control gate, a floating gate below the control gate, a source, and a drain; a plurality of word lines, and each of the plurality of word lines Are connected to a corresponding memory transistor Control gate; an area bit line is arranged across the plurality of memory areas arranged in parallel Page 31 550808 _Case No. 91118595_ Amendment 6. The scope of the patent application, which is connected in series with each other to form a NAND memory array. Miscellaneous • In the change of independence, the base unit cell is used to remember the line and the element shape is in place. The formula is: a well shape is mixed with an element, and a wire-type package is used to embed the element electricity. Er Yi Yi entered the record of the buried-type power generation recurrence of electricity; guide the first and the first one of the non-bottomed one or two, ·, • The number is from 1 to the compound well interlaced to the extreme block and short number Active area, which contains a memory that is connected to the bag, which is a universal electric block, a row of gates, a gate, a pole, and a line that are stacked in a single row. The number of crystals is buried, and the area of the block and the body of the body is covered and recharged. Each of the crystals is recorded in the memory of the square, and the following is set. The contact body and the element are connected to the string of crystals, and the element electrode field is recorded by the plug-in digital memory region through the plug-in method. If the element is touched and the ground is buried, it should be connected with the central well. At its repolarization, the well source body and the hybrid memory source are doped with the heterodeep doped type to generate deep electricity. The wave guide is connected to the non-electrical guide. The electric report is a miscellaneous item in the well. It is mixed with 6 1 numbers. It is surrounded by the paragraph and the cell line line. Apply for a guide as if you are counting one. · The complex road 1 Page 33 550808 6. Scope of Patent Application Each of the plurality of memory blocks corresponds to one of the plurality of sub-bit line sections. 〇 Its pole, the source body's memorandum, the day of the positive electricity, and the memory of the non-descriptiveness, which is not the description. ^ Well 17 pole, the source range, the miscellaneous range, and the profit-specific deep type, please call for advice. Section 9 1 The 2 0. The non-volatile memory according to item 16 of the scope of the patent application, wherein the plurality of rows of the second conductive buried bit lines are isolated from each other by using shallow trench isolation. 2 1. The non-volatile memory according to item 16 of the scope of the patent application, wherein each of the plurality of memory blocks further includes a selection transistor having a terminal electrically connected to a source of the memory transistor. Page 34