TW550772B - Packaging substrate and the test method thereof - Google Patents

Abstract

A packaging substrate has a packaging area and a connecting area surrounding the packaging area. The connecting area has a plurality of electrodes thereon and a circuit conducting each of the electrodes for testing failures of the packaging substrate.

Description

550772 V. Description of the invention 发明 The present invention relates to a kind of chip packaging substrate, especially to one? Ϊ́ ί: L circuit chip packaging substrate, this test circuit can be used to detect whether the chip packaging substrate is delaminated, causing the substrate ⑺ 路 ⑺ 口 ^), quality control. ^ With the trend of thin and light electronic products, the manufacturing of printed circuits is also moving toward ultra-thin thickness, ultra-fine line width and ultra-narrow line spacing of conductive circuits. At present, the plastic ball grid array (PBGA) package is the most commonly used in the industry. PBGA sealing plate is mainly used on chip sets and graphics chips. Tin balls are arranged on the bottom of the PBGA package substrate in an array of ^. As a chip and printed circuit board pin, it replaces the traditional metal lead frame. The advantage is that under the same size, the number of pins can be increased and the pitch is increased. Therefore, the PBGA package substrate is a round package (Chjp Scale Package / Flip). Chip, FCBga) ^ The key packaging technology for high I / 〇 requirements for portable products. FIG. 1A is a top view showing a conventional PBGA package substrate assembly. The one shown in the figure is the sealing board when the printed circuit board factory ships to the chip packaging factory. It is arranged in a 1x4 matrix manner and can package four chips. However, other matrix arrangements may also be used according to the needs of the international application.丨 b Top view of a unit substrate of a PBGA package substrate assembly in Figure 1A: As shown in Figure '1B, the PBGA package substrate 10 described above includes a quadrangular sealing area 12 and is arranged in an array. Metal welding points 丨 2 i; Four, the junction area 11 surrounds the above-mentioned packaging area 12, and a gap remains between the inner edge of the connection area U and the outer edge of the package 1. The above connection area is only used for fixing ^: Area 1 2 and provides the equipment for clamping when the chip is packaged.

550772

Generally, PBG A package substrates have multiple layers ^ ,, n. ^ ^ ^ Xi Zeng ¥ green layer (more than 8 layers), its thickness is only about 0.5mm, and the thickness of each wire layer * a. After the chip is packaged, a Will be cut off, forming waste. See the eight lines, the line spacing is less than 0 mm. The conventional printed circuit board manufacturing process includes _ ^ ^ m ^ ^ m ^ ds • Co-brew, wet, strong acid, strong alkali, etc. processing ^ sequence 'Because of the dagger, PBGA Feng Meng Qibo 6 η ^ yv ΛΑ * The mounting substrate is very susceptible to deformation and layering due to thermal expansion and contraction, or damage to conductive lines due to the sensitive folding of Nie Renfeng Jin & Road Belt Green ^ 疋 U Feng He 溥 copper box '^ Cause Product defects. In addition, the PBGA package substrate and the PBGA package substrate must be combined with the test circuit of the chip package. The test results can only know that the package is complete and that it is caused by a defect in the PBGA package substrate. For the situation on a good PBGA package substrate, please refer to FIG. 1A again. Because the area 12 and the connection area 11 are the same at the same time, they have the same number of multiple metal layers in the package area 12 as the multiple wire layers; However, the connection area Π is used to form a wire layer in the connection area 11. It still has the completion of die packaging and is considered as a waste. In view of this, the biggest difference between the general printed circuit board of the present invention is after installation, The electrical test can be performed in advance in the package and mounting area, and whether the chip is normal. It cannot be separated, the grain is bad, or the probability of the package is the sum of the three. Therefore, it often occurs Normal dies are packaged without increasing wafer manufacturing costs. The conventional PBGA packaging board 10 is produced by the package-printed electrical circuit board process. The difference between the metal layer and the insulation layer is only the production of a predetermined circuit (not shown). The shape is used to provide equipment positioning, The metal layer is not used to make a plurality of pure metal layers of the circuit, and is cut away in the packaging area i 2. Is to provide a

550772 V. Description of the invention (3) The wafer sealing substrate of the circuit is used in the connection area 11 of the conventional technology. In the above connection area, the medium will be used as a waste removal package substrate product inspection to make this crystal ^ The Na test circuit is used for product inspection before the wafer is mounted, so that the substrate can be mounted on the die to increase the yield of the product and reduce the production; = to provide the same function for the production of defective wafer packaging substrate boards. It can also be applied to printed circuits. In order to achieve the above-mentioned purpose, the package substrate of the present chip includes-a seal region and a crystal of a test circuit. It has a plurality of wire layers and a connection area spaced from the connection area of the wire f, and the connection area. A plurality of electrodes provided on the wafer 'J = JJ insulation layer and -test circuit' are provided, wherein the test circuit is placed in two places: the electrodes are electrically connected on the surface 'and at least through the insulation layer between two adjacent conductors c. . The wiring layer of M and sandwiched therebetween. In the preferred embodiment, the wiring layer and the insulating layer. In the-preferred embodiment. In Nujia's bismuth example, the connection area has a plurality of through holes (V i as), and the above through holes pass through the chip package substrate to make the test circuit electrical layer. & Coupling Guidance ' The electrodes and vias described above are disposed in the connection region at intervals. In a preferred embodiment, the connection region has a plurality of blind vias. The blind vias penetrate at least two wire layers and an insulating layer sandwiched therebetween to electrically connect the test circuit to the at least two wire layers. The packaging area has a connection area extending from the connection area and is arranged outside the packaging area.

0702-7939TW; 91P14; Jimy.ptd Page 6 550772 V. Description of the invention (4) In addition, the above-mentioned one is better and one is better (Polymer Resin The present invention also mentions, including a plurality of sealed reprints: wire The layer and the connection area are provided with a bipolar electrode and a test for electrically connecting the electrodes and an insulating layer. In a preferred embodiment of the solid wire layer and the insulating layer electrode and the blind hole system, the test embodiment is described above). A device is provided with a test area and ~ and each interval is set in a derivative set on the crystal circuit, wherein the test is set in the connection area through at least two intervals. The circuit is made of conductive material. The insulation layer is a connection area connected by the packaging area of the chip packaging substrate assembly of the polymer polymer circuit. It has a plurality of insulation layers between the wire layers, and the electrical circuits on the surface of the connection area of the chip package are arranged in the connection area. In a preferred embodiment, the inner conductive layer and the surrounding sandwiched between the package areas have a connection area extending from the connection area. In a preferred embodiment, the 'connection area is surrounded and arranged outside each package area in a preferred embodiment. The above-mentioned through-holes penetrate the wire layer. In addition, the above-mentioned insulation layer of a Blind Vias j is used to measure the above. In a preferred embodiment, the above-mentioned embodiment of connecting the chip package substrate electrode with the through-hole system connects the above-mentioned blind hole system. In the embodiment of the test circuit for electrically connecting the electrodes and the blind holes, the test area has a plurality of through holes (Vi as), and the test circuit is electrically connected to each conductive interval in the connection area. The region has a plurality of blind holes penetrating at least two wire layers and missing at least two wire layers therebetween. The interval is set in the link area. The circuit is made of conductive material.

0702-7939TW; 91P14; Jimy.ptd page 7 550772 5. Description of the invention (5) In a preferred embodiment, it is composed of (Poly mer Resin). ^ ,,, and the & layer are implemented by a high molecular polymer. Please refer to FIG. 2A and FIG. 2A. The chip package substrate and the package substrate of this embodiment are stacked in a top view. Eight by a plurality of wire layers and insulating areas 2 ... array of square 2 package area-packaging a predetermined circuit, can be used for chips ", 41, which has--a square connection area 23, connection area 23 :: = area 24 There is a gap between the perimeters and the outer edge of the package area 24 ± ^ from „♦”. 9a J 1 is connected to the package area 24 at the previous corner. As shown in FIG. 2A, the wafer of the present invention The sealed insulating surface layer has -first electrodes 21 and-^: electrodes 22: f 23 23 and a test circuit 24. The test circuit 234 is in the ring connection area 23 and electrically connects the first and second electrodes. 2i, in the path ± of the test circuit 234, a plurality of through holes 231 (Vias) and blind holes 232 (BHnd vj) are formed in the same way as in the seal to make each of the connection areas 23 of the chip package substrate 20 The wire layers can be connected respectively to detect whether the wire layers at different locations are delaminated or delaminated. The state of misalignment. The figure is a cross-sectional view of the aa cross section in FIG. 2A. In order to simplify the illustration, the PBGA package substrate 20 of the present embodiment is composed of only four metal layers. An insulation layer 26 is isolated and sandwiched between a first insulation surface layer 261 and a second insulation surface table 262. Therefore, the packaging substrate 20 of this embodiment can form a four-layer wire layer, and for convenience of explanation From 0702-7939TW: 91P14; Jimy.ptd Page 8 550772

The bottom to the bottom are sequentially defined as the first to fourth wire layers 25 to 254, but the actual PBGA package substrate may have more wire layers depending on the situation. As shown in Figures 2A and 2B, the through-holes 2 3 1 pass through each of the lead layers 25, 254 and the insulation layers 26 of the entire ρ β a package substrate 20, and are filled with a metal or conductive material to make the first lead The layer 2 5 1 can be electrically connected to the fourth wire layer 254 ′, that is, the wire layer connecting the uppermost layer and the lower layer; the blind hole M? Is a hole formed by each wire layer to form an interconnection, wherein the blind hole 23 2 penetrates at least any two wires. The layers 2 5 1 to 2 5 4 and the insulating layer 2 6 sandwiched therebetween enable the test circuit 2 3 4 to be electrically connected to the lead layers 2 5 1 to 2 5 4. Therefore, the test circuit 234 ′ provided in the connection in FIG. 2B is extended from the first electrode 21. In the first wiring layer 2 5 1, it first extends to the fourth wiring layer 2 through the via 2 3 1. 54. Then, it extends to the third wiring layer 253, the first wiring layer 251, and the second wiring layer 252 through the blind hole 232. After the test circuit 234 surrounds the entire packaging area 24, the electrical connection is located in the fourth wiring layer 254. Two electrodes 22. The first electrode 21 and the second electrode 22 may be more than one, and each may be plural. Therefore, it is possible to measure whether any two electrodes on the PBGA package substrate 20 are delaminated or disconnected. FIG. 3 is a top view of a pBGA package substrate assembly according to another embodiment of the present invention. As shown in FIG. 3, the package substrate assembly 30 has four packaging areas 31 arranged in an array. A plurality of metal soldering points 3 1 1 are set in a manner, and each package area 3 1 has a predetermined circuit inside, which can be used for packaging of a chip. At the periphery of the packaging area 31, there is a connection area 32 for fixing each packaging area 31 and for holding the packaging equipment. There is a looped test circuit 34 in the connection area μ, and a plurality of electrodes are provided on the upper insulating surface layer of the connection area 32

550772 V. Description of the invention (7) 34 The test electric circuit is electrically connected to each electrode 路, ~ Road 3 4 also uses the conventional printed circuit board manufacturing technology in each of the two test electric through holes 342 and blind holes 343 'to Each circuit i is electrically connected electrically; an in-phase formation: pole 3) 1 may also be electrically connected according to the first embodiment by setting the electrodes to the above-mentioned transmission test circuit 34. As you can see from the above description, the embodiment of the present invention is sufficiently profitable, and the test electricity surrounding the packaging area is arranged in the junction area ... The packaging substrate assembly 3 can be firstly processed by the substrate factory. Test; if there is an open circuit at any time, you can know the good quality of the pBGA packaging base near the two electrodes, or in the process of manufacturing a semi-finished product, or packaging ^ ‘,,, = package substrate 2. Elimination, can be a big sign: yield, effectively reduce production costs. The metal layer in the wire layer mentioned in the present invention is composed of copper, gold, and other conductive materials; and each of the insulating layers is mainly composed of a polymer polymer (Polymer Resin). For example, epoxy resin, Polyester, Cyanate Ester, or Polyethylene. FIG. 4 is a flowchart of a test method for a chip package substrate according to the present invention. As shown in Figure 4, a f-substrate is first made by the traditional pBGA package substrate manufacturing process. The PBGA package substrate has a plurality of packaging areas and a connection area connected to each packaging area as described above. Each electrode and a test circuit electrically connected to each electrode (S41). Before using the base board circuit to cut the time or chip package, use a resistance meter to detect any electric power. Page 10 〇702-7939TlV; 91P14; Jimy.ptd 550772

Whether the electrode is selected, it is necessary to check whether the substrate is between the electrodes or other samples. Although the size of the sensor and the range can be limited as the viewing path (S42), the pre-screening can be performed during the PBGA manufacturing process. Defective products can be removed first to avoid production waste. In package 1, if there is a path between any two of these electrodes, then this ρβ (^ can be directly packaged directly if the package is normal (S 4 3); If any of the two groups is open, it is judged that the PBGA package substrate has X-layer defects (S44), and the PBGA package substrate needs to be eliminated (S45): die inspection is performed with these detected PBGA package substrates. The overall yield of the PBGA package chip is improved. The present invention has been disclosed in the preferred embodiment as above, but it is not intended to be used by anyone skilled in the art. It can be modified and retouched without departing from the spirit of the present invention. Therefore, the scope of the patent application attached to the protection of the present invention shall prevail.

550772 Brief description of the drawings In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Figure 1A Top view of the conventional PBGA package substrate assembly. FIG. 1B shows a top view of a unit substrate of the PBGA package substrate assembly in FIG. 1A. FIG. 2A is a top view of a pBGA package substrate according to the first embodiment of the present invention. Fig. 2B is a cross-sectional view taken along the a-a section in Fig. 2A. Fig. 3 is a top view of a pBGA package substrate assembly according to a second embodiment of the present invention. Figure 4 is a flow symbol description of the test method of the chip package substrate of the present invention: 10 ~ PBGA package substrate; 11 ~ connection area; 12 ~ package area; 1 2 1 ~ metal solder joint; 1 3 ~ connection part; 20 ~ PBGA package substrate; 21 ~ first electrode; 2 2 ~ 篆 two electrodes; 2 3 ~ connection area; 231 ~ through hole; 〇232 ~ blind hole; 234 ~ test circuit;

Page 12 550772 Brief description of the drawings 2 4 ~ Packaging area; 2 4 1 ~ Metal solder joints; 251 ~ First wire layer; 252 ~ Second wire layer; 2 5 3 ~ Third wire layer; 2 5 4 ~ 第Four wire layers; 2 6 ~ insulation layer; 2 6 1 ~ first insulation surface layer; 262 ~ second edge surface layer; 30 ~ PBGA package substrate assembly; 3 package area; 3 11 ~ metal solder joint; 3 2 ~ connection Area; 3 4 ~ test circuit; 341 ~ metal electrode; 342 ~ through hole; 343 ~ blind hole.

0702-7939TW; 91P14; Jimy.ptd page 13

Claims (1)

Sixth, the scope of patent application • A chip package substrate, including: a package area; layers, complex layers; ϊ layer and ^ the connection area has a plurality of conductors-the insulation surface layer has a plurality of two insulation surface layers Between the conductor layers: an insulation layer such as the middle layer separates the first insulation surface layer and the second insulation; and a test circuit is sandwiched between the conductor layers, and the test circuit is arranged at least in Xi Rong ^ 2 '. The insulating layer is electrically connected to the first electrodes with an insulating layer. Ri and U 2 · Connect these second electrodes as in the first patent application. Leyi electrode, and the test circuit is also electrical. 3 · As in the first patent application scope, the connection area is surrounded by the outside of the package area. Xiao I substrate, of which 4. As in the first patent application, the package area has an edge layer extending from the connection area. The 4 wire layers and the insulation 5 from the first · If the connection area of the patent application item 1 _ has a plurality of through holes, \ package substrate, where the insulation layer, the first insulation surface == Be through these wire layers, and electrically connect these wire layers. θ and § 2nd Dior Insulation 'make the test electric 6. As described in item i of the patent application scope, the connection area has a plurality of blind substrates. at least 0702-793OT; 9lP14; Jimy.ptd Page 14 Two conductor layers and the connection between them. 7, Θ, 17 HAI Special Insulation # ， 彳 由 # ハ 4 At least two conductor layers. The water layer electrically connects the test circuit of the clam. 7 · As in the patent application section, the insulation layer is a self-contained molecular package, as described in the chip package substrate, in which 8. It is composed of the patent application. Each of the packaging areas has the chip packaging substrate described in item-^, wherein the fixed circuits are made at the same time. Circuit, the test circuit of the connection area and the existing chip package substrate assembly, including: a plurality of packaging areas; a paper u-character layer: Ϊίΐί 'connecting the packages', the connection area has a plurality of leads. Layer, a first-insulating surface layer and a second-insulating surface layer ^, and the taste surface layer has a plurality of first electrodes, among which the insulation layer ^ is placed between the 4 wire layers of the knot pipe, and the insulating layers and the wires Between the surface layer of the first and second margins and the second insulating surface layer; the under-tested circuit is provided on the wire layers and the insulation layers, and the test circuit passes at least two adjacent wire layers And sandwiched between the 涿 temple insulation layer and electrically connected to the 〆 electrodes. I 0 · The chip package substrate assembly according to item 9 of the scope of the patent application, wherein the second insulating layer has a plurality of first electrodes; and the test circuit is electrically connected to the second electrodes. II. The chip package substrate assembly according to item 9 of the scope of the patent application, wherein the connection area is surrounded and arranged at the periphery of the package area. 1 2 · The wafer package substrate assembly as described in item 9 of the scope of the patent application, wherein the side package area has the wire layers extending from the connection area. Surface 0702-7939TW; 91P14; Jimy.ptd page 15 550772 6. Scope of patent application and other insulation layers. Among them, 1 and 3 are the chip package substrate assembly as described in the "Item 9 of the Patent Scope," and a plurality of through holes are formed. These through holes pass through the test circuits of the wires. The chip package substrate assembly described in the scope item 9 has at least two leads having a plurality of blind holes, which are connected through the insulation to the i 5 clips, the insulation [make the test circuit electrical y First-class genus. The Douzhong cough must be the wafer mounting substrate assembly described in item 9 of the special range of Shen / Yueyue, where the insulating layer is composed of a polymer. According to the chip package substrate assembly described in item 9 of the / Λ patent scope, each of the predetermined lightning circuits has a predetermined circuit, and the test circuit in the connection area and the existing circuit are made at the same time. 2 · A chip package The test method of the substrate includes:-a zone and two 5 to 5 i 2 mounted substrates, the chip package substrate has a package electrode and ^ connecting material electrode-㈣ circuit; ^, there are * several electricity for breaking ϊ circuit If any two of these electrodes have defects, the Japanese-Japanese-Japanese package substrate has defects. ®; 7 ^ ^ ^^ ^ ^ ^ ^ The eight mega-connected, ,, and 0 areas are connected to the packaging area, and the distance is shown as follows: r #, ::: insulation layer,-#-insulation surface layer and a "The first-insulation, ~ the surface has a plurality of first-electrodes, where these insulation 0702-7939TW; 91P14; Jimy.ptd p. 16 550772 The layer interval is set between the wire layers, and a μ a layer sandwiches the first insulating surface layer and the second insulating surface layer. Γ Female 419 · Gan Ruoshi Vf test of the chip package substrate described in 17 items of patent scope / ^ 忒 / The test circuit is provided on the wire layers and the insulation f,, and !! The test circuit passes at least two adjacent wire layers and the 4 insulation layers sandwiched between them, and Sexually connect the first electrodes. 4 Ancient 22: If Gan Shenshi requested the method of measuring the chip package substrate described in Item 17 of the patent scope, the second insulating layer has a plurality of first test circuits and is also electrically connected to the second electrodes. . t pole, and test 2 1 · The wafer method according to item 17 of the scope of patent application ', wherein each of the packaging areas has a predetermined circuit and the predetermined circuit is made at the same time. #Test of mounting substrate ’Test of the connection area