TW550763B - Structure of discrete NROM cell - Google Patents

Abstract

A discrete NROM cell, at least comprising: a substrate; a first ONO stacking gate and a second ONO stacking gate over the substrate, wherein the ONO stacking gate is a structure having a nitride layer between two oxide layers; an oxide layer formed over the substrate covering the first and second ONO stacking gates; a polysilicon layer formed over the oxide layer; and the source/drain implanted in the substrate and next to the ONO stacking gates. The structure of discrete NROM cell of the invention can solve the problem of the electrons being trapped in the nitride layer of NROM cell, and also control the source/drain implant and ONO structure at precisely symmetrical positions.

Description

550763 V. Description of the Invention (1) [Field of the Invention] The present invention relates to a structure of nitride read-only memory (NR0M) cells, and in particular to a self-aligning A self-aligned process creates discontinuous NROM memory cells. [Background of the Invention] Memory devices that can store non-vol at i 1 e information, such as read-only memory (ROM), programmable read-only delta memory (PR0M), and erasable In addition to erasabie programmable ROM (EPROM), and other advanced memory devices' have been widely used in the global industry. Compared with a general memory device, a South-level memory device usually involves more complicated manufacturing processes and testing procedures. The high-level memory device includes electricaUy erasable programmable read-only memory (EEpROM), flash (flaSh) EEPROM, and nitride read-only memory (NROM). These high-level memory devices can accomplish tasks that are not possible with ROM in general. For example, the circuits using EERPOM devices can use the erase and write functions built into EEPROM devices. The main feature of NR0M is its cell, and the dual-bit memory cell has multiple voltage levels), every 2 critical bits, and other critical voltage levels. Among them, the system of the NR0M memory cell is a dual bit memory. It weighs 6 ¾ boundary voltage levels (threshold boundary voltage levels will be stored together differently. One bit will be stored in one of the memory cells. The manufacturing method and general structure are found in many

550763 V. Description of invention (2) In literature and reference materials. Please refer to Figure 1, which shows a cross-sectional view of a general NROM memory cell. First, it is long: a substrate 10 is provided, and a source 12 and a drain 14 are implanted on the substrate 10. Next, a 0N0 structure is formed on the substrate 10, which includes a nitride layer 17 sandwiched between a top oxide layer 16 and a bottom oxide layer 18. Then, a plurality of buried diffusion (BD) oxides 20 'are formed between the 〇NO structures to form channels 22 and isolate the adjacent 〇NO structures. In the structure of NROM memory cells, each memory cell has double bits, as shown in Figure 1. The larger area (the area circled by the larger dashed line in the figure) represents a single NROM § Ji Yi cell 30, and the two smaller areas (the area circled by the smaller dashed line in the figure) represent the first place Yuan 32 and second bit 34. In the NROM memory cell 30, the nitride layer 17 provides a charge retention mechanism that can be written into the memory cell. Under normal circumstances, 'electrons are introduced into the nitride layer 17 during the writing of the memory cell'. However, the electrons introduced into the nitride layer 17 are trapped in the nitride and cannot move freely, and the holes ([1〇 165) Nitride layer 17 is introduced during memory cell erasure to neutralize or combine electrons. In addition, according to the hot electron injection phenomenon (hot electron injec, h〇n Phenommen), some hot electrons will penetrate the lower oxide layer ^^ concentrated on the nitride layer 17 ', especially the thickness of the current oxide layer 18 Very 'exclusive%' due to the local charge generated by the hot electrons, the threshold voltage of part 22 of channel 22 will be higher than that of other channels 22

550763 V. Critical voltage of part (3) of the invention description. When the memory cell performs a write operation, a local charge will appear and the rising threshold voltage will prevent the memory cell from entering the on state. In the general state, that is, when the local charge does not appear, the read voltage can overcome the critical voltage of the channel 22, so that the channel 22 can be turned on. In addition, traditional NROM memory cells made by several steps of photolithography have some drawbacks. For example, implants and bits are not easily formed at the correct position and are displaced, resulting in a greatly reduced efficiency of NROM. [Objective and Summary of the Invention] In view of this, the object of the present invention is to provide a discontinuous nitride read-only memory memory cell structure (discrete nr0m ceii), so that the source / drain (source / drain) ) And the position of the 0-layer can be easily and accurately controlled. According to the purpose of the present invention, a discontinuous NROM memory cell is proposed, which includes: a substrate; a first 0N0 stacked gate (staking and a 0th 0N0 stacked gate formed on the substrate, The 〇N〇 stack gate is composed of a nitride layer (nitride layer) sandwiched between two oxide layers ㈧ 1 y \; an oxide layer is formed on the substrate to cover the first 0 / N0 A stack of gates, a gate, and a second 0N0 gate; a polycrystalline silicon layer formed on the oxygen substrate and a source / drain formed on the substrate and nearly the first 0N 〇 Stacked question electrode and second qn 〇 Stacked gate. In order to make the above-mentioned object, features, and advantages of the invention more obvious and easy to repeat, the following describes a preferred embodiment, and it will be described in detail with the accompanying drawings.

550763 5. Description of the invention (4) is as follows. [Preferred Embodiment] The present invention is a discrete read-only memory (NR0M) memory cell manufactured by a self-aligned process. The following are two kinds of processes to make the discontinuous NROM memory cell of the present invention. In addition, in order to understand the present invention more clearly, elements that are not directly related to the present invention will not be repeated here. Therefore, the embodiments and drawings described are only for illustration, but not for limiting the practical application scope of the present invention. 1 Example 2: Method 1 for manufacturing NRM memory cells Figures 2A to 2F show a method for manufacturing a discontinuous NRM memory cell using a self-aligned process according to Example 1 of the present invention. First, a substrate 210 is provided in FIG. 2A, and an ON0 layer is formed on the substrate 21O. The 'ON0 layer includes a bottom oxide layer 218, a nitride layer 217, and a top oxide layer 216. A lower oxide layer 218 is formed on the substrate 210, also known as a tunneling oxide layer, and a nitride layer 217 is formed on the lower oxide layer 2 1 8 'and the upper oxide layer 2 1 6 is formed on the nitride layer 217. Next, a patterned photoresist layer (patterned PR) 219 is formed on the upper oxide layer 216. Among them, the thickness of the lower oxide layer 218 is about 50A to 150 A.

TW0738F (Wang Hong) .ptd page 8 550763 V. Description of the invention (5) Room 'and preferably about 70a. The thickness of the nitride layer 2 17 is approximately in the range of 20A to i50A. Since the upper oxide layer 216 will be removed in a subsequent process', the thickness of the upper oxide layer 2 1 6 is not particularly limited. In addition, the thickness of each layer of the '0N0 layer is independent and not related to each other, and the thickness range can be changed according to its actual application. Next, the upper oxide layer 2 1 6 is etched according to the patterned photoresist layer 2 1 9. The upper oxide layer 2 丨 6 covered by the patterned photoresist layer 2 丨 9 is retained, and other uncovered upper oxide layers 2 1 6 are removed. After that, the patterned photoresist layer 219 is removed, as shown in FIG. 2B. Then, as shown in FIG. 2C, a thin film is uniformly deposited on the upper oxide layer 216 and a portion of the nitride layer 217. Then, an anisotropy etching process is used to form a thin film on the etched portion to form a spacer 221 on both sides of the discontinuous oxide layer 2 1 6. Among them, the thin film may be anything other than nitride, such as an oxide or polycrystalline stone (P 0 1 y s i 1 i c 〇 n). It is worth noting that the bottom width of the partition wall 221 is a predetermined value d. Then, the source / drain 222 is implanted in a self-aligned process, and the implanted dopant is, for example, an N-type dopant phosphorus or arsenic ion, or a p-type dopant boron (bOron, b) or fluorine. Boron ion (BF2 +). Then, the upper oxide layer 2 16 and the nitride layer 2 17 are sequentially removed, as shown in FIG. 2D. After the money is carved, the nitride layer 2 1 7 that is not covered by the spacer 2 2 1 is removed, and the other nitride layer 2 1 7 that is covered by the spacer 2 2 1 is left on the lower oxide layer 2 1 8 on. Next, the spacer 2 2 1 is removed. Then, the lower oxide layer 2 1 8 is removed according to the remaining nitride layer 2 1 7, as shown in FIG. 2E.

TW0738F (Wang Hong). Ptd Page 9 550763 V. Description of the invention (6) ------ So far, several layers of nitride 2 1 7 and lower oxide 2 2 have been formed on the substrate 2 1 0. 18, and the stacked gate (stacki called "). Then, as shown in Figure 2F, an oxide layer 226 is formed on the substrate 21 to fill the gap between adjacent stacked gates and cover nitrogen. The compound layer 217. Next, a polysilicon layer (228) is covered over the oxide layer 226 as a word line (Wordine). The polysilicon layer (228) may be amorphous silicon (amorphus). Si HcOn) or doped polycrystalline silicon, wherein the polycrystalline silicon layer can be doped with phosphorus or arsenic ions. In addition, in some special processes, a layer of tungsten silicide (tungsten si 1 pesticide 'ffSix) can be deposited on the polycrystalline silicon layer 228 (Not shown in Figure 2F) to complete the process of the discontinuous NROM memory cell. '' The formation of the NROM memory cell in Embodiment 1 Figure 2G shows the discontinuous NROM memory of the first embodiment of the present invention A cross-sectional view of the cell. The source / drain 222 is implanted at the substrate 210. The narrow stacked gate formed on the substrate 210 The structure is a 0N0 structure, including: an upper oxide layer 216, a lower oxide layer 218, and a nitride layer 217 sandwiched therebetween. The oxide layer 226 separates the ON0 structure and forms a discontinuous NROM memory cell structure. Above the oxide layer 226, a polycrystalline silicon layer 228 is further covered. In Figure 2G, the larger area (the large circle in the figure) represents an NRM memory cell 230, and the width of the two smaller areas is d (the small circle in the figure) Range) means the first bit 2 3 2 and the second bit 2 3 3. In addition, the source / ;: and the pole 2 2 2 are implanted in a self-aligned manner, and the subsequent steps are also self-aligned. Therefore, the relevant positions of the source / drain 222 and ON0 layers can be easily and accurately controlled.

TW0738F (Wang Hong). Ptd Page 10 550763 V. Explanation of the invention (7) ± JL1H Second method for making NR0M memory ^ The second section 3 A ~ 3 F diagram shows the second embodiment of the present invention using a self-aligned process Peng Zao manufacturing method of discontinuous NROM memory cell. Among them, the manufacturing method of the second embodiment is substantially the same as that of the first embodiment, and only a few steps are modified to improve it. 〆 Figure 3A is the same as Figure 2A. In FIG. 3A, a 100 layer is formed on the substrate 310. The 0N0 layer includes an upper oxide layer 316, a nitride layer 3.17, and a lower oxide layer (tunneling oxide layer) 318. Next, lithography is used to form a plutonium, and a patterned photoresist layer (patterned pR) 3119 is formed on the upper oxide layer 316. Similarly, the thickness of each layer of the 0-rib layer is independent and not interconnected, and the thickness range can be changed according to its actual application. The upper oxide layer 316 is etched according to the patterned photoresist layer 319. Next, the source / drain 322 is implanted in a self-aligned process. The source / non-polar milk is, for example, (boron, B) or boron fluoride ion (BII? 2+). Then, a part of the patterned photoresist layer 319 is removed to expose the oxide layer 316 having a predetermined degree d, as shown in FIG. 3B. Then, according to the stripped patterned photoresist layer 3-9, the upper layer 316 is etched / the patterned photoresist layer 319 is removed, as shown in FIG. 3C. ^ ^ ^ ^ ^ 316 ^ 1¾, q? 1. Gan is formed on both sides of the oxide layer 3 1 6 on the non-connected and sintered layer. The thin film can be any substance other than nitride. At this time, the bottom width of the partition wall 321 is controlled at a predetermined value d.

550763 V. Description of the invention (8) Then, the discontinuous upper oxide layer 3 1 6 is removed, and the spacer 3 2 1 is exposed on the nitride layer 3 1 7. Then, the nitride layer 317 is etched according to the spacer 3 2 1 so that the nitride layer 317 not covered by the spacer 321 is removed, and the other nitride layers 3 1 7 covered by the spacer 3 2 1 remain below. On the oxide layer 318. Next, the spacer 321 is removed, as shown in FIG. 3E. The lower oxide layer 3 1 8 is removed according to the remaining nitride layer 3 1 7 to form a plurality of stacked gates. Then, an oxide layer 326 is formed on the substrate 310 to cover the ONO stacked gate. Next, a polycrystalline silicon layer 328 is covered over the oxide layer 326, as shown in FIG. 3F. Structure of NRM Memory Cell in Embodiment 2 FIG. 3G is a cross-sectional view of a discontinuous NRM memory cell in the second embodiment of the present invention. The source / drain 322 is implanted at the substrate 310. On the substrate 310, there are a plurality of narrow stacked gates. The stacked gates have a structure of 0N0, including an upper oxide layer 3 1 6 and a lower oxide layer 3 1 8 with a nitride interposed therebetween. Layer 31 7. The oxide layer 326 separates the 0N0 structure and forms a discontinuous NROM memory cell structure. A polycrystalline silicon layer 328 is further covered over the oxide layer 326. In Figure 3G, the larger area (the range of the large circle in the figure) represents an NR0M memory cell 330, and the width of the two smaller areas is d (the range of the small circle in the figure) represents the first bit 332 and the first Two bits 3 3 3. In addition, the source / drain 3 2 2 is implanted in a self-aligned manner, and subsequent steps are also performed in a self-aligned manner. Therefore, the relative positions of the source /> and the electrode 3 2 2 and 0 N 0 layers can be easily and accurately controlled.

TW0738F (Wang Hong) .ptd

Page 12 550763 V. Description of the invention (9) In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art will not depart from the spirit of the present invention. Within the scope and scope, various modifications and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the appended patent application.

TW0738F (wanghong) .ptd Page 13 550763 Brief description of the drawings [Simplified description of the drawings] Figure 1 shows the cross-section of a general NROM memory cell; Figures 2 A ~ 2 F show the implementation of the present invention Example 1 Manufacturing method for manufacturing discontinuous NROM memory cells by self-alignment process FIG. 2G illustrates a sectional view of a discontinuous NROM memory cell according to the first embodiment of the present invention. FIGS. 3A to 3F illustrate embodiments of the present invention. Second, a method for manufacturing a discontinuous NROM memory cell using a self-aligned process; and FIG. 3G illustrates a cross-sectional view of a discontinuous NROM memory cell according to the second embodiment of the present invention. [Schematic symbol description] 10, 21 0, 3 1 0:: substrate 12: = source 14 = drain 16, 216 > 316 upper oxide layer 17, 217 '317 nitride layer 18, 218 > 318 lower oxide layer 20: buried diffusion region Oxide 22 = channel 30, 230 > 330 NROM memory cell 32, 232 > 332 first bit 34, 233 > 333 second bit 219, 3 1 9: patterned photoresist layer

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Claims (1)

550763 VI. Scope of patent application1. A discreet nitride read-only memory (NR0M) memory cell (ceu) structure, including at least: a substrate; a plurality of 0N0 stacking gates Electrode is formed on the substrate, wherein the gate stack gate is composed of a nitride layer sandwiched between two oxide layers; an oxide layer is formed on the substrate To cover the 0N0 stacked gate; a polycrystalline silicon layer formed on the oxide layer; and a plurality of source / drain formed in the substrate and close to the 0N0 stacked gates. 2. The structure of the discontinuous NR0M memory cell described in item 1 of the scope of the patent application, where the far 0 Ν 0 stacked gate is composed of an upper oxide layer and a nitride layer ( consisting of a nitride layer) and a bottom oxide layer. 3. The structure of the discontinuous NRM memory cell described in item 2 of the Chinese Patent Application, wherein the thickness of the nitride layer is between 20A and 150. 4. The non-connection as described in item 2 of the scope of the patent application. The structure of the continuous NROM memory cell ' wherein & the thickness of the lower oxide layer is between 50 and 150. 5. The structure of the discontinuous NR0M memory cell as described in the application and the fourth item of the scope of the invention, wherein the thickness of the lower oxide layer is preferably about? 〇A. 6. The structure of the discontinuous NROM memory cell as described in item 1 of the scope of the patent application, wherein the polycrystalline layer is doped with filler or kun ions. Page 16 TW0738F (Wang Hong) .ptd 550763 6. Scope of patent application ----- 7. The structure of the discontinuous NRM memory cell as described in item} of the patent application scope, wherein the source / drain is a P-type dopant. 8. The structure of the discontinuous NROM memory cell as described in item 7 of the patent scope of Zhongeye, wherein the P-type dopant contains boron or boron fluoride ions. 9. The structure of the discontinuous NROM memory cell described in item 1 of the Chinese Patent Application, wherein the source / drain is an N-type dopant. 10. The structure of the discontinuous NROM memory cell according to item 9 of the scope of the patent application, wherein the N-type dopant system contains phosphorus or arsenic ions. Π · A discrete NROM cell of discontinuous nitride read-only memory, comprising at least: a substrate; a first 0N0 stacked gate and a second 0N0 stacked gate formed on the substrate; The 0 Ν 0 stacked gate is composed of a nitride layer sandwiched between two oxide layers; an oxide layer is formed on the substrate to cover the first 0 Ν 0 stack The gate and the second ON0 stacked gate; a polycrystalline silicon layer formed on the oxide layer; and a source / drain formed on the substrate and close to the first 0N0 The stacked gate and the second 0N0 stacked gate. 1 2 · The discontinuous NR 0 Μ memory cell as described in item 11 of the scope of the patent application, wherein the ONO stacked gate is composed of a top oxide layer and a nitride layer. layer), and bottom oxide layer. 13. Discontinuous NROM memory as described in item 11 of the scope of patent application TW0738F (Wanghong) .ptd Page 17