TW550761B - Method for operating an NROM device - Google Patents
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- TW550761B TW550761B TW091116949A TW91116949A TW550761B TW 550761 B TW550761 B TW 550761B TW 091116949 A TW091116949 A TW 091116949A TW 91116949 A TW91116949 A TW 91116949A TW 550761 B TW550761 B TW 550761B
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000002347 injection Methods 0.000 claims abstract description 17
- 239000007924 injection Substances 0.000 claims abstract description 17
- 230000000694 effects Effects 0.000 claims abstract description 16
- 239000002784 hot electron Substances 0.000 claims abstract description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 239000004575 stone Substances 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 3
- -1 nitride nitride Chemical class 0.000 claims description 3
- 230000005641 tunneling Effects 0.000 claims description 3
- 238000005121 nitriding Methods 0.000 claims 2
- 229920001296 polysiloxane Polymers 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 239000010410 layer Substances 0.000 description 7
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 241001674048 Phthiraptera Species 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- Non-Volatile Memory (AREA)
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Abstract
Description
550761 五、發明說明(1) 本發明是有闕於—種唯讀記憶元件的操作方法,且 別有闕於一種氮化矽唯讀記憶元件(nitride read 、 memory Je'ce,簡稱财〇M device)的操作方法。 目前的氮化石夕唯讀記憶幻牛是利用氧化石夕/氮化石夕/氧 化石夕(〇N〇)複合層所構成之堆疊式(Stacked)結構作為電3 陷入層,而於氧化矽/氮化矽/氧化矽(0N0)層上有間極,了 以及於基底内具有鄰接托夕、店/、议& 百間極, 之材質主要以Ϊ 因為電荷陷入層 二貝彳為虱化矽’所以此種可電抹除且可程式唯讀記 :外 lofc rically erasable programmable ROM)亦稱為 鼠化矽唯讀記憶體(NROM)。 尤%為 由於氮化石夕層具有抓住電荷 層之中的電子並不合 所以射入氮化矽 集中於氮切層的局部區域上日之中而疋 元件程式化時,電子僅合在虱化矽唯讀記憶 部性地儲存J 1接近源極或汲極上方的通道局 存。故而,精由改變p q } 區所施加電壓,可以在單一的氮化: J源極/汲極 :、單-群電子或是不存在電子。因:之2在兩群電 ;:以在單-的記憶胞之中寫入 匕離T唯讀記憶 ::元(=",)之快閃=種單一記 t會逐漸縮小,而導致氮化矽唯钱ne ’閘極線寬 :題,譬如進行程式化操作日在操作上發生 ^ ^ ΐ ; :r:slng)^ ^ ^ ^ ^^ a Λ Λ ρ性地注人電洞(hQle),尤μ㈣多次抹Λ的550761 V. Description of the invention (1) The present invention is based on a method of operating a read-only memory element, and does not include a silicon nitride read-only memory element (nitride read, memory Je'ce, abbreviated as CaiM) device). The current read-only memory of nitrided stone Xiuyu is a stacked structure composed of oxide stone / nitrided stone / oxided stone (〇N〇) composite layer as the electrical 3 sink layer, and the silicon oxide / The silicon nitride / silicon oxide (0N0) layer has interlayers, and there are adjacent Toyo, store /, and &100; poles in the substrate. The material is mainly Ϊ because the charge is trapped in the layer. 'So this kind of electrically erasable and programmable read-only record: the external lofc rically erasable programmable ROM (also known as the ratified silicon read-only memory (NROM). In particular, because the nitrided layer has no ability to capture the electrons in the charge layer, the silicon nitride is injected into the local area of the nitrogen-cut layer and the electrons are only concentrated on the lice when the element is programmed. Silicon read-only memory partially stores the local memory of J 1 near the source or drain. Therefore, the voltage applied by changing the p q} region can be in a single nitride: J source / drain :, single-group electrons or no electrons. Because: No. 2 is written in two groups of electricity ;: To write in a single-memory cell T read-only memory :: Yuan (= ",) flashing = a single record t will gradually shrink, resulting in Silicon nitride only "gate line width: Questions, such as the occurrence of stylized operation on the operation of ^ ^ ΐ ;: r: slng) ^ ^ ^ ^ ^ ^ a Λ Λ ρ sex injection hole ( hQle), You μ㈣ wiped Λ multiple times
cS713twf .ptcj 550761 五、發明說明(2) 因為在源極或沒極上方累積大量電洞,所以與其使用同一 位元線或字元線的另一位元的電子會有嚴重的漏電 (leakage)發生,特別是在高溫下的情形更加嚴重,這就 是所謂的「過度抹除((^61*_61^^)」。而且,在初始電壓 (initial voltage)降低或是通道長度(channel “叫讣) 縮短後,上述情形同樣會更加嚴重。 口因此,本發明之目的是提供一種氮化矽唯讀記憶元件 的操作方法’以防止在源極或汲極上方累積的大量電洞影 響相鄰的另一位元的電子,而產生嚴重的漏電。 本發明之再一目的是提供一種氮化矽唯讀記憶元件的 操作方法,可避免發生過度抹除。 本發明之另一目的是提供一種氮化矽唯讀記憶元件的 操作方法,可以降低作為通道熱電子注入(channei hQt electron injection,簡稱CHEI)程式化的電流。 一根據上述與其它目的,本發明提出一種氮&化矽唯讀記 憶兀件的操作方法,係於源/汲極周圍提供一具重摻雜的 基j。當程式化氮化矽唯讀記憶體時,使用一較正的源極 ,壓(more positive source bias)或是一較負的基底偏 [:(厂:㈣ive substrate bias),藉以增加基底效應 0 y e feet)而降低作為通道熱電子注入 的:”外’在抹除氮化石夕唯讀記憶陣列之前义二 二預,式化操作(pre-programining 〇perati〇n),以程 化氮切唯讀記憶陣列中的所有記憶胞成為寫人的狀態 (written state),來防止過度抹除。cS713twf .ptcj 550761 V. Description of the invention (2) Because a large number of holes are accumulated above the source or non-electrode, there will be a serious leakage of electrons from another bit using the same bit line or word line Occurs, especially at high temperatures. This is the so-called "over-erase ((^ 61 * _61 ^^)". Moreover, the initial voltage is reduced or the channel length is called "channel" After shortening, the above situation will become more serious. Therefore, the object of the present invention is to provide a method for operating a silicon nitride read-only memory element to prevent a large number of holes accumulated above the source or drain from affecting adjacent ones. Another bit of electrons causes a serious leakage. Another object of the present invention is to provide a method for operating a silicon nitride read-only memory element, which can avoid excessive erasure. Another object of the present invention is to provide a nitrogen The operation method of the silicon read-only memory element can reduce the current programmed as a channel hot electron injection (channei hQt electron injection (CHEI) for short.) According to the above and other purposes, The invention proposes an operation method of a nitrogen & silicon read-only memory element, which is provided around a source / drain with a heavily doped base j. When the silicon nitride read-only memory is programmed, a correction is used. More positive source bias or a more negative substrate bias [: (factory: ㈣ive substrate bias), which increases the substrate effect by 0 ye feet) and reduces the injection of hot electrons as channels: "outside" in Prior to erasing the nitride read-only memory array, a pre-programining operation (pre-programining 〇perati〇n) was performed to cut all the memory cells in the read-only memory array into a written state. ) To prevent over-erase.
8713twf.ptd 第6頁 550761 五、發明說明(3) 本發明因為在源/汲極周 :增加程式化的效能。並且在園么供;-具重摻雜的基底’ =是較負的基底偏壓,藉較正的源極偏 作為通道熱電子注入(CHEI) 9力,底效應,故可以降低 在進行抹除前,、萝# — ' 的電流。此外,本發明 /汲極上方、?=預&式化操作,因此可避免在源 而產生嚴重的t 度抹除。 卜;進而防止氮化矽唯讀記憶元件發生過 說明如下·· 、♦軚佳貝轭例,並配合所附圖式,作詳細 圖式之標號說明: ίο ··提供一氮化石夕唯讀記憶元件,其中於源/ 圍誕供一具重摻雜的基底 2 〇 :增加基底效應 3 0 :在抹除前施行預程式化 21 0 :增加源極之偏壓 220 :增加基底之負偏壓 實施例 本實施例主要是以氮化矽唯讀記憶元件(ni tride read only memory device,簡稱NROM device)為例,而 隨著元件不斷縮小,使得執行氮化矽唯讀記憶元件程式化 的機制以通道熱電子注入(channel hot electron inject ion,簡稱CHEI )的方法為主,而其操作步驟如第1 8713twf.ptd 第7頁 5507618713twf.ptd Page 6 550761 V. Description of the invention (3) The invention is based on the source / drain cycle: it increases the performance of programming. And in the garden? -Heavy doped substrate '= is a negative substrate bias, the positive source bias as the channel hot electron injection (CHEI) 9 force, the bottom effect, so you can reduce the erasing Before, Luo # — 'the current. In addition, the present invention / above the drain,? = Pre & type operation, so it can avoid serious t-degree erasure at the source. Bu; further prevent the silicon nitride read-only memory element from being described as follows: ♦ 軚 軚 Example of yoke, and in accordance with the attached drawings, make detailed labeling description: ίο · Provide a nitride nitride read-only Memory element, where a heavily doped substrate is provided at the source / periphery 2 0: Increase substrate effect 3 0: Pre-programmed before erasing 21 0: Increase source bias voltage 220: Increase substrate negative bias This embodiment mainly uses a silicon nitride read-only memory device (NROM device) as an example, and as the device continues to shrink, the execution of the silicon nitride read-only memory device is programmed. The mechanism is mainly based on the channel hot electron injection (CHEI) method, and the operation steps are as follows: 8713twf.ptd page 7 550761
圖所示。 第1圖是依照本發明之一較佳實施例之氮化矽唯讀記 憶元件(NROM device)的操作流程步驟圖。 貝。 請參照第1圖,於步驟1 〇中,提供一氮化矽唯讀記情 元件’其中於源/汲極(source/drain)周圍提供一具重換 雜的基底(heavily doping substrate)。由於本發明的目 的之一是要降低程式化電流,而程式化電流降低又會影響 私式化的效能(programming efficiency)。因此,需使源 /沒極周圍的基底為重摻雜的基底;也就是要增加源/沒 極周圍的基底摻雜濃度(d〇ping concentration),以增加 程式化的效能,而增加基底摻雜濃度的方法例如是利用記 十思胞_子植入製程(ceH implantation)或口袋型離子植 入製程(pocket implantation)。 然後’於步驟2 0中,增加基底效應(b 〇 d y e f f e c t )。 因為藉由通道熱電子注入(CHEI)程式化氮化矽唯讀記憶元 件時’增加基底效應是一種有效降低所需之通道熱電子注 入(CHEI)程式化電流的方法。舉例來說,增加基底效應的 方法可利用一較正的源極偏壓(111〇]:6 p〇sitiVe source bias),就如同步驟21〇中,增加源極之偏壓(Vs);或是利 用較負的基底偏壓(more negative substrate bias), 如同步驟220中,增加基底之負偏壓(|VB|)。 之後’於步驟30中’在抹除(erasing)前施行預程式 化(pre-programming),這是為了消除過度抹除 (over-erase)的問題,而用電子補償注入的電洞 i I 1 1 I ! 11 1 I ! I S I 1 8713twf.ptd 第8頁 550761 五、發明說明(5) (in jected hole)。因此,在進行抹☆之乂 化矽唯讀記憶陣列(array)中的所有=憶:成=程式化氮 態(wntten state)。而施行預程式化之风為寫入的狀 通道熱電子注入(CHEI),還可藉由F_N =不但可藉由 tunnel ing)或任何以電子注入方式的其他^ (mechanism)來施行。表一則是習知方法ρ、制 化矽唯讀記憶元件的操作方法之間的比較以。及本發明之氮 表一 ’As shown. FIG. 1 is a flowchart showing the operation flow of a silicon nitride read-only memory device (NROM device) according to a preferred embodiment of the present invention. shell. Please refer to FIG. 1. In step 10, a silicon nitride read-only memory element is provided, wherein a heavily doping substrate is provided around the source / drain. Since one of the objectives of the present invention is to reduce the programming current, the reduction of the programming current will affect the programming efficiency. Therefore, it is necessary to make the substrate around the source / dim electrode a heavily doped substrate; that is, to increase the doping concentration of the substrate around the source / dim electrode to increase the programming efficiency and increase the substrate doping. The concentration method is, for example, using a ceH implantation process or a pocket ion implantation process. Then, in step 20, the base effect (b o d y e f f e c t) is increased. Because the channel thermal electron injection (CHEI) is used to program the silicon nitride read-only memory element, 'increasing the substrate effect is a method to effectively reduce the required channel hot electron injection (CHEI) program current. For example, the method of increasing the base effect can utilize a corrected source bias (111〇]: 6 poSitiVe source bias), as in step 21, increasing the source bias (Vs); or With more negative substrate bias, as in step 220, the substrate negative bias (| VB |) is increased. Thereafter, in step 30, pre-programming is performed before erasing. This is to eliminate the over-erase problem, and the injected holes i I 1 are compensated electronically. 1 I! 11 1 I! ISI 1 8713twf.ptd Page 8 550761 V. Description of the invention (5) (in jected hole). Therefore, all of the = Memory: 成 = stylized nitrogen state (array) in the siliconized read-only memory array are being wiped. The pre-programmed wind is written in the form of channel hot electron injection (CHEI), which can also be performed by F_N = not only by tunnel ing) or any other mechanism by electron injection. Table 1 shows the comparison between the conventional method ρ and the operation method of the silicon read-only memory element. And the nitrogen of the present invention.
卜—______——丄習知方法I本發明丨 I記憶胞初始電壓(伏特)I ! — — Η 1 丄· d I 2· 5 I 卜 - --+ 丨 程式化V g (伏特)丨 卜 —---——+ 丨 程式化Vd (伏特)t ^ 丨 6 ^ ~ — —I----—+ —— L —(伏特)I 0 | 1二2 ; 、 ----—(------^ 程—式—Ή二公A)丄 350〜4°0 I 5◦〜1。〇 1 猶~,表可知,本發明增加源極之偏壓(Vs),ρα 獲得較習知方、、参俏沾和a ^ ^v s;則可以 法以及本發明夕备儿a , 1 衣一只〗疋習知 k 唯碩記憶元件的操作方法之間的 --1--~ —— 9〜1 1 + 一 --- 1—--— 五、發明說明(6) 式化效能的比較表。 表二 電 流Bu — ______ — 丄 Conventional method I The present invention 丨 I Memory cell initial voltage (volts) I! — — Η 1 丄 · d I 2 · 5 I Bu--+ 丨 stylized V g (volts) 丨 Bu —---—— + 丨 stylized Vd (volt) t ^ 丨 6 ^ ~ — —I ----— + —— L — (volt) I 0 | 1 2 2;, ----— ( ------ ^ 程 — 式 —Ή 二 公 A) 丄 350 ~ 4 ° 0 I 5◦ ~ 1. 〇1 Still, as can be seen from the table, the present invention increases the source bias voltage (Vs), ρα obtains more conventional formulas, spheroids, and a ^ ^ vs; you can use the method and the present invention to prepare a, 1 clothes One 疋 疋 knowledge k operation method of V-Master memory element --1-- ~ ---- 9 ~ 1 1 + one --- 1 ---- 5. Description of invention (6) Comparison Chart. Table 2 Current
丁— Γ 記憶胞數目I I-----1 〜—__ 時間Ding — Γ The number of memory cells I I ----- 1 ~ —__ time
| 習 知 | 5 0 0 # A l·, _ ——— —- I _ ' -- 丁 — I本發明I 100 # A + 丄 + ---- 4 Η + ——— 20 Η Μ秒 本毛月雖…、在知作上需要較多時間 寫入的記憶胞數目遠大於習知一 =因為母 〜體觀之本叙明仍具有較習知高的操作效 因此,本發明的特徵包括: 噥产i::: t在源/汲極周圍的基底具有增加的摻雜 =低 化電流降低時,不會使元件程式化的效 正& s ί i2 7在程式化氮化石夕唯讀記憶元件時使用較 正的源極偏壓或是動;自Mi ^ ^ ^ ^ 負的基底偏壓,藉以增加基底效應, 3 通道熱電子注入(CHEI)程式化的電流。 作,以徒株二為在進行抹除前,還施行一預程式化操 免被抹除:位元寫入的狀態’因此可避 的另-位元的電子,的大量電洞影響相鄰 向屋生嚴重的漏電。 《明藉由改變作用於閘極、源/汲極與基底之偏 550761 五、發明說明(7) 壓,來增加基底效應,以及在抹除前進行預程式化,故可 在不違背元件小型化發展的趨勢下,同時防止過度抹除與 提昇元件程式化效能。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作各種之更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。| 知 知 | 5 0 0 # A l ·, _ ——— —- I _ '-Ding — I This invention I 100 # A + 丄 + ---- 4 Η + ——— 20 Η Μ seconds Although Mao Yue ..., the number of memory cells that requires more time to write in the known works is much larger than that in the first knowledge = because the description of the mother ~ body concept still has higher operating efficiency than the known ones. Therefore, the features of the present invention include : 哝 i ::: t The substrate around the source / drain has an increased doping = When the current is reduced, the device will not be stylized. &Amp; s i2 7 in stylized nitride Use a more positive source bias or dynamics when reading the memory element; a negative substrate bias from Mi ^ ^ ^ ^ to increase the substrate effect and a 3-channel hot electron injection (CHEI) stylized current. Before the erasing, we performed a pre-programmed operation to prevent erasure: the state of the bit write 'so the electrons of another bit can be avoided, and a large number of holes affect the neighboring Serious leakage to the house. "By changing the bias acting on the gate, source / drain, and substrate 550761. 5. Description of the invention (7) pressure to increase the substrate effect, and pre-programmed before erasing, so it can Under the trend of technological development, at the same time prevent excessive erasure and improve the programming performance of components. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.
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