TW546793B - Solder bump structure and laser repair process for memory device - Google Patents

Abstract

A solder bump structure and laser repair process for memory device include forming a first dielectric layer on a bump pad of a semiconductor wafer. After that, the first dielectric layer is etched to form a contact hole and to expose portions of the bump pad. A second dielectric layer is then formed on a surface of the semiconductor wafer outside of the contact hole. An under bump metallurgy (UBM) process is performed to form a metal layer on a surface of the contact hole, and a solder bump is formed on the metal layer. Finally, the laser repair process for memory device is completed.

Description

546793

V. Description of the invention (1) The field of invention (LaSe \ Repaii ^ H is used to form a solder bump for memory laser repair. Background note end f see 1: == installation technology * medium '. High-efficiency electronic components are usually soldered. · (Soider balls) or solder bumps to achieve the purpose of electrical and mechanical connection between each other. For example, an Ultra Urge scale integration (ULSI) can The use of solder balls or solder bumps to form an electrical connection with a circuit board or other secondary stage packaging substrate. This connection technology is called flip-chip bonding ( Flip-chip packaging (FC). Please refer to FIGS. 1-4, which are schematic diagrams of a conventional memory laser repair process on a semiconductor wafer 10. As shown in FIG. 1, the semiconductor wafer 10 includes A substrate 12 is formed on the substrate 2 with an integrated circuit region (not shown), and the integrated circuit region includes a memory structure array. The substrate 12 further includes a bump pad (bump). pad) 1 4. A fuse structure 6 and an alignment key 18, and the bump pad 14 is electrically connected to the integrated circuit area. Therefore, after completing the subsequent packaging process, the integrated circuit The circuit is

Page 5 546793 V. Description of the invention (2) It can be connected with external lightning%, y, external circuit (eye) i 雷 through the bump pads 14. In addition, the fuse structure 16 is made of 1 ms electrical inverse _ ^, Φ I is made on the integrated circuit area

And electrically connect the memory array, squeeze & dive up X ^ J, so when the memory array is completed and a circuit test program is performed to find 苴 Φ #. 〃 After working with some memory cells, word lines (wires) or wires, the fuse structure 16 and a laser repair process can be used to replace some of the memory problems. Cell, character line, or wire. The conventional memory laser repair process is to form a first dielectric layer 20 on the surface of the semiconductor wafer to completely cover the bump pads 14 and the fuse structure 16. The first dielectric layer 20 is also referred to as a passivation layer, and its role is to provide sealing protection to prevent the intrusion of moisture. Next, a yellow light and etching process is performed to form a contact hole 21 in the first dielectric layer 20 above the bump pad 14 and expose a portion of the bump pad 14. It is worth mentioning that the 'first dielectric, layer 20 must be made of a light-transmissive material, so that the laser light can penetrate and cut the fuse structure 16 in the subsequent laser repair process. As shown in FIG. 2, a circuit test procedure is subsequently performed. A probing tip (not shown) is used to electrically connect the bump pads 14 to find out the partially damaged memory in the memory structure of the integrated circuit area. Cells, word lines, or wires, and precisely locate the area to be repaired by the laser through the alignment structure 18, and use a laser cutting (1 aserzip) step to cut off part of the dazzling silk Structure 16 to destroy the electrical connection of memory cells, word lines or wires damaged by this function.

Page 6 546793 V. Description of the invention ⑶ "One to one as shown in Fig. 3, a benzocyclobutene (BCB), polyimide (PI) or PI on the BCB port is formed on the surface of the semiconductor wafer" 0) Second dielectric layer 2 2. Then, as shown in FIG. 4, an under bump metallurgy (UBM) process is performed to sputter-form a metal layer 2 4 and a metal layer 2 4 made of a specific multilayer metal thin film on the surface of the contact hole 21. It has the functions of providing adhesion, diffusion barriers, improving wetting of bump pads and preventing oxidation. Subsequently, a solder bump is formed by evaporation, printing, electricity, dipping, or ultrasonic soldering. The technology is placed on the metal layer 24 at a position opposite to the contact hole 21 to form a solder bump. 2 6. Finally, the semiconductor wafer 10 is placed on a mounting substrate (not shown), and a bonding heat treatment process is performed to melt the solder bumps 26 to produce a surface tension effect to bond the semiconductor wafer 10 to the mounting substrate. The conventional technology first performs the circuit test and the laser repair process, so it may affect the subsequent formation of the second dielectric layer 22 and the metal layer 24. First, the circuit test program is to directly detect the probe. The electrical connection of the bump pads 1 4 ′ may therefore cause a serious probing mark on the surface of the bump pads 14, and the metal layer 24 subsequently formed on the surface of the bump pads 14 is covered in steps. The coverage capability is very poor, which will cause the adhesion and the diffusion barrier function of the metal layer 24 to be lost or weakened, and then affect the reliability of the product. In addition, when the metal interconnect system is used When the copper process technology is used with the low dielectric constant material as the insulating layer between the metals, the circuit test procedure performed directly on the bump pads 14 may face problems such as bare copper or insulation layer cracking due to excessive test force.

Page 7 546793 V. Description of Invention (4). At the same time, the oxidation of the detection marks of copper gaskets after needle testing is also a difficult challenge. Secondly, since the laser repair process performed after completing the circuit test procedure will cut off a part of the fuse structure 16, a plurality of trenches with a large aspect ratio are formed on the surface of the semiconductor wafer 10 ( trench) 27, and voids may be generated in the second dielectric layer 22 that is subsequently filled, which affects product reliability. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a bump and memory laser repairing process to solve the above problems. In a preferred embodiment of the present invention, the method of the present invention first provides a semiconductor wafer, wherein the semiconductor wafer includes an integrated circuit area and a bump pad is formed on the substrate of the semiconductor wafer, and the bump is soldered. The pad is electrically connected to the integrated circuit area. Then, a contact hole is formed in a first dielectric layer above the bump pad, and a part of the bump pad is exposed, and then a second dielectric layer is formed on the surface of the semiconductor wafer outside the contact hole. Then, a bump bottom metal layer process is performed to form a metal layer on the surface of the contact hole and a solder bump at a position opposite to the contact hole. Finally, the bonding of the semiconductor wafer and a mounting substrate is completed.

546793 V. Description of the invention (5) The bump and memory laser repair process of the present invention first performs a bump bottom metal layer process, then forms a solder bump, and then performs a circuit test program through the solder bump. And finally, a laser repair process was performed. In this way, gp can avoid that the circuit test process in the conventional technology may affect the quality of the metal layer formed above the bump pad, or damage the electronic component structure of the semiconductor wafer. In addition, the invention can also It is avoided that the conventional technology may form holes in the second dielectric layer, thereby affecting the reliability of the product. Detailed description of the invention Please refer to FIG. 5 to FIG. 7. FIG. 5 to FIG. 7 are schematic diagrams of a first embodiment of a bump and memory laser repair process on a semiconductor wafer 40 according to the present invention. As shown in FIG. 5, the semiconductor wafer 40 includes a substrate 42, and an integrated circuit area (not shown) is formed on the substrate 42, and the integrated circuit area includes an embedded memory array. The substrate 4 2 further includes a bump pad 44, a plurality of fuse structures 4 6 and an alignment structure 4 a 8, and a silicon oxide layer (not shown). (Shown) formed on the surfaces of the fuse structure 46 and the alignment structure 48. The bump pads 4 and 4 are electrically connected to the integrated circuit area. Therefore, after the subsequent packaging process is completed, the integrated circuit can be electrically connected to the external circuit through the bump pads 4 4. In addition, the fuse structure 46 is fabricated on the upper layer of the integrated circuit area and is electrically connected to the memory structure. Therefore, the memory structure is completed and a circuit test process is performed.

546793 V. Description of the invention (6) sequence to find some memory cells, word lines (word 1 i ne) or wires that have functional problems, then you can use the fuse structure 4 6 and a laser repair (laser repair ) Manufacturing process to replace parts of memory cells, character lines, or conductor lines that have functional problems. In the bump and memory laser repair process of the present invention, a first dielectric layer 50 is formed on the surface of the semiconductor wafer 40 to completely cover the bump pads 4 and the dazzling wire structure 46. The receiver then performs a yellow light and money engraving process to form a contact in the first dielectric layer 50 above the 4 4, a hole 51, and expose a portion of the bump pad 44. As shown in FIG. 6, a second dielectric layer 52 composed of benzocycl obutene (BCB), polyimide (PI) or BCB + PI is formed on the surface of the semiconductor wafer 40, and an etching process is performed to remove the contact holes. 51. The second dielectric layer 52 on the surface of the fuse structure 46 and the alignment structure 4 8 is then subjected to an under bump metal 1 urgy (UBM) process to sputter the surface of the contact hole 51. A metal layer 54 composed of a specific multi-layer metal thin film is formed. The metal layer 54 has functions of providing adhesion, barriers to diffusion, enhancing bump wetting 44, and preventing oxidation. Subsequently, a solder bump is formed on the metal layer 54 with respect to the contact hole 51 by using a technique such as steaming clock, printing, electric clock, dipping or ultrasonic spot welding (U1 tras on ic Soldering). 58. As shown in Figure 7, a circuit test procedure is performed using a probe pin

Page 10 V. Description of the invention (7) __________ iPr ° bingUP) (not in the memory area of the road area) electrically connect the solder bump 5 8 to find the product / W〇r (i Une) or lead Green, columns, memory cells with damaged parts, character lines to be repaired by the laser, and an accurate alignment 48 to find the step to cut off the fusion of the part = accurate laser zip Steps: word line or wire t, Γ structure 46, to destroy the memory of this function damage, and finally connect the semiconductor, and then. After completing the above-mentioned laser repair process, then an access_sheet 40 is placed on a structured substrate (not shown). The surface tension effect is used to connect 1: process the solder bump 5 8 to produce a table + Conductor wafer 40 and, (the structure of the substrate. Please refer to Figure VIII, Figure 8 is too a-2 and memory laser repair ^ = Conductor wafer 80 is carried out in this embodiment, in the semiconductor Schematic diagram of the embodiment. After the contact hole, the process of forming the second dielectric layer 82 and the second dielectric layer 82 on the two and eight sides can also be saved, and the second dielectric layer 52 of this embodiment can be directly sputtered. The metal layer 84 is formed. The manufacturing process of the two-layer metal layer is the same as that of the contact hole surface, and the metal layer 84 is in contact with each other; and is the same as the first embodiment of the invention. The fuse structure of the cut-off part of the bump laser repair process, and the placement of an 80 on the structure substrate (not shown), the structure = a defect, and the sheep conductor wafer process to join the semiconductor wafer 80 and the structure Assembled-bonding the heat treatment to form a first dielectric with the bump provided on the surface of the body wafer ^ ^ Laser repair process is based on one; 丨 Layer, contact hole and coating, + conductor ~ dielectric layer

546793 V. Description of the invention (8), first carry out a process of forming a metal layer of a bump and forming a solder bump, then perform a circuit test procedure through the solder bump, and finally perform a laser repair process. Compared with the conventional bump and memory laser repairing process, the bump and memory laser repairing process of the present invention can avoid the circuit test program directly electrically connecting the probe pin to the bump pad, and may be formed on the solder pad. The quality of the metal layer on the surface of the pad is affected, or the electronic component structure of the semiconductor wafer is damaged. On the other hand, the present invention can further avoid adjusting the groove formed on the surface of the semiconductor wafer by the laser repair process, which will cause holes in the second dielectric layer, thereby affecting the reliability of the product. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

Page 546793 Brief description of the diagrams Brief description of the diagrams Figures 1 to 4 are schematic diagrams of a conventional process for performing a bump and memory laser repair on a semiconductor wafer. Figures 5 to 7 show the invention on a semiconductor. A schematic diagram of a first embodiment of a bump and memory laser repair process on a wafer. FIG. 8 is a schematic diagram of a second embodiment of a bump and memory laser repair process on a semiconductor wafer according to the present invention. . Explanation of symbols in the figure 丨, 10 semiconductor wafer 12 substrate 14 bump bonding pad 16 fused wire structure 18 alignment structure 2 (L · 22 dielectric layer 24 metal layer 26 solder bump 27 trench 40, 80 semiconductor wafer 42 substrate 44, 92 bump pad 46 ^ 88 fuse structure 48, 90 alignment structure 5 0, 52 ^ 82 dielectric layer 51 contact hole 54, 84 metal layer 58 '86 solder bump

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Claims (1)

546793 VI. Scope of patent application 1. A bump and memory laser repair process, the bump and memory laser repair process includes the following steps: Provide a semiconductor wafer, the semiconductor wafer includes a substrate, an integrated circuit (Integrated circuit) and at least one bump pad electrically connected to the integrated circuit is formed on the substrate; a first dielectric layer is formed on the surface of the bump pad; a yellow light and etching process is performed on the substrate Forming a contact hole in the first dielectric layer and exposing a portion of the bump solder; forming a second dielectric layer on the surface of the semiconductor wafer outside the contact hole; performing a bump underlying metal layer An under bump metallurgy (UBM) process to form a metal layer on the surface of the contact hole; forming a solder bump on the metal layer relative to the contact hole; and performing a bonding process to complete the Bonding of a semiconductor wafer to a mounting substrate. 2. For the bump and memory laser repair process of item 1 of the patent application scope, the semiconductor wafer further includes: a plurality of fuse structures electrically connected to the integrated circuit; at least one alignment structure (a 1 i gnm entkey); and a silicon oxide layer is formed on the fuse structures and the surface of the alignment structure. 3. As for the bump and memory laser repair system of the second patent application scope Page 14 546793 6. The scope of patent application, wherein the method of forming the second dielectric layer on the surface of the semiconductor wafer outside the contact hole further includes the following steps: forming the second dielectric layer on the surface of the semiconductor wafer; And performing an etching process to remove the second dielectric layer on the contact hole surface, the fuse structure, and the alignment structure surface. 4. If the bump and memory laser repairing process of item 2 of the patent application 'in which the integrated circuit further includes' an embedded memory array (歹 Ί)' ", 5. The bump and memory laser repair process of the first item in the scope, wherein after forming the solder bump, a circuit probi ng procedure and a laser repair process are included, and the circuit test The manufacturing process uses a probe tip to electrically connect the solder bump to perform the circuit testing process. 6. For the bump and memory laser repair process of the first patent application, the second valence layer includes benzocyclobutene (BCB), ρ ο 1 yimide (PI) or BCB + PI or other functions. Similar insulation materials. 7. A bump and memory laser repair process, the bump and memory laser repair process includes the following steps: providing a half-conductor wafer, the semiconductor wafer includes a substrate, a Page 15 546793 6. Patent application scope An integrated circuit and at least one bump pad electrically connected to the Xi body circuit are formed on the substrate; a dielectric layer is formed on the surface of the bump pad; and a #etching process is performed. A contact hole is formed in the dielectric layer and a part of the bump pad is exposed; an under bump metallurgy (UBM) process is performed to form a metal on the contact hole surface Forming a solder bump on the metal layer relative to the contact hole; and performing a bonding process to complete the bonding of the semiconductor wafer and a mounting substrate. 8 · If the bump and memory laser repair process of item 7 of the patent application process, the semiconductor wafer further includes: a plurality of fuse structures electrically connected to the integrated circuit; at least one alignment key And a silicon oxide layer is formed on the fuse structures and the surface of the alignment structure. 9 · As for the bump and memory laser repair process of item 8 of the patent application, where the integrated circuit further includes an embedded memory array 歹 J 〇 1 0 · As the patent application scope of the seventh The bump and memory laser repair process of the item, which includes a circuit test after the solder bump is formed. Page 16 546793 VI. Patent application procedure (circuit probing) procedure and a laser repair process, and the circuit test process uses a probe tip to electrically connect the solder bump to perform the circuit test Process. Page 17