TW546660B - Current-mode sense amplifier with low power consumption - Google Patents

Abstract

A current-mode sense amplifier for detecting data stored in a flash memory cell. The sense amplifier has a first current generator for generating a first current to a first circuit according to current passing through the memory cell, a second current generator for generating a second current to a second circuit according to current passing through a reference cell, and a switch. When the switch is on and a common node of the first circuit and the second circuit is floating, the first and second circuit will generate equal initial voltages. When the switch is off and the common node of the first and second circuits is ground, one of the initial voltages will increase, and the other initial voltage will decrease.

Description

546660 --- 5. Description of the invention (1) Field of the invention The present invention provides a sensing circuit for flash memory, especially a sensing circuit that operates at low voltage and has low power consumption. Ming Background In recent years, as the demand for portable electronic products has increased, flash memory (f 1 ash) technology and market applications have also matured and expanded. These portable electronic products include i-camera film, video game apparatus, personal digital assistant (PDA) memory, telephone answering device, and programmable IC. Flash memory is a type of non-volatile memory (non-volatile memory). Its operating principle is to control the switching of the gate channel to achieve memory by changing the threshold voltage of the transistor or memory cell. The purpose of the data, so that the data stored in the memory will not be lost due to power interruption. Generally speaking, flash memory mainly includes a floating gate (f 1 〇atinggate) and a control gate for controlling data access. And the gate is isolated from the floating gate by a dielectric layer of 〇〇 (〇ide-nitride-oxide) structure. Therefore, the memory can use the principle of thermoelectron or tunneling to store the inductive charge in the stacked gate, so that the memory stores the signal "0". If " ^ required

546660 V. Description of the invention (2) ~-To replace the data in the memory, you only need to supply a little extra energy, erase the electrons stored in the floating gate, and then write the data again. Take 4 for. The state of each memory cell in the memory body I, must / page uses a sense amplifier (senseamp 1 ifier) to detect the storage state of the induced charge in the memory cell to determine the value represented by the memory cell as 11 0 '' or `` 1 ''. Generally speaking, the conventional sense amplifier uses the sensing mode knife as the voltage mode and current mode. For flash memory operating under low voltage, The voltage swing is too low, so that the voltage-mode sense amplifier cannot operate normally in the low-voltage operating environment. Therefore, the storage state of the induced charge in the memory unit cannot be accurately determined. However, a sense amplifier using a current mode can know the charge storage state of the memory cell in the flash memory under low voltage operation through the influence of the current change on the voltage. Please refer to FIG. 1. FIG. 1 is a circuit diagram of a conventional flash memory sensing circuit 1 〇, the sensing circuit 10 includes a signal generator 11 for inputting a pulse wave, and an output terminal 13 for outputting A signal representing a binary value. The two input circuits 12, 14 are connected to a reference cell 16 (reference cell) and one's own '丨 思 元 18 (memory cell)' a differential amplifier (differential amplifier) 2 0 is used to generate a corresponding output signal according to two different input signals, a voltage source V dd is used to provide the operating bias of the sensing circuit 10, and another differential amplifier 22 is used to process

546660 yuan 1 8 output circuit 1 2, sound 1 2, 1 4 whether the transistor 2 2 transistor, so refer to the single amplifier 22 Shen Tong 2 8 and the differential amplifier unit 18 to produce a phase five, Description of the invention (3) 丨 the reference unit 16 and the corresponding memory voltage change. S2 'is used to control the input transistor 24 and the differential amplifier current mirror). The current mirror is used for the differential current. Similarly, the transistor current mirror is used to memorize the current in the differential amplifier 22 and to the terminal A. , B produces 14 including the control switch si, which is a path or an open circuit. In addition, the current generated by 2 6 forming a current mirror element 16 will generate an electric current of the same size as the electric transistor 22 over time. A current of the same magnitude through the current mirror. The generator 32 'electrically amplifies electricity when it is energized. By the same reason, if the voltage source Vdd provides a "Volt operation 11 input a high voltage level (high) signal = although the signal The output 34 will be turned on, so the voltages at the terminals A and B are reset by the output voltage of the transistor 20 (MM / so the differential number generator 11 is input to a low voltage level (10 "When 32 and 34 are turned off, when the switch S1 is controlled by J Tiger, 'When this path 12, μ forms a path, it is input to the circuit 12] and the current mirror formed by the power transmission crystals 26, 24 is input. Differential current, the current generated by the input circuit 14 is also input to the differential amplifier 22 through an electric current mirror, the current is smaller than that generated by the input circuit 14, and the circuit 12 produces t and j ^ points A through the ground voltage. The voltage of the voltage taste point A reaches J it which makes the transistor 33 conductive ^^

Page 7 546660 V. Description of the invention (4)

At the threshold, the voltage at terminal b has not yet reached the starting value for turning on transistor 35, and then transistor 33 will turn on and the voltage at terminal 6 will drop and become embedded in the ground voltage. The transistor 35 will remain in the closed state, so that the voltage at the terminal A is greater than the voltage at the terminal b, and finally the differential amplifier circuit 20 generates a round voltage close to the voltage source vdd. Similarly, if the current generated by the input circuit 12 is greater than the current generated by the input circuit i 4 ', the differential amplifier circuit 20 will generate an output voltage close to the ground voltage'. Because the sensing circuit 10 operates, the terminal A The scale takes grounding voltage ^ as the initial value, and then gradually increases the voltage. When the initial value that makes the transistor 32 or the electric body 3 4 conductive is reached, the two ends a, B +, and one end will be embedded = The ground voltage drops. However, the other end must continuously input current to increase the voltage to a value close to the voltage source Vdd. Therefore, the sensing circuit 10 of the conventional current mode requires more energy to operate, so its power Power consumption; larger. Summary of the invention Therefore, the main object of the present invention is to provide a fast flash memory circuit for low-voltage operation, and it uses less power. To solve the above problems. '' The scope of the patent application of the present invention provides a flash memory sensing circuit based on the memory cell and a reference unit in the flash memory.

Page 8 546660 V. Description of the invention (5) Current level detection The first generator of the current generation circuit is used according to the circuit. The first end of the output of the electrical connection generator is connected to a voltage of the first circuit and the second The current is reduced to the memory current generator for the first circuit, electricity, the first current and the second voltage approach the first circuit and the first voltage of a circuit at a ground terminal is turned on and the first, The ground of the first circuit is distributed to the data stored in the first circuit and the first voltage and the second voltage. The memory unit powers the first current generator, a current generating a first power and a power supply, and a first sensing circuit including a first generating a first electrical current generating a second generator, and a two-output The current rises to another centered ground voltage. The first current, the output charge of the remaining charge of an interconnect circuit of the first first electrical and the first data, when the open end connection voltage will depend on the first current and the voltage and output signal connection, when the second end The terminal will be averaged so that the supply power is turned off until the output terminal of the receiving device is the second number that refers to the output from the second power to the power. When the switch is floating, the voltage is high and the first ground is connected to the output of the first connected to the unit, the current source of the current source and the second generator of the voltage generator. The second electrical circuit and the first output voltage tend to ground electrical terminals and the and the first currents are based on the and the first output circuit terminals. The memory single circuit is through the second terminal two circuit terminals and the near-low voltage. From the second electric second voltage, the supply voltage is used for the voltage reference, and the two electric currents are generated, and a second second electric current is used for the electric circuit. Residual second circuit supplies this power supply with the starting voltage. The voltage of one of the first electric circuits, the detailed description of the first electric invention

Page 9 546660 V. Description of the invention (6) Please refer to FIG. 2. FIG. 2 is a schematic circuit diagram of the first flash memory sensing circuit 30 according to the present invention. The sensing circuit 30 is based on a memory unit. 32 and a reference current level of unit 34 to detect the binary value represented by memory unit 32. The sensing circuit 30 includes a first current mirror 36, a first circuit 38, a second current mirror 40, a second circuit 42, an output circuit 44 and a power supply 45. The first circuit 38 and the second circuit 42 are symmetrical circuits, that is, the connection methods and specifications of the circuit elements in the first circuit 38 and the second circuit 42 are the same. In addition, a transistor 50 is connected to the first circuit 38 and the second circuit 42, which controls the conduction state via a first clock 51, and when the transistor 50 is turned on, the endpoint in the first circuit 38 The potential of S will approach the potential of the terminal T in the second circuit 42. The other transistor 52 is connected to one end of the first circuit 38 and the second circuit 42, and the conduction state is controlled through a second clock 53 to control whether the first circuit 38 and the second circuit 42 are connected to ground. Voltage. The switches S2, S2, and S3 are used to control whether the memory unit 32 forms a current transmission path with the first current mirror 36, and whether the reference unit 34 and the second current mirror 40 form a current transmission path. When the memory unit 3 When 2 forms a path with the first current mirror 36, the current generated by the memory unit 3 2 will generate a first current 4 6 through the first current mirror 36 and enter the first circuit 3 8. Similarly, when the reference unit When 3 4 and the second current mirror 40 form a path, the current generated by the reference unit 34 will generate a second current 4 8 ′ through the second current mirror 40 and enter the second circuit 4 2. The operation of the memory sensing circuit 30 is described in detail below.

Page 10 546660 V. Description of the invention (7) Please refer to Fig. 2 and Fig. 3. Fig. 3 shows the driving clock of the sensing circuit 30 shown in Fig. 2 ° In this embodiment, the power supply 45 is raised to 30 The bias voltage required for operation (for example, 18 volts), when the electric time is J, the switches SI, S2, S3, and the first clock 51 are at the low voltage level, and the clock 53 is at the high voltage level. "Sensing electricity to -balance", and the terminals s, τ will also reach the same voltage quasi-voltage level is tied to the ground voltage. When the time S2, S3 and the first clock 51 are the handle Φ / ^ 隹 仞The threshold voltage level is changed to a low voltage level & Λ = the second clock 53 will be slightly adjusted from the high voltage level and will also be reached;: The voltage level is higher than the ground voltage. Then, when: Si, s2, and S3 change from a low voltage level to a high voltage level. ^ Take the diurnal 依 3 二 2 as follows: The current generated by the element 32 will generate a corresponding ΐ 2 mirror 54 0 will be based on the reference unit 34. The generated current produces the talented current Yiyi 48, and the transistor approaches the same-voltage level, but because the transistor 52 is V-pass, the brother Yi circuit 3 One end of 8 and the second circuit 42 are connected to the power supply 45, and the other end is connected to the ground voltage. At this time, in the first circuit 38 and the second circuit 42, the transistors 54, 56, 62, 63 The system operates in the saturation region, and the transistors 58 and 60 operate in the linear region (1 inear region). If the second current 48 is less than the first current 4 6, the current flowing through the transistor 60 is also Will be less than the current flowing through the transistor 58 because the transistors 58, 60 operate in a linear region, so the voltage level of the terminal X in the first circuit 38 will be greater than the voltage of the terminal γ in the second circuit 42

Page 11 546660 V. Description of the invention (8) The voltage level, however, the transistor 50 is turned on so that both ends S, T approach a starting voltage (for example, 1 volt) which is greater than the ground voltage at the same time. Transistors 5 4, 5 6 operate in the saturation region, and the gate (ga te) voltage of transistors 5 4, 5 6 approaches the same voltage level at the same time due to the two ends S, T, but the end point X The voltage level is greater than the voltage level of the terminal γ, so the source voltage of the transistor 5 4 will be greater than the source voltage of the transistor 5 6 and the current flowing through the transistor 5 4 will be less than that of the transistor 5 6 As mentioned above, before time 12, the voltage levels at both ends s, T will approach the same level at the same time because the transistor 50 is turned on. When the time is 12, the first clock 5 丨 changes from a low voltage level to a high voltage level, while the switches sl, S2, and S3 remain at the high voltage level and the second clock 53 remains at the low voltage level Position, so the first current mirror 36 will be input to the first — based on the memory unit 32, the six currents and the current 46, and the 38th; and the corresponding 34th element will be generated. The current k ^ = r mirror 40 will be conducted by the transistor 52 according to the reference single circuit 42 '; pair = two: the-terminal of the current flowing into the second circuit 42 will be connected to the ground. "Electricity: 38 and the second circuit The current is less than the current of transistor 56. When the transistor 50 is non-conducting due to the bit of transistor 54, and when the first clock 51 is high voltage quasi-crystal 52, the transistor will be The ^ clock 53 is a low voltage level, which causes the electrical level to drop slightly. Similarly, the ^, the voltage level of the voltage point S of the terminal T in the second circuit 42 is slightly increased, and the I crystal & body 54 will also When the middle end of the first circuit 38 turns on the transistor 6 2, the voltage level of the terminal T when the terminal T decreases and the voltage level of the sensor circuit 3 provided by the last supplier 45 will increase to Near the power transistor gate voltage rise 60 while the voltage at first, and to provide further - make the transistor 60 capable of conducting more current,

546660 V. Description of the invention (9) Therefore, the electric level of the terminal T can approach the grounding electric dust faster, and finally the terminal S reaches a high voltage level and the terminal T is a low voltage level, and then output The circuit 44 outputs an output caret according to the voltage levels of the terminals S and T to represent the binary value represented by the memory unit 32. Similarly, if the second current 4 8 generated by the reference unit 3 4 is greater than the first current 4 6 generated by the memory unit 32, the last endpoint S is a low voltage level and the endpoint τ is high. Voltage level. Please refer to FIG. 2 and FIG. 4. FIG. 4 is a circuit diagram of the output circuit 44 shown in FIG. The output circuit 44 is composed of complementary metal-oxide semiconductor (CMOS) transistors 6 4 and 6 6, and the gate of the transistor 6 4 is connected to the terminal S ′ of the first circuit 3 8 and the circuit. The gate of the crystal 6 6 is connected to the terminal T ′ of the second circuit & 2 and the first day guard pulse 5 1 When the signal of a south voltage level is input, the output circuit 4 4 will start and the transistor 6 will be activated. The inverters composed of 4, 6 and 6 work. When the terminal s is a high voltage level and the terminal τ is a low voltage level, the first output terminal 68 will output a high voltage level and the second output terminal 70 will output a low voltage level. Conversely, when the terminal When the point τ is a high voltage level and the endpoint S is a low voltage level, the first output terminal 68 will output a low voltage level and the second output terminal 70 will output a high voltage level. Terminal 68 or the second output terminal 70 to determine the binary value represented by the memory unit 32. For example, if the first current 46 is greater than the second current 48, the endpoint S is a high voltage level and the endpoint τ is a low voltage level, so the first output terminal 68 of the output circuit will output a high voltage level, that is, the memory unit 3 2 represents

Page 13 546660 V. Description of the invention (ίο) A carry value π 1π, if the first current 4 6 is less than the second current 4 8, the terminal S is a low voltage level and the terminal τ is a high voltage level, so The first output terminal 68 of the output circuit 44 outputs a low voltage level, that is, the memory unit μ represents a binary value π Γ. In this embodiment, the output circuit 44 includes two inverters composed of transistors 64 and 66 to correspondingly process the first current 46 and the second current 48. However, a differential amplifier may also be applied to the first current 4 6 and the second current 4 8 are correspondingly processed, which also belongs to the scope of the present invention. In this embodiment, in addition, since the memory unit 32 is connected to the first circuit 38 through the first current mirror 36, the first current 46 generated by the first current mirror 36 is fixed and will not be affected. The influence of the first circuit 38 changes, so the sensing circuit 30 of the present invention can also be applied to multi-level flash memory.

Please refer to FIG. 5 'FIG. 5 is a schematic circuit diagram of a second flash memory sensing circuit 80 according to the present invention. The sensing circuit 30 shown in FIG. 2 generates a first current 46 and a second current 48 by means of a current mirror. In this embodiment, the first current generator 81 outputs a signal corresponding to the memory. The first current 46 of the unit 32 and the second current generator 8 2 are used to output the second current 4 8 corresponding to the reference unit 3 4. In the sensing circuit 80, the first clock 51, the first The driving clocks of the two clocks 5 3 and the switches S 1, S 2, and S 3 are as shown in FIG. 3, and the voltage levels of the terminals X, Y, S, and T also change as described in the sensing circuit 30. Finally, the output circuit 44 outputs an output signal according to the voltage levels of the terminals S and T to represent the binary value represented by the memory unit 32.

Page 14 546660 V. Description of the invention (11) Please refer to the sensing circuit of the flash memory 100 and 110 (refer to the input terminals shown in the flash memory), and the input pulse is shown in Figure 3, current 46 and circuit 44. I don't want to memorize early FIG. 6 to FIG. 8. FIG. 6 is a schematic circuit diagram of the third flash memory 900 according to the present invention, and FIG. 7 is a circuit schematic diagram of the fourth flash memory circuit 100 according to the present invention. A circuit diagram of the fifth sensing circuit 110 is invented. The sensing circuit 9 0,, the first current 4 6 corresponds to a memory unit (not shown) X, and the second current 4 8 corresponds to a reference unit (the terminal Y is not shown, and the first clock 5 1 As shown in the driving timing of the second clock 53, as described above, the voltage levels of the terminals S and T will change relatively according to the second current 48. Finally, the output according to the An output signal is output from the voltage level to represent the binary value represented by the table element. Compared to the conventional technology, the flash memory sensing circuit of the present invention activates the output circuit to detect the current of the memory unit and the reference unit. Before, the potentials connected to the two ends of the output circuit were first raised to a predetermined level, and then when the current between the memory unit and the reference unit was detected, the potentials at both ends were based on the predetermined level as the starting point. Raising to the high voltage level and the low voltage level, respectively, can greatly reduce power consumption. The above description is only a preferred embodiment of the present invention, and all equal changes and modifications made in accordance with the scope of the patent application of the present invention should belong to The scope of the invention patent.

Page 15 546660 Brief description of the diagram Brief description of the diagram Figure 1 is a circuit diagram of a conventional flash memory sensing circuit. FIG. 2 is a circuit diagram of a first flash memory sensing circuit according to the present invention. FIG. 3 is a driving schematic diagram of the sensing circuit shown in FIG. FIG. 4 is a circuit diagram of the output circuit shown in FIG. 2. Figure 5 is a circuit diagram of a second flash memory sensing circuit of the present invention. Figure 6 is a circuit diagram of a third flash memory i of the sensing circuit of the present invention. Figure 7 is a fourth flash memory of the present invention. Circuit diagram of the sensing circuit of the memory FIG. 8 is a schematic circuit diagram of the sensing circuit of the fifth flash memory of the present invention. Schematic symbol description

10 > 30 ^ 80 > 90 ^ 100 '110 Sensing circuit 11 Signal generator 12 ^ 14 Input circuit 13 Output 16' 34 Reference X XL Early morning 18> 32 Memory unit 20 Differential amplifier circuit 22 Differential amplifier 24 '26 ^ 28 > 30 > Λ 33, 35, 5 (L52 52 54 54 56 1 Λ 58 Page 16 546660 Brief description of the diagram 60 '62> 63, 6 [66 36 First current mirror 40 Second current mirror 44 Output circuit 4 6 The first current 51 The first clock 6 8 The first output 8 2 5 8 3 0 3 4 4 4 5 7 The end of the device should flow out of the body when the electricity is supplied. Electricity No. Electricity No.

Page 17

Claims (1)

546660 VI. Application for patent scope 1. A flash-memory (f 1 ashmem 0ry) current-mode sense amplifier, which is based on the memory cell (memory cell) in the flash memory and a A current level of a reference unit (reference 1 1) detects data stored in the memory unit, and the sensing circuit includes: a first current generator for generating a first current according to the current of the memory unit; a first A circuit electrically connected to the first current generator for generating a first voltage according to the first current output by the current generator, and the first first end is connected to a power supply; a current generator for The first electric circuit, the second electric circuit, and the second electric current are generated according to the current of the reference unit. The second electric circuit generates the second electric circuit corresponding to its connection. When the second terminal is averaged, the output power is output. The electrical output end stores the first floating switch circuit in the memory unit, and is electrically connected to the student's brother. The terminal system is connected to the power supply circuit, and is electrically connected to the circuit. According to the first stored data, the second current generating current generates a first basis, the first electric-voltage circuit and the second are turned on, and the first ground is dispersed to the first electric-first circuit and a circuit. The first voltage, the second voltage, and the output circuit connected to a ground terminal are the voltage of the second output terminal of the circuit approaching the ground voltage; the output of the circuit is applied to the first signal; And the starter lower than the second, the two voltages and the output terminal and the second two voltage switch phase are used to supply voltage to the second two circuit power supply to generate an output circuit of the remaining charge of the interconnection circuit. Should be opened Page 18 546660 6. When the scope of patent application is closed and the second terminal of the first circuit and the second terminal of the second circuit are connected to the ground terminal, one of the first voltage and the second voltage will According to the first current and the second current, the voltage is approached to the supply voltage, and the other voltage of the first voltage and the second voltage is reduced to approach the ground according to the first current and the second current. Voltage. 2. The sensing circuit according to item 1 of the patent application scope, wherein the output circuit includes at least one pair of inverters or at least one differential amplifier. 3. The sensing circuit according to item 1 of the scope of patent application, wherein the first circuit and the second circuit are symmetrical to each other. 4. The sensing circuit according to item 1 of the scope of patent application, wherein the first current generator is a first current mirror for generating the first current and the second current according to the current of the memory unit. The device is a second current mirror for generating the second current according to the current of the reference unit. Page 19