TW546484B - Method for measuring gate-to-body current of metal oxide semiconductor device - Google Patents

Abstract

A kind of method for measuring gate-to-body current of metal oxide semiconductor (MOS) device is disclosed in the present invention. In particular, the invention is related to a method for measuring gate-to-body current of MOS device provided with partially depleted SOI (silicon on insulator) of floating body. The measuring method at least includes the followings: providing a metal oxide semiconductor; providing a bias voltage for the gate of metal oxide semiconductor; providing a pulse signal for the drain of metal oxide semiconductor to be inputted to the metal oxide semiconductor; measuring the source of metal oxide semiconductor to obtain the source current waveform of metal oxide semiconductor; using the source current waveform to calculate the slope in the recovering period of the source current; calculating body conductance of the metal oxide semiconductor; calculating body capacitance of the metal oxide semiconductor; and obtaining a gate-to-body current of metal oxide semiconductor from dividing the value which is achieved by multiplying the slope in the recovering period of the source current with the body capacitance by the body conductance. By using the invented measuring method, it is easy to have accurate gate-to-body current such that it is capable of conducting precise improvement and analysis onto the device and the circuit and decreasing design time and cost of product.

Description

546484 A7 B7 V. Description of the invention () Field of invention: (Please read the notes on the back before filling out this page) The present invention relates to a gate-to-substrate (Gate-to- Body) current measurement method, especially with respect to a partially empty (PartiaUy Depleted; PD) MOS device with a floating body (PartiaUy Depleted; PD) with silicon (SO) on its insulating layer, with its gate to the base The current measurement method is used to accurately measure the gate-to-substrate current of pD s0 IM〇s to accurately optimize the M 0 S element. Background of the Invention: In recent years, semiconductor components have been widely used in the fields of industry, commerce, home, communication, transportation and power. In the next few decades, electronic components will all develop toward miniaturization, integrated circuitization, and the characteristics of low operating voltage, low power consumption, and two operating powers. With the development of semiconductor process technology, the size of semiconductor components is getting smaller and smaller, making the line size into the sub-micro or even the deep sub-micron (Deep Sub_Micr〇) of the Ministry of Economic Affairs Intellectual Property Bureau employees consumer cooperatives printed制 Sphere. As a result of the continuous stacking of components in a limited space, when semiconductor components enter the field of deep sub-microns, in order to improve the operating efficiency of integrated circuits and the consideration of the area occupied by the components, the size of the components must be greatly reduced, so various semiconductors The accuracy required for design and manufacturing processes is increasing. This paper is in accordance with the Standard for Timely Home Care (CNS) A4, Lai 546484 A7 ____B7 _ V. Description of the invention () The circuit produced by the SOI process technology has fast speed, low power consumption, and low-level components. ) Small and strong anti-radiation ability, and can be compatible with the existing VLSI technology and other advantages, so that many circuits based on the S 01 process technology developed rapidly. In the MOS device structure using the SOI process technology, there is a buried oxide layer on the Shixi substrate, and a thin film (often a silicon film) on the buried oxide layer. With the difference in film thickness, SOI MOS devices can be roughly divided into two types: thick film devices and thin film devices. The film thickness of a thick film element is relatively large, so the film is depleted only in the upper part near the gate oxide, and the lower part is maintained as an electrically neutral region. This structure of the MOS device Therefore, it is called that there is a silicon MOS (PD SOI MOS) on a part of the empty insulating layer. In thin film elements, the film is completely empty, so the thin film element is called Fully Empty (Fully

Depleted; FD) SOI MOS. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs π ------------- Installation -------- Order (Please read the precautions on the back before filling this page) Line

The advantage of the PD SOI MOS device is that the thin film is not completely dissociated, so when the gate is biased at the threshold voltage (ThresholdVoltage), the empty area in the film is not affected by the film, so the threshold voltage of the PD SOI MOS is relatively stable. However, due to the incomplete dissociation of the PD SOI MOS thin film, the thin film below its empty region will have an electrically neutral region (Neutral Region), and most of the PD SOI MOS device structure, because of buried oxide Layer and lack of body contact, so PD SOI MOS This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 gong) 546484 Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs Λ7 B7 V. Invention Note () There will be more serious problems such as Floating Body Effect, Parasitic Bipolar Device, and the empty area in the film is easily affected by the source and drain, so PD The secondary effect of soI MOS is more serious. In addition, 'advanced process technology, some technologies used to increase the speed of components and circuits', such as the use of metal ribbons (such as pOlyCide, etc.), shorter channels, thinner gate oxide, etc. Various deep sub-micron components in integrated circuits exhibit different transient phenomena or transient properties, so the precise transient characteristics of components during the design process are not easy to grasp. In particular, when the gate oxide layer of the M 0 S element becomes thinner and thinner (for example, less than 2 5 Α), the gate leakage current becomes more serious, so the tunneling current from the gate to the substrate (Tunneling Current) 'The substrate voltage of a floating substrate MOS device (Flo at ingBodyMOS Device) with a thin gate oxide layer will have a direct effect', for example, the substrate voltage can be changed by about 0.2 volts to about .0.4 volts, thereby making the drain electrode The current produces about 5% to about by. The unequal variation 'seriously affects the voltages between the gate, source, and three poles of the floating base MOS device and their related transient characteristics, and then affects the accuracy of the circuit operation. However, it is very difficult to directly measure the gate-to-substrate tunneling current (leakage current) and its related effects on the floating substrate MOS device. Ordered by _% This paper size applies to Chinese national standards (CNSM4 specification (210x297 cm)) ---- * --- Ordered ----------- Line (Please read the precautions on the back before (Fill in this page) 546484 In the printing technology of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, or it is calculated to be essential. When the leakage current is a thin gate oxygen, the direct current of the shadow-drain triode circuit and the current Now 7A7 B7 V. Description of the invention () The base MOS device lacks the base contact, and compared with other currents in the device, such as the gate-to-channel current, the gate-to-source current and the gate-to-drain The current between the electrode and the substrate is very small, so it is difficult to distinguish between them for measurement. Only by using simulation software (such as T-CAD, SPICE, etc.), the gate to the substrate of the floating substrate MOS device can be measured. Rough simulation analysis and estimation of the current between them to make design adjustments. Purpose and summary of the invention: In view of the above background of the invention, 'the size of current semiconductor process components is getting smaller and smaller, so regardless of the fabrication of the components the amount The degree of difficulty has doubled, but the characteristics of accurate measurement components are measured in order to perform circuit analysis. The gate oxide layer of the MOS device becomes thinner and thinner, and the gate becomes less severe. 'So the gate-to-substrate tunneling current will have an impact on the substrate voltage of a floating substrate MOS device with a chemical layer, which seriously affects the gate, source, and mutual voltages of the floating substrate MOS device and their correlation. Transient characteristics, which in turn affects the accuracy. In the past, simulation software was used to measure the transient characteristics of the gate to the substrate, which can only provide general reference information. Micro MOS components and complex integrated circuits are no longer applicable. The main object of the present invention is to provide a metal oxysemiconducting tin < branches table sheet paper scale turning towel towel miscellaneous standard (CNS) A4 secret ~ 297 meals) equipment --------- order ---- ----- Line (please read the notes on the back of B3 before filling out this page) 546484 A7 R7 V. Description of the invention () Measurement method of the current to the substrate >, θ, especially for those with floating substrate Part of the empty insulation layer is Shi Xi ’s Μ Q ς Kaidu, Pentian,匁 J MUS element The measurement method of the gate-to-substrate current. The application of the present invention < 1 measurement method can effectively and accurately measure the gate of the PD SOI MOS device. Its current from the substrate to the substrate and its related transient characteristics' make the design and development of the device. 〇The solder and circuit layout are optimized precisely, thus reducing product design time and product cost. According to the above-mentioned purpose, the method for measuring the gate-to-substrate current of the present invention includes: providing a gold oxide semiconductor; providing a pulse wave signal to the gold oxide semiconductor at the gold oxide semiconductor's drain electrode; Measure the source to obtain the gold waveform; use the source current waveform to calculate the source slope; calculate the base conductance of the metal oxide semiconductor; bulk capacitance; use the source current during the recovery period to divide by the base conductance to obtain the metal oxide semiconductor For the gate. The measurement method of the present invention can accurately measure the current from the gate to the substrate and its related transient characteristics and circuit layout to be accurately optimized. A measurement method of metal oxyhalide is provided. The gate provides a bias current to the metal oxysemiconductor source current. The metal oxide semiconductor conductance slope is multiplied by the base PD-to-base electrical PD SOI MOS property. The conductor element contains at least the voltage; the body; the base capacitance of the body during the pole current, the current. Design of favorable components. ---------- ^ --------- (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Simple description of the formula: The preferred embodiment of the present invention will be supplemented by the following explanatory texts. The following paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 mm ^) 546484 A7 B7_ V. Description of the invention ( ) The graphics are explained in more detail, in which: FIG. 1 is a schematic circuit diagram of an embodiment of the present invention. FIG. 2 is a detailed circuit diagram of an embodiment of the present invention. FIG. 3 is a waveform diagram showing a voltage between a drain and a source (VDS) in an embodiment of the present invention according to FIG. 2. FIG. 4 is a waveform diagram showing a current (IDS) output from a source of a MOS device according to an embodiment of the present invention according to FIG. 2. Fig. 5 is a diagram showing a current waveform obtained when the source current of the MOS device is affected by the current between the gate and the base, and the analog software is used to measure the source. Fig. 6 is a diagram showing a current waveform obtained when the source current of the MOS device is not affected by the current between the gate and the substrate, and the analog software is used to measure the source. Drawing number comparison description: ............... installation --- pupil- V ---- order ......... line (please read the precautions on the back before (Fill in this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 10 MOS element 12 Base 14 Gate 16 Drain 18 Source 20 Pulse generator 22 Measuring instrument 24 Pulse signal 26 Current 101 Capacitor 103 Capacitor 105 Capacitor 105 Paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 546484 A7 B7 V. Description of invention () 10 7 Diode 109 Diode 111 Current 113 Current 1 15 Current 150 Gate voltage 200 First curve 202 The second curve 204, the third curve 206, the fourth curve 208, and the recovery period (please read the notes on the back before filling this page). Detailed description of the invention: Please refer to FIG. 1, which shows a circuit according to an embodiment of the present invention. schematic diagram. The MOS device 10 in the first figure is a floating base MOS device (such as PD SOI MOS, etc.). A DC bias is applied to the gate 14 of the MOS device 10 to make the MOS device 10 operate in the Triode Region. To increase the accuracy of measuring the current from the gate 14 of the MOS device 10 to the base 12. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the drain 16 of the MOS element 10 is connected to the pulse generator 20, and the source 18 of the MOS element 10 is connected to a measuring instrument 22 (such as an oscilloscope). The pulse wave generator 20 is used to generate a pulse wave signal 24 (such as a square wave pulse wave signal) when measuring the MOS element 10, and is input from the drain 16 to the MOS element 10, and the measuring instrument 22 is used to measure The waveform of the current 26 output from the source 18 is measured. This paper size applies to China National Standard (CNS) A4 (210X297 mm) 546484 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Please refer to Figure 2 for the illustration of the invention Detailed circuit diagram of an embodiment. As shown in FIG. 2, the internal circuit structure of the MOS device 10 in FIG. 1 can be roughly composed of the capacitance 101 between the gate 14 and the base 12 and the capacitance 1 between the pole 16 and the base 12. Capacitance 105 between source 18 to base 12 and diode I 16 between base 16 and base 12 are 〇7 source! It is composed of a diode 10 between 8 and 12. Also, current!丨〗 is the current between the gate j 4 to the base 12, the current 1 1 3 is the current between the gate 14 to the sink 16, and the current 1 1 5 is the gate 14 to the source 18 Current. In addition, in an embodiment of the present invention shown in FIG. 2, the pulse wave generator 20 has an output resistance of 50 ohms, and the input resistance of the measuring instrument 22 is 50 ohms. In the measuring method of the present invention, first, a gate voltage of 150 is applied to the gate of the MOS device 10 to be tested, and a gate voltage of 150 is applied to make the MOS device 10 operate in the triode region. Next, the pulse wave generator 20 generates a pulse wave signal 24 and inputs it to the MOS device 10 from 16 points. Please refer to FIG. 3, which is a waveform diagram of a voltage between a drain and a source (VDS) in an embodiment of the present invention according to FIG. In order to accurately measure the current 1 1 1 from the gate 14 of the M 0 S element 10 to the substrate 12, the measurement method of the present invention uses a square wave pulse signal and inputs it to the MOS at the drain 16. Element 10, and the minimum level of this square wave pulse signal needs to be less than 0. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297) ............. Packing — ---- Order ... (Please read the precautions on the back before writing this page) 546484 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description () The voltage is high. The highest level depends on the design parameters of the MOS device 10 to be measured. Generally, the square wave pulse signal must have a large level difference, that is, the range between the highest level and the lowest level should be as far as possible. It is large to facilitate the measurement instrument 22 to capture the instantaneous waveform of the current 26 output from the source 18. The lowest level of the square wave pulse signal in Figure 3 is about 0.325 volts, the highest level is about 1 volt, and the difference between the lowest level and the highest level is about 0.675 volts. Please refer to FIG. 4, which is a waveform diagram of currents (Ids) output from a source of a MOS device according to an embodiment of the present invention according to FIG. 2. When the MOS device 10 is biased in the triode region, and the square wave pulse signal of FIG. 3 is input from the drain 16 to the MOS device 10, the current 2 6 output from the source 18 appears as shown in FIG. 4 Waveform. The first curve 200 in FIG. 4 represents the waveform of the current 26 outputted from the source 18 when the gate voltage 14 of the MOS element 10 is applied with a gate voltage 1.5 V of 1.5 V; the second curve 202 represents When the gate voltage 14 of the MOS device is applied with a gate voltage of 1.5V of 1.5, the waveform of the current 26 output by the source 18 is presented; the third curve 204 indicates that when the gate of the MOS device is applied with a 1.7V gate The waveform of the current 26 outputted by the source 18 when the electrode voltage is 150; the fourth curve 206 shows that when the gate voltage of the MOS element is applied with a gate voltage of 1.8 V 1 50, the output of the source 18 is The waveform of the current 2 6 is presented. This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) ............... F f ---- Order ... (Please read the precautions on the back before copying this page) 546484 A7 _B7_ V. Description of the invention () First, the first curve 200 is used to explain that when the square wave pulse signal applied to the drain 16 is dropped from a high level to When the level is low, the current 2 6 output from the source 18 is under shoot, and when it falls to the lowest level (approximately 0.00306 amps as shown in Figure 4), the current 26 will be Affected by the current between the gate 14 and the substrate 12, as shown in the first curve 200, it gradually rises back to a fixed value within the recovery period 208 (depending on the square wave pulse signal). It can be seen from FIG. 4 that when the gate voltage 1 50 applied to the gate 14 of the M0S element 10 is higher, the recovery period of the current 26 output from the source 18 is shorter, so that It is known that the magnitude of the gate voltage is inversely proportional to the length of the recovery period. Through the measurement of the measuring instrument 22, the waveform of the current 26 output from the source 18 is known, and then based on the inference of the circuit science, the current IGB between the gate and the base of the M0S element 10 can be obtained. 31s / 5t) x (CB / GB), where Is is the current 26 output from source 18, t is time, CB is the base capacitance, and GB is the base conductance, and (3IS /) is the source 18 output The slope of the current 26 during the recovery period. As shown in Figure 2, the base capacitor CB is the capacitor 101 between the gate 14 and the base 12, and the drain 16 to the base 12 ............... --Order ......... line (please read the notes on the back before filling out this page)

The sum of the three is 5 micro and 10 bias voltage of the electric body 2 base 1 convection electrode 1 drain source and Β. 3 G) 10-lead VB capacitor 3 base Dδ and C points

B G This paper size is applicable to China National Standard (CNS) A4 (210 × 297 mm) 546484

(Please read the precautions on the back before writing this page) Installation · -port; (dls / 5t) x (cb / gb), the relevant data such as the capacitance value and conductance value of M0S element 10 can be easily obtained, Therefore, #According to the waveform of the current 26 output from the source 18 measured by the measuring instrument 22 household kilograms, and respectively substituted into the calculation formula (called / to) of the measurement method of the present invention, you can accurately know the to be measured By electrically grasping 11 11 ′ from the gate 14 of the MOS element ι to the base i2, the Mos element and the related circuit arrangement can be accurately optimized to improve the accuracy of the circuit. Please refer to Figure 5 and Figure 6 at the same time. Figure 5 shows when the source current of the MOS device is affected by the current from the interrogator to the substrate, the simulation software measures the current obtained at the source. The waveform diagram, Figure 6 shows the current waveform diagram of the source at the source when the source current of the MOS Phantom is not affected by the current from the gate to the substrate #current. It can be seen from FIG. 5 that when the operation of the M0s element} 〇 is affected by the current ln between the gate 1 4 j and the substrate 12, the current waveform obtained by analyzing the m0s 4 element 10 using simulation software The shape is very similar to the current wave: shown in Figure 4. Therefore, the measurement method of the present invention can be verified, and the energy between the gate and the substrate printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs can be measured. |:

I I

I I

II Comparing Figure 5 and Figure 6, it can be seen that if the current between the gate 14 and the base 12 of the M0s element is not taken into account, the M0s element is not removed; 12 This paper size applies to China National Standard (CNS) A4 specification (210X297 public love) 546484

、 Explanation of the invention (The current at the source 18 will show the waveform as shown in Figure 6. This waveform lacks the recovery period 208 shown in Figure 4. Therefore, the designer cannot grasp the accurate component parameters. Optimization has certain effects. As the gate oxide layer of a nano-device becomes thinner, the current between the gate and the substrate must have an effect on the source current. Therefore, when optimizing components and circuit simulation, it is necessary to consider and be precise. The current from the gate of the MOS device to the substrate. An advantage of the present invention is to provide a method for measuring the current from the gate of the MOS semiconductor device to the substrate, especially with respect to silicon on the part of the empty insulating layer having a floating substrate. MOS device, its gate-to-substrate current / measure method. Because the measurement method of the present invention is simple and fast, and can accurately measure the gate-to-substrate of floating base MOS device (such as PD SOI MOS device) The current and its related transient characteristics allow the component design and circuit layout and analysis to be accurately optimized, thereby reducing product design time and product cost. ▼ .............. fί _---- 1 (Please read the precautions on the back before writing this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. As understood by those familiar with this technology, the above is only the invention. It is only a preferred embodiment and is not intended to limit the scope of patent application of the present invention. 'All other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the scope of patent application described below. 13 Line This paper size applies to China National Standard (CNS) A4 (210X297 mm)

Claims (1)

^ 0484 Method of measuring patent application range 2: Oxygen semiconductor devices ... to base ... Stream J Insulation :: Gold-oxide semiconductor-where the gold-oxide semiconductor is-a part of the empty insulation layer has a silicon (soi) gold-oxide semiconductor; Provide a -pulse generator connected to the metal-oxide abundant-conductance-drain electrode; use the -source-measurement equipment of the metal-oxide semiconductor; provide the -bias voltage of the intervening electrode of the oxygen + conductor; use the Pulse wave production wada $ TAN # The semiconductor pulse wave signal is turned into the> and pole of the metal-oxygen dry conductor, Japan, ▲ η /, 丄 m 彳. / The R wave signal has the lowest soap level of a pulse wave signal and the highest level of a pulse wave signal. The measurement device is used to perform the step of the source of the metal oxide semiconductor to obtain the combined main waveform. Have a slope; /, calculate the slope; calculate the base conductance of one of the metal oxide semiconductors; δ calculate the base capacitance of one of the metal oxide semiconductors; and multiply the slope by the base capacitance and then divide by the base A conductance is passed through a current from the gate of the metal oxide semiconductor to the substrate. 2. The measurement method described in item 1 of the scope of patent application, wherein the above gold-oxygen semiconductor does not have substrate contact. a 14 This paper size applies the Chinese National Standard (CNs) A4 specification (210X297 mm) 546484 ABCD Patent Application Scope The measurement method described in the first patent application scope, the measurement § is also an oscilloscope. Among them, the above 4. The pulse wave generator of the measuring method described in item 1 of the scope of patent application has a -50 ohm wheel-out resistance. Among them, the above-mentioned measurement method described in item 5 of the scope of patent application: δ has a 50 ohm wheel resistance. 6) If the bias voltage of the first range of the patent application is the measurement method described in the DC bias electric item, press the above 7. If the voltage value of the first bias voltage of the range of the patent application is the Metal Oxygen Half Cropping Area. The measurement method described in the item, the conductor is kept in the above-mentioned triode. 8_ As described in the application ㈣μ㈣1, the minimum level of the pulse wave signal of the square wave pulse signal is not lower than 0. ...............--------, but ......... ^ (Please read the notes on the back before filling this page) Ministry of Economic Affairs The above-mentioned volts are printed by the Intellectual Property Bureau employee consumer cooperative. 9. The measurement method according to item 1 of the scope of the patent application, wherein the above-mentioned base capacitance is the first capacitance between the gate of the gold-oxide semiconductor and the base of the gold-oxide semiconductor, the first capacitance of the metal-oxide semiconductor The drain to the metal oxide semiconductor 15 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 546484 A8 B8 C8 D8 6. A second capacitor between the substrate of the patent-applicable conductor and the source of the metal oxide semiconductor to the The sum of a third capacitor between the substrates. I 0 · The measurement method as described in item 1 of the scope of the patent application, wherein the above-mentioned substrate conductance is a partial differential value of a drain current of the metal-oxide semiconductor to a voltage of a substrate of the metal-oxide semiconductor. II · A method for measuring the gate-to-substrate current of a metal-oxide semiconductor device, which is applied to a metal-oxide semiconductor having a structure with silicon on a partially empty insulating layer. The measurement method includes at least: providing the metal-oxide Semiconductor; providing a bias voltage to the gate of the metal oxide semiconductor to bias the metal oxide semiconductor; providing a pulse signal input to a drain of the metal oxide semiconductor; A measurement step is performed on a source electrode to obtain a waveform of a source current of the metal oxide semiconductor, wherein the waveform has a slope; calculating the slope; calculating a base conductance of the metal oxide semiconductor; calculating the metal oxide semiconductor A base capacitance; and multiplying the slope by the base capacitance, and then dividing by the base conductance to obtain a current from the gate of the gold-oxide semiconductor to the base. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I — — — — — — --IIII · LII I'1 __ ^ «— — —III — — (Please read the notes on the back first (Fill in this page again) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs's Consumer Cooperatives 546484 A8 B8 C8 D8 VI. Application for Patent Scope 1 2. The measurement method described in item 11 of the scope of patent application, in which the above-mentioned gold oxide semiconductor does not have Substrate contact. 13. The measurement method as described in item 11 of the scope of patent application, wherein the above-mentioned pulse wave signal is generated by a pulse wave generator connected to the drain of the metal-oxide semiconductor. 1 4 · The measurement method according to item 13 of the scope of patent application, wherein the pulse wave generator has an output resistance of 50 ohms. 15. The measuring method according to item 11 of the scope of patent application, wherein the above-mentioned measuring step is performed by using a measuring device connected to the source of the gold oxide semiconductor. 16 · The measurement method described in item 15 of the scope of patent application, wherein the measurement device is an oscilloscope. 17. The measurement method according to item 15 of the scope of patent application, wherein the measurement device has an input resistance of 50 ohms. 18. The measuring method as described in item 11 of the scope of patent application, wherein the above-mentioned bias voltage is a DC bias voltage. This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ------------- L ------- Order · ------- -(Please read the precautions on the back before filling in this page) ^^ 0484 6. Application for Patent Scope 19 · Summer test method of the lightning voltage of the bias voltage as described in the application scope of the patent, including the upper working area. The electric house value is to keep the metal-oxide semiconductor at -triode: Γ: "The measurement method described in item 11 of the patent range, the above pulse wave signal is a square wave pulse: the upper and middle levels and- The highest level of the pulse wave signal. Z. The lowest number with a pulse "^ The lowest level of the pulse wave signal of the square wave pulse wave signal described in the measurement method described in item 20 of the patent application range is not lower than. Fu :. The measurement method described in item π of the patent application range above is a first capacitance between the substrates == a first capacitance between the substrates of the semiconductor of the metal oxide semiconductor and the drain electrode of j to the gold The sum of a third capacitance from the source of the oxygen U gold-oxygen semiconductor to the substrate. Printed clothing for employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 23. The measurement method as described in item 11 of the scope of patent application, wherein the above-mentioned substrate conductance is a non-polar current of the metal-oxide semiconductor and a substrate of the metal-oxide semiconductor A partial differential value of the voltage. 18 This paper size applies to China National Standard (CNS) A4 (210 X 297 meals)