544517 A7 B7 656twf.doc/〇〇6 五、發明說明（/ ) 本發明是有關於一種測試電路與測試方法，且特別是 有關於一種於測目式機台上輸入時脈訊號樣式（pattern)的電 路與方法。 在積體電路製作完成後，往往需要進行測試來檢驗該 積體電路是否能夠達成預期的功能與目的。在進行測試 時，通常係將積體電路安裝在測試機台上，之後輸入一測 試輸入訊號。接著再量測輸出訊號並進行比對，檢測所得 到的輸出訊號樣式是否滿足預期的樣式。一般來說，積體 電路都有接收時脈訊號的輸入埠，而此時脈訊號的產生， 許多是由一組晶體震盪焊墊所提供，晶體震盪焊墊通常具 有驅動電路與緩衝器。 一般而言，緩衝器會接在驅動電路的輸出。在測試機 台上，當測試訊號，如時脈訊號，灌入晶體震盪焊墊的輸 入端後，再從緩衝器之輸出讀取輸出的訊號樣式。然而， 晶體震盪焊墊之驅動電路的存在，其對負載的敏感度相當 大，驅動力便會對輸出入訊號造成相位的影響；而另一方 面負載通常是電容性負載，並且不同的測試機台將有不同 的負載。因此，輸出訊號與輸入訊號在時間上往往有移位 (Shift)產生。如第1圖所示，輸入訊號I之上升緣與輸出 訊號〇之上升緣有時間t的移位。這一段時間，往往會使 寫測試圖案（test pattern)的人或測試工程師感到困惑，亦即 造成測試的不確定性。 --種習知的改進方法係將驅動電路改爲三態驅動器， 使輸出與負載無關。但是，三態驅動器需要額外一隻控制 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --裝—— (請先閱讀背面之注意事項再填寫本頁) . 經濟部智慧財產局員工消費合作社印製 544517 A7 B7 6656twf . doc/006 五、發明說明（k) 腳位來進行控制，而增加電路的複雜性以及控制不易。 因此，本發明係提出一種測試電路與應用此電路之測 試方法，其以簡單的電路與方法使測試電路之輸出訊號與 輸入訊號之間沒有時間移位，減少測試時的不確定性’並 藉此增加測試的準確性。 本發明係提出一種測試電路與應用此電路之測試方 法，其使輸出與輸入波形幾乎相等一致’且實際上外加晶 體使之震盪對震盪的輸出入波形之振幅可以接近完整範圍 (full range) ° 本發明揭露一種配合實際測試晶體震盪焊墊電路係用 於測試機台中，以接收一時脈訊號後，再進行測試樣式之 比對。晶體震盪焊墊電路至少包括驅動電路與緩衝器。驅 動電路具有輸入端與輸出端，其中輸入端接收時脈訊號’ 且輸入與輸出端均耦接至測試負載。緩衝器則耦接至驅動 電路之輸入端，以輸出時脈訊號，並將輸出輸出訊號至內 部電路，其中更擷取輸出訊號做爲參考時脈訊號用以進行 測試。 本發明更揭露一種測試電路，其於測試機台中接收測 試樣式(test pattern)訊號後，再量測對應測試樣式訊號之輸 出訊號，其包括一驅動電路與緩衝器。驅動電路具有輸入 端與輸出端，輸入端接收測試樣式訊號，且輸入與輸出端 均耦接至一測試負載。緩衝器耦接至驅動電路之輸入端， 以接收測試訊號，並將輸出輸出訊號至內部電路，其中利 用輸出訊號用以進行測試，輸出訊號係直接從，緩衝器輸出 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） -----------裝--- (請先閱讀背面之注意事項再填寫本頁) · 經濟部智慧財產局員工消費合作社印製 544517 6 5 6ti d o c / Ο 〇 6 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（多） 而不經過驅動電路。 前所述及之緩衝器可以爲波形整形緩衝器（shaping buffer) 0 本發明更揭露一種測試方法，用以檢測測試電路之輸 出訊號。測試電路包括驅動電路與緩衝器，驅動電路與緩 衝器之輸入端耦接一起。首先，輸入一輸入訊號至驅動電 路與緩衝器之輸入端，使輸入訊號分別經過驅動電路與緩 衝器。之後，利用緩衝器之輸出訊號做爲參考時脈訊號’ 進行測試樣式比對，其中輸出訊號僅通過緩衝器，使得輸 入訊號與輸出訊號間沒有時間移位。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如下： 圖式之簡單說明： 第1圖繪示習知測試電路之輸出與輸入波形的比較示 意圖； 第2圖繪示依據本發明之實施例的測試電路示意圖； 第3圖繪示依據本發明之實施例的測試電路所得到之 輸出與輸入波形的比較示意圖；以及 第4圖繪示依據本發明之實施例的測試電路所得到之 輸出與輸入波形的測試模擬圖。 標號說明： 1〇晶體震盪焊墊電路 12驅動電路 14緩衝器 5 本紙張尺度適用中國國家標準（CNS)A4^7Fl〇x297公釐Ί -裝--- (請先閱讀背面之注意事項再填寫本頁) · 544517 6 6 5 61 w f .544517 A7 B7 656twf.doc / 〇〇6 V. Description of the invention (/) The present invention relates to a test circuit and a test method, and in particular to a clock signal pattern input on an eyepiece type machine. Circuit and method. After the integrated circuit is manufactured, tests are often performed to verify that the integrated circuit can achieve the intended function and purpose. When testing, the integrated circuit is usually installed on the test machine, and then a test input signal is input. Then measure and compare the output signal to check whether the output signal pattern meets the expected pattern. Generally, integrated circuits have input ports for receiving clock signals. At this time, many pulse signals are generated by a set of crystal oscillatory pads. The crystal oscillatory pads usually have a driving circuit and a buffer. Generally speaking, the buffer is connected to the output of the driving circuit. On the test machine, when the test signal, such as the clock signal, is poured into the input terminal of the crystal oscillation pad, the output signal pattern is read from the output of the buffer. However, the existence of the driving circuit of the crystal oscillating pad has a large sensitivity to the load, and the driving force will affect the phase of the input and output signals. On the other hand, the load is usually a capacitive load and different test machines The table will have different loads. Therefore, the output signal and the input signal are often shifted in time. As shown in Fig. 1, the rising edge of the input signal I and the rising edge of the output signal 0 are shifted by time t. This period of time often confuses the person writing the test pattern or the test engineer, which causes test uncertainty. -A conventional improvement method is to change the driving circuit to a tri-state driver, so that the output is independent of the load. However, the tri-state driver needs an additional one to control the paper size. Applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)-installed-(Please read the precautions on the back before filling this page). Ministry of Economy Printed by the Consumer Property Cooperative of the Intellectual Property Bureau 544517 A7 B7 6656twf.doc / 006 V. Description of the Invention (k) Pin position for control, which increases the complexity of the circuit and the control is not easy. Therefore, the present invention proposes a test circuit and a test method using the circuit, which uses a simple circuit and method so that there is no time shift between the output signal and the input signal of the test circuit, thereby reducing the uncertainty during the test. This increases the accuracy of the test. The invention proposes a test circuit and a test method using the circuit, which make the output almost equal to the input waveform ', and in fact an external crystal makes it oscillate. The amplitude of the oscillating output and input waveforms can approach the full range ° The invention discloses that an oscillatory pad circuit used in conjunction with an actual test crystal is used in a test machine to receive a clock signal and then perform a test pattern comparison. The crystal oscillating pad circuit includes at least a driving circuit and a buffer. The driving circuit has an input terminal and an output terminal, wherein the input terminal receives a clock signal 'and the input and output terminals are both coupled to a test load. The buffer is coupled to the input terminal of the driving circuit to output the clock signal and output the output signal to the internal circuit. The output signal is also used as the reference clock signal for testing. The invention further discloses a test circuit, which receives a test pattern signal in a test machine and then measures an output signal corresponding to the test pattern signal, which includes a driving circuit and a buffer. The driving circuit has an input terminal and an output terminal. The input terminal receives a test pattern signal, and the input and output terminals are both coupled to a test load. The buffer is coupled to the input end of the driving circuit to receive the test signal and output the output signal to the internal circuit. The output signal is used for testing. The output signal is directly from the buffer output. The paper size is suitable for China. Standard (CNS) A4 specification (210 X 297 public love) ----------- install --- (please read the precautions on the back before filling out this page) Printed 544517 6 5 6ti doc / 〇 〇6 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of invention (many) without passing through the drive circuit. The buffer mentioned above may be a shaping buffer. The present invention further discloses a testing method for detecting an output signal of a test circuit. The test circuit includes a driving circuit and a buffer, and the driving circuit is coupled to the input terminal of the buffer. First, an input signal is input to the input terminals of the driving circuit and the buffer, so that the input signal passes through the driving circuit and the buffer, respectively. Then, use the output signal of the buffer as the reference clock signal ’for test pattern comparison. The output signal passes through the buffer only, so that there is no time shift between the input signal and the output signal. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings, as follows: Brief description of the drawings: FIG. Figure 2 shows a comparison diagram between the output and input waveforms of the test circuit. Figure 2 shows a schematic diagram of a test circuit according to an embodiment of the present invention. Figure 3 shows the output and input waveforms obtained by a test circuit according to an embodiment of the present invention. A comparison diagram; and FIG. 4 is a test simulation diagram of output and input waveforms obtained by a test circuit according to an embodiment of the present invention. Explanation of symbols: 10 Crystal oscillation pad circuit 12 Drive circuit 14 Buffer 5 This paper size is applicable to Chinese National Standard (CNS) A4 ^ 7Fl0x297 mmΊ -Packing --- (Please read the precautions on the back before filling (This page) · 544 517 6 6 5 61 wf.
/ 0 0 I A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（φ ) 實施例 第2圖繪示依據本發明之實施例的測試電路示意圖。 如圖所示，測試電路1〇中包括驅動電路12與緩衝器14。 驅動電路12具有輸入端I與輸出端1〇。緩衝器Μ之輸入 端則連接到驅動電路12之輸入端I，而緩衝器14之輸出 端則更連接到積體電路之內部電路。其中緩衝器14可以 是波形整形緩衝器（shaping buffer)。 驅動電路12之輸出端I◦與輸入端I則分別耦接到負 載上’其通常爲電容性負載Cl、C2，在測試機台上有可 能是87pf或一不確定的數値，其數値將依不同機台而異。 在測試機台上不並聯震盪器，然而在實際電路上，晶體則 並聯於測試電路1〇與負載Cl、C2之間。 此時’用來作測試用所灌入的時脈訊號便由輸入端I 輸入’之後分別經過緩衝器14與驅動電路12。在進行測 試時’便從緩衝器14之輸出端〇輸出做爲參考時脈訊號 到積體電路內部。灌入的輸入波形則可以爲方波的時脈訊 號或是弦波訊號。由於量測到的輸出訊號不經過驅動電路 12,所以不會受到驅動電路的推動力所影響，且由負載α、 C2對輸出波形所造成的波形影響也可以降低。同時此電 路組態對實際上並聯之晶體的震盪狀態也不會有影響。 第3圖係繪示依據本發明之實施例的測試電路所得到 之輸出與輸入波形的比較示意圖。當一個時脈方波從驅動 電路12之輸入端I輸入時，其在驅動電路12之輸出端1〇 的輸出波形則如圖中間之波形所示。緩衝器14之輸出端 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 544517 6656twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（f) 〇的輸出波形則如圖下方所示。由圖可以看出，輸入端I 的波形與輸出端〇之波形兩者之間並不存在時間移位。亦 艮P，輸入端I的波形的上升端與輸出端〇之波形的上升端 是一致的。因此，使用本發明的電路並不會產生如同習知 般的波形移位的問題出現。因此，在進行做輸出波形的樣 式測定時便不會有不明確的區域出現，且可以使測試結果 更加正確性。 第4圖繪示依據本發明之實施例的晶體震盪焊墊電路 並聯晶體做爲震盪器所得到之輸出與輸入波形的震盪模擬 圖。其中曲線⑴代表驅動電路12輸入端I所灌入的波形， 曲線(II)代表驅動電路12之輸出端I◦所量測的波形，而 曲線(III)代表緩衝器14之輸出端〇的輸出波形。由實際 的模擬測試圖來看，本發明之電路確實可以達到其目的。 對應於本發明之電路在測試機台上的測試方法敘述如 下。如前所述’晶體震盪焊墊電路包括驅動電路與緩衝器， 其中驅動電路與緩衝器之輸入端耦接一起。首先，輸入一 輸入訊號至驅動電路與緩衝器之輸入端，使輸入訊號分別 經過驅動電路與該緩衝器。接著，從緩衝器之輸出讀取輸 出訊號’進行測試樣式比對，其中輸出訊號僅通過緩衝器， 使得輸入訊號與輸出訊號間沒有時間移位。 如前所1述’由於量測到的輸出訊號不經過驅動電路 12,所以不會受到驅動電路的推動力所影響，且由負載ci、 C2對輸出波形所造成的波形影響也可以降低。同時此電 路組態對實際、说聯晶體做成的震盪電路時也不會造成傷 7 本紙張尺度適用中國國豕標準（CNS)A4規格do X 297公爱） (請先閱讀背面之注意事項再填寫本頁)/ 0 0 I A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (φ) Embodiments Figure 2 shows a schematic diagram of a test circuit according to an embodiment of the present invention. As shown in the figure, the test circuit 10 includes a driving circuit 12 and a buffer 14. The driving circuit 12 has an input terminal I and an output terminal 10. The input terminal of the buffer M is connected to the input terminal I of the driving circuit 12, and the output terminal of the buffer 14 is further connected to the internal circuit of the integrated circuit. The buffer 14 may be a shaping buffer. The output terminal I and the input terminal I of the driving circuit 12 are respectively coupled to the load. 'It is usually a capacitive load Cl, C2. It may be 87pf or an uncertain number on the test machine. Will vary by machine. The oscillator is not connected in parallel on the test machine. However, in the actual circuit, the crystal is connected in parallel between the test circuit 10 and the loads Cl and C2. At this time, the clock signal which is used for test purposes is input through the input terminal I, and then passes through the buffer 14 and the driving circuit 12, respectively. During the test, it is output from the output terminal 0 of the buffer 14 as a reference clock signal to the inside of the integrated circuit. The input waveform can be a square wave clock signal or a sine wave signal. Since the measured output signal does not pass through the driving circuit 12, it is not affected by the driving force of the driving circuit, and the waveform effect caused by the load α, C2 on the output waveform can also be reduced. At the same time, this circuit configuration will not affect the oscillation state of the crystals connected in parallel. FIG. 3 is a schematic diagram showing a comparison between an output and an input waveform obtained by a test circuit according to an embodiment of the present invention. When a clockwise square wave is input from the input terminal I of the driving circuit 12, the output waveform at the output terminal 10 of the driving circuit 12 is shown in the middle waveform. Output end of buffer 14 6 This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page). 544517 6656twf.doc / 006 A7 B7 Ministry of Economy Printed by the Intellectual Property Bureau's Consumer Cooperatives 5. The output waveform of invention description (f) 〇 is shown below. It can be seen from the figure that there is no time shift between the waveform of the input terminal I and the waveform of the output terminal 0. That is, the rising end of the waveform at the input terminal I is consistent with the rising end of the waveform at the output terminal 0. Therefore, using the circuit of the present invention does not cause the problem of conventional waveform shifts. Therefore, there will be no ambiguous areas when performing the type measurement of the output waveform, and the test results can be made more accurate. FIG. 4 shows an oscillation simulation diagram of the output and input waveforms of a crystal oscillation pad circuit according to an embodiment of the present invention. The curve ⑴ represents the waveform filled by the input terminal I of the driving circuit 12, the curve (II) represents the measured waveform of the output terminal I of the driving circuit 12, and the curve (III) represents the output of the output terminal 0 of the buffer 14. Waveform. Judging from the actual simulation test chart, the circuit of the present invention can indeed achieve its purpose. The test method of the circuit corresponding to the present invention on a test machine is described below. As mentioned earlier, the crystal oscillation pad circuit includes a driving circuit and a buffer, wherein the driving circuit and the input terminal of the buffer are coupled together. First, an input signal is input to the input terminal of the driving circuit and the buffer, so that the input signal passes through the driving circuit and the buffer respectively. Then, the output signal is read from the output of the buffer for test pattern comparison. The output signal passes through the buffer only, so that there is no time shift between the input signal and the output signal. As described in the foregoing paragraph 1, since the measured output signal does not pass through the driving circuit 12, it is not affected by the driving force of the driving circuit, and the waveform impact caused by the load ci and C2 on the output waveform can be reduced. At the same time, this circuit configuration will not cause damage to the actual oscillator circuit made of connected crystals. 7 This paper size applies to China National Standard (CNS) A4 specification do X 297. (Please read the precautions on the back first.) (Fill in this page again)
· ϋ ϋ I n n ϋ ϋ^δ,τ I ι ϋ I n ϋ l I .%· 544517 A7 B7 6656twf.doc/006 Γ - 五、發明說明（< ) 害。因此，本發明提供一個解決測試問題中向位偏移的問 題。 綜上所述，本發明之測試電路與應用此電路之測試方 法與習知技術相較之下至少具有下列之優點與功效： 依據本發明之測試電路與應用此電路之測試方法，# 不必對電路做大幅修改便可以改善習知電路與測試方法_ 缺點，故開發新電路的成本可以節省。 依據本發明之測試電路與應用此電路之測試方法，g 以簡單的電路與方法使測試電路之輸出訊號與輸入訊號2 間沒有時間移位，減少測試時的不確定性，測試工程師_ 以藉此增加測試的準確性。 依據本發明之測試電路與應用此電路之測試方法，g 可以使輸出與輸入波形幾乎相等一致，且對震盪的輸出A 波形之振幅可以接近完整範圍。· Ϋ ϋ I n n ϋ ϋ ^ δ, τ I ϋ ϋ I n ϋ l I.% · 544517 A7 B7 6656twf.doc / 006 Γ-V. Description of the invention (&); Therefore, the present invention provides a solution to the problem of bit shift in the test problem. To sum up, the test circuit of the present invention and the test method using the circuit have at least the following advantages and effects compared with the conventional technology: According to the test circuit of the present invention and the test method using the circuit, # 别 对The circuit can be greatly modified to improve the conventional circuit and test methods. _ Disadvantages, so the cost of developing a new circuit can be saved. According to the test circuit of the present invention and the test method using this circuit, g uses a simple circuit and method so that there is no time shift between the output signal and the input signal of the test circuit 2 to reduce the uncertainty during the test. This increases the accuracy of the test. According to the test circuit of the present invention and the test method using this circuit, g can make the output and input waveform almost equal, and the amplitude of the output A waveform to the oscillation can approach the full range.
綜上所述，雖然本發明已以較佳實施例揭露如上，g 其並非用以限定本發明，任何熟習此技藝者，在不脫離^ 發明之精神和範圍內，當可作各種之更動與潤飾，因此I 發明之保護範圍當視後附之申請專利範圍所界定者爲準QIn summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in this art can make various changes and modifications without departing from the spirit and scope of the invention. Retouching, so the scope of protection of the I invention shall be determined by the scope of the attached patent application.
(請先閱讀背面之注音P事項再填寫本頁J ^--------訂--------- 經濟部智慧財產局員工消費合作社印製(Please read the note P on the back before filling in this page. J ^ -------- Order --------- Printed by the Employee Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
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