TW538627B - Apparatus and method for compensating clock phase of monitor - Google Patents

Abstract

An apparatus for compensating a clock phase of a monitor is disclosed, in which a first memory stores reference digital data, a PLL generates a predetermined sampling clock, synchronized with a horizontal synchronizing signal and a vertical synchronizing signal applied from a main body, and an A/D converter samples an analog image signal received from the main body according to the sampling clock. The A/D converter converts the analog image signal to a digital image signal, and a second memory temporarily stores the digital image signal by a frame unit, after a scaler formats it as a frame. A microcomputer extracts digital data from the digital signal output from the scaler to control the PLL according to whether the extracted digital data is substantially equal to the reference data stored in the first memory. Thus if a clock phase set by a user is changed, for example due to environment, the change can be detected and automatically compensated to maintain a normal screen state.

Description

538627 V. Description of the invention (1) Background of the invention 1. Field of the invention The present invention relates to an image display, and more particularly to a method and device for compensating the phase of a deformed clock. 2.Related technology background Generally, the image display is a device used to display image signals. It has image modes such as SVGA (800X600), XVGA (1 280X1 024), and the columns are transmitted by the main body connected to the display. Video letter & going out. “二 如” The main body is a video card of a workstation or a personal computer. In addition, the Hai display was initially based on cathode ray tube technology. Recently, digital displays that are suitable for large-area displays and that use liquid crystal displays (LCDs) as plate-shaped display units have been commercialized. Because of the current development, there is a trend towards large-sized display devices. trend. The display of the unrelated technology shown in FIG. 1 includes the microcomputer 1, and according to the second of the horizontal synchronization signal and the vertical synchronization signal sent from the main body: ί = Ρ image mode. The microcomputer controls ‘3 f 3 H t or processing operations according to the image mode output. Next, the phase-locked loop (PLL) 2 generates a clock pulse according to a control signal from the microcomputer.

538627 V. Description of the invention (2) Shi r Cai Wei, and matchmaker ^ to digital (A / D) converter 3, according to PLL 2! # A 'D / D The transmitted R / G / B image signal ^ π 二 ia: ° Converts the analog number into a digital signal. The scaler 4 uses the ^ 6 digital signal size output from the A / D converter 3 to the frame unit to reflect the microcomputer i control signal using the PLL 2 clock pulse. Finally, the frame buffer memory 5 stores the output of the scaler 4, and lcd = and 6 according to the control signal of the microcomputer i, the image signal in the memory 5 is extracted. The display operation of the related art described above will be described below. First, the microcomputer 1 outputs a control signal to pLL 2. The PLL 2 then provides a sampling clock based on the horizontal / vertical synchronization signal frequency transmitted from the main body to the A / D converter 3 and the ratio. In particular, ρ ^^ 2 generates a clock pulse preset signal according to the control signal of the power supply, and provides the clock pulse to the A / D converter 3 and the proportional device 4. The A / D converter 3 samples the R / G / B image signal transmitted from the main body according to the sampling clock provided by the PLL 2, and converts the analog image # number into a digital signal. Output. Proportioner 4 is then based on a microcomputer! Control signal to regulate A / d conversion

Page 6 538627 V. Description of the invention (4) ~ '一 ~ ----------

In order to achieve the full or partial realization of at least the clock phase, the device includes storage; the advantage J-; the memory body 'produces a horizontal i and a vertical synchronization from the main body 4 古 vc ^ HS y π c to The PLL sampling clock synchronized by the Chinese master and UL_V_Sync. For the PLL connected to the clock, the analog reference signal and the analog video signal are taken according to the sample. The D frame of the digital video signal output by the D converter is The A / D conversion output stored in the third image is essentially the same as the microcomputer that is stored in the first memory to control the PLL. And the PLL: dry or partial To achieve at least these advantages, the method of compensating the clock phase of the PLL, including the PLL, the PLL, the PLL, and the PLL can be set by referring to the preset reference digital data and displaying the clock phase f, that is t, After a preset period of time, the iiV is extracted and displayed on the current screen by controlling the PLL to adjust the output phase of the clock pulse, so that whether the iuVW digit data Λ matches the digital asset displayed on the current screen. The reference digital data can match the display on the current screen. Digits on the screen "A, and if the adjusted digital data can match the preset reference digital material, the adjusted clock phase value is stored. In order to fully or partially achieve the above-mentioned object of the present invention, 538627 V. Description of the invention (5): 2: The clock generator including the first memory that stores reference data, and the sample clock that generates the sample clock with the sample clock According to the exchange 3 !, the π-type image signal is converted into the second-format image signal and the conversion unit converts the second memory module of the second-format image signal into a unit that sends the second-format image signal to the display. Data, the virtual computer used to extract the second format image signal from the sampler ’s microcomputer and control the clock generation based on the compensation result for the full or partial; the method provided by the method includes compensation for the purpose of the present invention. + "", The phase of the clock, the sentence will be set to the old digital lean value, according to the preset on the OSD to remove the 'bit adjustment bar, after the first pre-number :: shell material to display the number of clock phase Deletion, decided to show the phase of the punch on the current glory, so that when: is expected, and adjust the clock pulse = image data is equal to the reference digital data, = tone;

The method provided in order to further or partially process the image signal includes in vivo, the data in the received image signal processing is extracted by the first format image signal, and the first format image signal is converted into the first to achieve the above-mentioned object of the present invention, and the storage is controlled. Preset the reference value to the first memory = one-way video signal, use the control signal with the same frequency information, ~ the one-way video signal, and adjust the second

538627 V. Description of the invention (6) ~ ^ ~ Format of the image signal, generating a frame unit, feeding back the feedback signal to the image signal processor, and comparing the feedback signal with the reference value, and adjusting the control signal according to the comparison result . ratio

In order to further fully or partially achieve the above-mentioned object of the present invention, an image signal control system including an image signal processor is disclosed. The image signal processor receives a first format image signal, generates a control signal, and converts the image signal into In a second format, the image signal control system further includes a first memory coupled to the image processor and storing at least one preset reference value, including receiving a second format image signal, generating a frame unit, and providing feedback number 1. A scaler for an image processor, wherein the image processor uses the feedback signal to control the conversion of the image signal. Other advantages, objectives, and characteristics of the present invention will become more apparent to those skilled in the art after reviewing the following description, or the technology may be learned from the experience of the present invention. The purpose and advantages of the present invention: The detailed description of the preferred embodiment is shown in the scope of the attached patent application or is particularly special. The detailed description of the preferred embodiment is shown in the device for compensating the clock phase of the display according to the preferred embodiment of the invention Display = in Figure 2. Including phase-locked loop (ρα) 3 which generates clock pulses,

A / D to sample the analog R / G / B video signal to be transmitted from the body

Page 10 538627, Description of the invention (7) It also provides the first memory 20, which stores the preset reference value of the digital image data output by the A / D converter 40, and provides a microcomputer 10, which is 1 / D conversion. The digital image data output from the device 40 and fed back to the microcomputer 10 = the reference digital image data stored in the first memory 20. Is it best to control when errors occur? 1 ^. Secret μ followed by 'Proportioner 5' uses the clock pulse provided by PLL 30 and the control signal of ICON and PC 10 to adjust the digital R / G / B output from A / D converter 4 to the frame unit. Image signal size. The second memory 60 is used to store the output of the scale 50, and the LCD module 70 is used to display the digital image information stored in the second memory after the size of the scaler 50 is adjusted. . The first memory is preferably EEPR0m, and the second memory 60 is preferably a frame buffer memory. u Now it will be explained that the operation of the device for compensating the clock phase of the display is 0 '. First, the microcomputer 10 generates and outputs a control signal to the PLL 30. The PLL uses this frequency to generate and provide a sampling clock signal to the A / D converter 40 according to the frequency of the horizontal / vertical synchronization signal sent from the main body. In particular, the 'PLL 30 generates a clock pulse preset by the control number of the microcomputer 10. 538627 V. Description of the invention (8) Punch' in order to provide the clock pulse to the A / D converter 40. A / D converter 4 〇 Then according to the clock pulse, sample the analog R / G / B image signal sent by the main body, and convert the R / G / B image ^ number into a digital R / G / B Video signal, output the digital R / g / b video signal to the scaler 50. The digital image signal output by the scaler 50 is then fed back to the microcomputer 10, and the microcomputer 10 extracts a preset area size from the digital image signal in order to detect the corresponding number of clock pulses. The number of detected clock pulses is compared with the reference data stored in the first memory 20, and the occurrence of an abnormal clock phase is detected. History In other words, the microcomputer 10 determines whether the data stored in the first test corresponds to (for example, equivalent to) the digital data in item 1 and 2 ?, and refers to the digital data detected from the field D item. ;. ,,, and later, if the currently extracted digital data is larger or smaller than the digital reference data stored in memory 20, an abnormal clock phase occurs. If this is true, it is expected that the PLL 30 will be produced to increase or decrease the PLL variables and / or output control signals to the digital image data of the variable A / D converter 40 to change the PLL phase. After the digital shadow | data #number and digital comparison to compensate the clock phase. But & like

538627 V. Description of the invention (9) " — ----—— The -m'0 stores the output of the a / d converter 4〇, which is stored in the first § = body 60, with the frame as The unit is then changed according to the LCD module 7. Show its output. Technique 2: It is explained that the phase of the display clock used to compensate the display according to the present invention is shown in FIG. 3 'The user is best to manually readjust the data ^ 1 " digital video signal Vram, and will correspond to the reference digital The shirt looks like VraiD-part of it is displayed on the OSD, as shown in step 31. Then-determine whether the preset time interval has passed or failed, as in step I ::, the result of the decision is' If the preset time passes in step S3, say Yutian-Dimuxian Non-fluorescent digital data (A) will be extracted. 々 Then, it is determined whether the extracted digital data (A) corresponds to the reference digits stored in the first memory q ^^^^, as shown in step S4. 0 if The decision result of step S4 is' If the extracted digital signal (A) does not correspond to the reference digital data stored in the first memory, it is determined whether the extracted digital signal (A) has a value smaller than the reference digital data, such as Step S5 is shown.

Page 13 538627 V. Description of the invention (10) '' a ~ ^ = The value of the reference digital data ham stored in the memory of the first brother, it is determined that there is an abnormal clock phase i. It is therefore possible to control the PLL and then increase the phase of the OSD display to control the clock phase, as shown in step%. As shown in the following if step ^, the digital shadow controlled by pll is extracted. Then, it is determined whether the controlled digital image data B has a value equal to the multi-test digital data Vram, as shown in the steps. The decision result of step S8 is that if the controlled digital image data 8

; 1 = 2 refers to the value of the digital data Vram, and stores the phase variable corresponding to the update number seven = image _ shell material B, as shown in step ". In addition, the position of the upper display rod will be based on the stored clock The phase variable is changed, as shown in step S10. Then, as shown in step S11, it is determined whether the power supply is turned off or in order to complete the entire process. The result of step S5 is that if the digital signal (A) is extracted, the reference digital data is used. The value of Vram controls the PLL and reduces the ^ bit by 1, as shown in step S12. The output number to the stored number is then extracted as shown in step S13, and the bit controlled by pll is extracted > material 0 'to determine Whether the extracted digital data c is a cheap value Vram is shown in step S14.

Page 14 538627 V. Description of invention (12) State generation. Therefore, the normal screen state can be maintained, thereby improving the reliability of the display.

The above embodiments and advantages are merely illustrative and are not intended to limit the present invention. What has been proposed so far has been applied to other types of devices. The description of the present invention is intended to be illustrative, and not to limit the scope of the claimed patent. There are many other ways, modifications and changes that will be apparent to those skilled in the art. In the scope of the patent application, the method plus function sentence is intended to cover the structure described here. If the structure that can perform the above functions is not only structurally equivalent, but also an equivalent structure

Page 538627 Brief description of the drawings Brief description of the drawings The invention will be described in detail with reference to the following drawings. Similar reference numbers in the drawings refer to similar units, of which: Figure 1 is a conventional technology display Schematic block diagram. Fig. 2 is a schematic block diagram of a device for compensating a clock phase of a display according to a preferred embodiment of the present invention.

3 is a flowchart of a method for compensating a clock phase of a display according to a preferred embodiment of the present invention. Reference number in the figure 1 0 Microcomputer 2 0 First memory 3 0 Phase frequency locked loop (P L L) 40 Analog to Digital (A / D) converter

5 0 Scaler 6 0 Second memory

Page 17

Claims (1)

538627 Case number 89116338 6. Scope of patent application1. A display device, including a first memory, storing reference data, and a clock generator step; generating a sampling clock, and converting at least one synchronization signal into a first format image signal into a first A converter, according to the sampling clock two format image signal;-a second memory, using the frame as a unit, to store the second format image signal;-ratio: the device 'forms and transmits the second format image signal in the frame unit to A display module; and a microcomputer, extracting data 'comparative reference data' from the second format image signal output by the scaler, and controlling the clock generator based on the comparison result. 2. The device according to item 1 in the scope of the patent application, wherein the first memory is an electrically erasable programmable read-only memory (EEPROM). 3. The device as described in item 1 in the scope of the patent application, wherein the reference material is a clock pulse of a plurality of second-format image signals' is input from a scaler 538627 -— Case No. 89116338__ Year Amendment 6. Scope of Patent Application Out ’and sampled from the preset area after scanning. 4. The device according to item 丨 in the scope of patent application, wherein the second memory is a frame buffer memory. 5. Install to digital (A / D) converter as described in item 1 of the scope of patent application. 6: = The device described in item 丨 in the scope of patent application, wherein the clock generator is a phase-locked frequency loop. 7 · A method for supplementing the display of the clock phase, including: · Setting the reference data value; ^ The clock phase adjustment corresponding to the on-screen display (0SD) reference data has passed the first preset time * '㈣ appears on the screen The scene data on the scene; determine whether the reference material is essentially equal to the image data; control the clock pulse generator and adjust the output phase of the clock pulse to change Page 19 2003. 04. 24.017 538627 J ^ _19U6338 6. Scope of patent application Image asset department, make the image data equal to the reference data in quality; and, for example, the clock phase value of the adjusted image data at the moment of this adjustment.疋 When it is equal to the reference data, store 8. As the 7th place in the scope of the patent application, the steps of rushing the output phase include the following methods: • The method of adjusting the clock pulse to pass the-preset time |, scan the preset area, In order to extract the image data; the image signal on the screen and determine whether the extracted image data is smaller than the reference data; if the extracted image data is determined to be less than the phase change of the clock plus the clock generator & If it is m, continue adding materials. Putting the sampling data is equal to the reference data 9 :: Please ask ::;: =; The method described in the item package is displayed after the first preset time of the image signal on the clock pulse is scanned, and it is displayed in the preset Area to extract image data; determine whether the extracted image data is larger than the reference data; and 2003. 04. 24.018 538627 Case No. 89116338 6. If you apply for the patent scope section, then increase until you extract the image data & the poor section is equal to the reference data. If the extracted image data is determined, it is greater than the phase variable of the reference data plus the clock generator , So far. 1 0 · If the image data at the time of application for patent scope order No. 7 and · is equal to the 夂 === method at the beginning, if the extracted data is' extracted again, the image data is passed through the second preset. Π. 如The clock phase adjustment rod described in item 7 in the scope of the patent application, wherein the display is updated at 0SD, which is based on adjusting the clock phase. 12 · If in the scope of patent application ... The image data should be displayed on the screen as described in step 2. The method, in which the extracted periodical image data is taken from the preset time unit. The 7th output phase in the method is adjusted, in which the clock pulse makes the image data equal to the reference data. 1 4 · If Shen Qing's patents are digital image data. The method described above, wherein the image data 15. If the patent application is digital data. The method lost in item 7 of the above, the reference material is 2003. 04. 24.019, page 21, 538627. Amendment VI. Apply for speciality, 16 methods for controlling the image, including: storing the preset reference data in the first memory; receiving The video signal in the first format is transmitted to the video signal processor; the control signal generated according to the class rate extracted from the video signal in the first memory volume is used to convert the video signal in the first format into the video signal in the second frame. ; Scale the image signal in the second format, and generate a pivot unit and a feedback signal based on the image signal in the second format; feed the feedback signal to the image signal processor, and compare the feedback signal and the reference value 'and according to the comparison As a result, the control signal is adjusted. 17 The method according to item 16 in the patent application park, wherein the first format is an analog format and the second format is a digital format. 18. The method according to item 16 in the patent application park, wherein if the feedback signal is not equal to the reference value, the control signal is adjusted. Page 22 2003. 04. 24. 020 538627 _Case No. 89116338_Year_Month__ VI. Patent application scope 1 9. An image signal control system, including: an image signal processor, receiving a first-format image input Signals, generate control signals, and convert the image signals into a second format; a first memory coupled to the image signal processor to store at least one preset reference; and a scaler coupled to receive the second format The image signal unit generates a frame unit and provides a feedback signal to the image signal processor, wherein the image signal processor uses the feedback signal to control the conversion of the image signal. 20. The system according to item 19 in the scope of the patent application, wherein the first format is an analog format and the second format is a digital format. Page 23 2003. 04. 24. 021