TW538464B - Method of forming buffer layer on polysilicon gate - Google Patents

Abstract

This invention provides a method of forming a buffer layer on a polysilicon gate, especially a method using nitrogen ion implantation and thermal oxidation to from a hybrid layer of silicon oxynitride and silicon dioxide on the polysilicon gate for use as a buffer layer. This invention uses the ion implantation method to implant nitrogen ions onto the surface of the polysilicon gate, which is followed by forming a solid hybrid layer of silicon oxynitride and silicon dioxide on the surface of the polysilicon gate through thermal oxidation process. The hybrid layer of silicon oxynitride and silicon dioxide formed on the polysilicon gate can prevent other ions from diffusing into the polysilicon gate and affecting critical dimension of the polysilicon gate.

Description

538464 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for making a buffer layer (buffer 1 ayer), and more particularly to a method for utilizing nitrogen ion implantation and thermal oxidation in polycrystalline stones. A method for forming a mixed layer of oxynitride and oxydioxide on a gate electrode (ρ ο 1 ysi 1 ic ο ngate) as a buffer layer. The mixed layer of silicon oxynitride and silicon dioxide formed on the polycrystalline silicon gate by the method of the present invention can prevent the stress defect of the polycrystalline silicon gate, and prevent the polycrystalline silicon gate from affecting its critical size due to the entry of other ions. 5-2 Background of the Invention: Generally, when manufacturing a spacer for polycrystalline silicon gates, most of the materials used for the spacers are insulating materials to reduce the current leakage defects of polycrystalline silicon gates. A buffer layer is usually formed on the outside of the polysilicon gate to increase the bonding between the spacer and the polysilicon gate, and to prevent defects such as leakage current and stress from occurring on the polysilicon gate, which affects the quality of the semiconductor device. Generally, the insulating material used for the bulkhead is nitrided silicon nitride, and the combination of nitrided silicon and polycrystalline silicon is not high. Therefore, if a buffer layer is not formed outside the polysilicon gate, the polysilicon gate and the gap The wall will be prone to voids, which will affect the quality of the semiconductor device. The function of the buffer layer is to serve as the interface between the polysilicon gate and the spacer.

Page 4 538464 V. Description of the invention (2) In order to increase the bonding quality between the polycrystalline silicon gate and the gap wall, so that the polycrystalline silicon gate does not cause defects such as leakage current or stress, the material of the buffer layer must be the same as that of the polycrystalline silicon gate and The material of the partition wall has a good degree of combination in order to exert its due effectiveness. Generally, the material used for the buffer layer is silicon dioxide, because it has a good degree of combination with polycrystalline silicon and silicon nitride as a spacer. The traditional methods for forming a silicon dioxide layer on a polycrystalline silicon gate as a buffer layer are thermal oxidation methods. First, the crystal circle on which the polycrystalline silicon gate has been formed on the substrate is sent to the furnace tube reaction chamber. When the temperature of the reaction chamber reaches 700 ° C, oxygen is introduced, so that oxygen ions penetrate into the surface of the polycrystalline silicon gate, and react on the surface of the polycrystalline silicon gate to form a silicon dioxide film as a buffer layer. Although the silicon dioxide layer formed by the thermal oxidation method can successfully combine the polycrystalline silicon gate and the spacer, so that the polycrystalline silicon gate does not cause defects such as leakage current and stress, the oxygen atoms are not easily affected in the thermal oxidation process. control. In the thermal oxidation process, oxygen atoms easily penetrate too deeply into the polycrystalline silicon gate, and react with silicon atoms inside the polycrystalline silicon gate to form a silicon dioxide layer, thereby reducing the original size of the polycrystalline silicon gate. This situation easily affects the electrical properties of the polycrystalline silicon gate, thereby reducing the quality of the semiconductor device. The buffer layer can also use chemical vapor deposition (chemical vapor d e p o s i t i ο η) to form a monocrystalline silicon dioxide and silicon oxynitride on the polycrystalline silicon gate.

Page 5 538464 V. Description of the mixed layer of (3), but the structure of the mixed layer is relatively loose. When the polycrystalline silicon gate continues the process of making the barrier wall, the ions in the barrier wall will still break through the mixed layer and enter Polycrystalline silicon gates affect its electrical properties. Therefore, the mixed layer of silicon dioxide and silicon oxynitride formed on the polycrystalline silicon gate by chemical vapor deposition must undergo a re-oxidation process to densify the mixed layer. During the reoxidation process, oxygen atoms will still penetrate the inside of the polycrystalline silicon gate and affect the standard size of the polycrystalline silicon gate. Therefore, a buffer layer must be formed on the polycrystalline silicon gate by using the method of the present invention. 5-3 Purpose and summary of the invention: In view of the above background of the invention, it is impossible to form a suitable buffer layer on the polycrystalline silicon gate by the traditional method. The present invention uses silicon ion implantation and thermal oxidation to form silicon oxynitride on the polycrystalline silicon gate. The mixed layer with silicon dioxide is used as a buffer layer to control the critical size of the polysilicon gate. A second object of the present invention is to form a mixed layer of silicon oxynitride and silicon dioxide as a buffer layer on a polycrystalline silicon gate by means of nitrogen ion implantation and thermal oxidation, so as to simplify the process steps and increase the process efficiency. A third object of the present invention is to form a mixed layer of silicon oxynitride and silicon dioxide as a buffer layer on a polycrystalline silicon gate by means of nitrogen ion implantation and thermal oxidation, so as to reduce the diffusion or extension region of the source / drain. .

Page 6 538464 V. Description of the invention (4) The fourth object of the present invention is to form a mixed layer of silicon oxynitride and silicon dioxide as a buffer layer on a polycrystalline silicon gate by means of nitrogen ion implantation and thermal oxidation. Expansion of the bird's sbeak area on the gate oxide layer. The recipe is for the chemical layer, oxygenation, thermal mixing, and fragmentation of the phytochemical oxygen. Nitrogen and quality silicon products are converted into oxygen parts of the nitrogen element mesh. The upper part of the upper half of the gate is then raised to raise the silicon crystals to crystallize. The method of nitriding the nitrogen into the children's form is the first step to stop the supply of the gate and prevent the silicon from being lifted. The crystal is made of multiple layers. According to the silicon roots of silicon, the oxygen ionization from the nitrogen and the semi-gate of the conducting ring are more transparent, and the silicon oxide crystals that pass through the inch ruler are controlled by silicon, and the multi-layered sound is slow. This is 5 ο internal The gate of the electrode is a silicon crystal region. • The layered pieces of the cut bird's elementary oxygen gate are reduced to a small height, within which the bottom region of the material domain is fragmented and expanded. The process of the source and bottom regions of the gate electrode oxygen drain and gate The process of commanding the heights and raising the steps is less subtraction. The production rate of the original rate and the original rate are borrowed from the effect and the operation details are explained in detail. 4 I 5 are detailed except the following.

Page 7 538464 V. Description of the invention (5) In addition to the detailed description, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited, which is subject to the scope of subsequent patents. It has been reported that the electrical components that form the gate internal components of the gate, and the bird's bird pecking element, use the thermal oxygen-silicon dioxide layer in the multi-buffer layer system, which cannot affect the polymorphism. Infiltrate the quality of the gate's oxygen region. The polycrystalline silicide layer on the crystalline silicon gate electrode, which is based on the Tinan semi-chemical method or layer, or the oxygen-generating protolith, will expand the formation of the nitrogen conductor element, which is the original size of the chemical vapor phase silicon dioxide and the heating. In the source of the original oxygen silicon substrate of the gate electrode, the source and the drain electrode are separated from the silicon oxide by nitrogen and the quality of the two pieces. During the process of nitrogen oxidation by deposition, the gate region will be implanted with silicon oxide. The infiltration of polycrystalline silicon affects the semi-permeation into the oxide layer, and the mixing of shadow and thermal oxygen> Polycrystalline silicon conductor element Polycrystalline silicon is susceptible to a semi-conductive square layer as shown in the first figure. A gate oxide layer 2 2 is formed on the wafer silicon substrate 10 and a polycrystalline silicon layer 24 is formed on the gate oxide. Layer 2 2 on. Referring to the second figure, after the position of the polycrystalline silicon gate is defined, a photoresist layer 30 is formed on the polycrystalline silicon layer 24 on the polycrystalline silicon gate. The extra gate oxide layer 22 and polycrystalline silicon layer 24 are removed through a coin-cut process, and the photoresist layer 30 is removed by cleaning with a chemical solvent. A polycrystalline silicon gate has been formed on the silicon substrate 10 of the wafer. pole. Referring to the third figure, this is a schematic diagram of a polysilicon gate 20. The polysilicon gate 20 includes at least a polysilicon layer 24 and a gate oxide layer 2 2 (

Page 8 538464 V. Description of the invention (6) 2 2—The polycrystalline silicon layer 24 is formed by a thermal oxidation method. The gate oxide layer is a formed pad oxide layer formed on a silicon substrate and on the gate oxide layer 22. f As shown in the fourth figure, the nitrogen ion 40 is implanted on the surface of the polysilicon gate 20 'the gas ion 40 is implanted from all directions to the surface of the polysilicon gate 20, and the silicon in the silicon gate 20 The atomic reaction becomes silicon nitride, and a silicon nitride layer 45 can be formed on the surface of the polycrystalline silicon gate 20. Nitrogen ion 4 〇 Through the implanted two f: Z also enters the bottom of the polycrystalline silicon gate 20, and a silicon nitride layer 45 is formed at the polycrystalline silicon gate 20 =, or with the polycrystalline silicon gate The gate oxide layer 22 at the bottom of the electrode 20 reacts to form a gas oxide layer. There are many ways to implant nitrogen and sub 40. Nitrogen ion 40 can be implanted on the surface of polysilicon gate 20 by ion bombardment S-type or electro-forging implantation. The energy of nitrogen ion 40 was introduced to control the depth of nitrogen ion ^ 〇 implanted on the surface of Xi Jing Shi Xi gate 2 0, so as to avoid implantation too deep and affect the original size of Shi Xi closed pole 20. The energy implanted by nitrogen ion 4 〇 is generally large, and the spoon is 200 to 5 0 0 electronic Ford (electric voltage; eV), and the amount of nitrogen ion 40 implanted is approximately per cubic centimeter 丨E 丨 4 to 1 £ 丨 7 nitrogen ions 4 0. The process time for implanting nitrogen ion 40 varies depending on the implantation method, and is generally about 120 to 180 seconds. The wafer that has been implanted with nitrogen ion 40 is sent to the furnace tube reaction chamber for the thermal oxidation process. When the temperature of the reaction chamber reaches 600 to 7000c,

538464 V. Description of the invention (7) Pass oxygen into the reaction chamber and keep warming. When the temperature of the reaction chamber is heated to 750 to 900 ° C and maintained for 120 to 240 seconds, the furnace is then lowered. The temperature in the reaction chamber is taken out and the wafer is taken out to end the thermal oxidation process. At this time, a mixed layer 50 of silicon oxynitride and silicon dioxide will be formed on the surface of the polycrystalline silicon gate to serve as a buffer layer of the polycrystalline silicon gate 20, Refer to the fifth figure. The entire thermal oxidation process takes approximately 1 800 to 1260 seconds. The thickness of this mixed layer of silicon oxynitride and silicon dioxide 50 is about 10 to 50 angstroms. When the primary 4 5 that is infiltrated into the silicon nitride oxide in the early stage of heat is more dense, the oxygen atoms can only be used in silicon and dioxygen because of the oxygen atoms. The main purpose is to make it stronger and unable to penetrate the polycrystalline nitride; the mixed layer of the fossil layer of the layer 4 and 5 penetrates into it and has a size that enters the oxygen atomic surface during the thermal oxidation process. In the silicon nitride layer, a mixed layer 50 is formed as a buffer layer through the reaction. Furnace tube plus polycrystalline silicon gate 2 silicon nitride layer on the surface of the silicon oxide layer 2 5 on the surface of the silicon nitride layer 4 5 when oxygen is turned on for thermal oxidation process, the surface is oxidized to form nitrogen and oxygen 5 0. Therefore, the polycrystalline silicon gate does not react with Shi Xi atoms inside, and the polycrystalline is reduced to affect the quality of the semiconductor device. The equipment used for the thermal oxidation process in this embodiment is a furnace tube. The slow temperature rise process enables the buffer layer formed on the surface of the polycrystalline silicon gate 20 to be more dense and the structure to be more robust, so that the When the spacer is subsequently made, impurities will not penetrate into the polysilicon gate through this buffer layer, which will affect the electrical properties of the polysilicon gate, and shrink the polysilicon gate 20 area.

Page 10 538464 V. Defect of invention description (8), but it does not limit the scope of invention. A mixed layer of silicon oxynitride and silicon dioxide 50 formed at the bottom of the polycrystalline silicon gate 20 can be used as a gate oxide layer to prevent oxygen atoms from penetrating into the gate oxide layer 2 through penetration in the thermal oxidation process. 2, and bird peck occurs at the gate oxide layer 22. This mixed layer of silicon oxynitride and silicon dioxide 50 can further prevent oxygen atoms from penetrating through the gate oxide layer 2 2 into the silicon substrate 10 under the gate oxide layer 2 in the thermal oxidation process, and Reacts with silicon atoms in the silicon substrate 10 to expand the source / drain range. Using the method of the present invention, a mixed layer 50 of a silicon oxynitride layer and a silicon dioxide layer is formed on the surface of the polycrystalline silicon gate 20 as a buffer layer, and this buffer layer can be fully combined with the polycrystalline silicon gate 20 and the gap wall. As a good interface, the current leakage and stress defects of polycrystalline silicon gate 20 are avoided. By using the method of the present invention, a buffer layer can be formed on the polysilicon gate 20 surface more quickly, so as to improve the efficiency of the process and reduce the cost of production. According to the embodiment described above, the present invention provides a method for implanting a surface of a polycrystalline silicon gate with nitrogen ions to form a silicon nitride layer and subjecting it to a thermal oxidation process to form silicon oxynitride on the polycrystalline silicon gate. The mixed layer of silicon and silicon dioxide is used as a buffer layer to prevent oxygen atoms from penetrating into the polycrystalline silicon gate during the thermal oxidation process, which affects the size of the polycrystalline silicon gate and further affects the electrical properties of the semiconductor device. This buffer layer can also be fully combined with the polysilicon gate and the spacer to avoid current leakage from the polysilicon gate.

Page 11 538464 V. Description of the invention (9) Defects. This buffer layer can further inhibit oxygen atoms from penetrating the gate oxide layer and the silicon substrate at the bottom of the gate, reducing the bird peck area and the source / drain diffusion area of the gate oxide layer, which has improved the quality of semiconductor devices. With the method of the present invention, the steps of the traditional manufacturing process are reduced, and the operating efficiency and productivity of the manufacturing process are improved. It has not only practical effects, but also a design never seen before. The new type of requirements must be applied for in accordance with the law and documents. For this reason, the examiners would like to examine the details in detail and pray that the grant of the patent will be granted as soon as possible. The above description is only a preferred embodiment of the present invention. This embodiment is only used for illustration, not for limiting the scope of patent application of the present invention. It can still be implemented without departing from the essence of the present invention. Such changes should still fall within the scope of the present invention. Therefore, the scope of the present invention is defined by the following patent application scope.

Page 538464 Brief description of the diagram The first picture is the intention of depositing a gate oxide layer and a polycrystalline layer on the wafer stone substrate, and the second picture is a photoresist formed at the position of the polysilicon gate A schematic diagram of a layer on a polycrystalline silicon layer; the third diagram is a schematic diagram of forming a polycrystalline silicon gate on a wafer substrate; the fourth diagram is an intent to implant gas ions into the surface of the polycrystalline gate; and the fifth The figure is a schematic diagram of forming a mixed layer of silicon dioxide and silicon oxynitride on the surface of a polycrystalline gate after the wafer undergoes a thermal oxidation process. Symbols of the main parts: 1 wafer substrate 2 polycrystalline silicon gate 2 2 gate oxide layer 2 4 polycrystalline silicon layer 3 0 photoresist layer 40 nitrogen ion 4 5 silicon nitride layer 5 0 silicon oxynitride and dioxide Mixed layer of silicon

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Claims (1)

538464 VI. Application Patent Scope 1. A method for fabricating a buffer layer on a polycrystalline silicon gate, which at least includes: a shape-increasing constant resistance layer; an etching gate implantation degree; and a wafer for general use The wafer includes at least a substrate; a gate oxide layer is formed on the substrate; a polycrystalline stone layer is formed on the gate oxide layer; a position of the polycrystalline silicon gate is defined at the position Forming a gate oxide layer and a polycrystalline silicon layer of a photolithographic portion to form an appearance of the polycrystalline silicon; removing the photoresist layer; inserting a nitrogen ion onto a surface of the polycrystalline silicon gate; placing the wafer in a reaction An oxygen gas is introduced into the reaction chamber and one of the reaction chambers is heated to enter the reaction chamber to form the buffer layer. 2. The method according to item 1 of the patent application scope, wherein one of the materials of the gate oxide layer mentioned above may be pulverized dioxide. 3. The method according to item 1 of the patent application, wherein a material on the surface is silicon nitride. 4. The method according to item 1 of the patent application, wherein the energy of the nitrogen ion is about 2000 to 5000 e-Ford. Page 14 538464 6. Scope of patent application 5. For the method of the first scope of patent application, the number of nitrogen ions mentioned above is about 1 E 1 4 to 1 E 1 7 per cubic centimeter. 6. The method according to item 1 of the patent application range, wherein the buffer layer includes at least one oxynitride and one oxidant. 7. A method for fabricating a buffer layer on a polycrystalline silicon gate, which at least comprises: providing a wafer, the wafer including at least a substrate; forming the polycrystalline silicon gate on the substrate, and the polycrystalline silicon gate at least Including a gate oxide layer and a polycrystalline stone layer; implanting a nitrogen ion into the polycrystalline stone gate to form a nitride stone layer; placing the wafer in a reaction chamber and raising one of the reaction chambers Temperature, and a gas is introduced into the reaction chamber to form the buffer layer. 8. If the method according to item 7 of the patent application is applied, one of the materials of the gate oxide layer mentioned above may be silicon dioxide. 9. The method according to item 7 of the patent application, wherein the energy of the nitrogen ion is about 2000 to 5000 e-Ford. 10. The method according to item 7 of the scope of patent application, wherein the number of nitrogen ions mentioned above is approximately 1 E 1 4 to 1 E 1 7 nitrogen ions per cubic centimeter. I Page 15 538464 6. Scope of patent application 1 1. The method according to item 7 of the scope of patent application, wherein the above buffer layer includes at least silicon oxynitride and silicon dioxide. 12. The method according to item 11 of the scope of patent application, wherein the thickness of the buffer layer is about 10 to 50 angstroms. 1 3. The method according to item 7 of the scope of patent application, wherein the above-mentioned gas includes at least Page 16