經濟部智慧財產局員工消費合作社印製 538374 7 863twf.doc / 〇〇6 五、号务明說明（/) 本發明是有關於一種指令快取裝置及方法，且特別是 有關於一種使用指令讀取緩衝器（instruction read buffer， IRB)之指令快取裝置及方法。 快取言己憶體（cache memory)主要由快取指令^<記憶體 (cache instruction word memory)以及快取標籤記憶體 (cache tag memory)所構成，且快取指令字記憶體與快取 標籤記億體所儲存之指令字與標籤爲互相對應的。所以一 般當中央處理器（CPU)需要存取記憶體時，就會先檢查 快取標籤記憶體中是否有所需指令字（instruction word)之 標籤（tag)。如果有，也就是代表快取指令字記憶體中有 所需之指令字，也就是所謂的指令命中（instruction hit)， 然後由快取標籤記憶體發出一個指令命中信號給快取指令 字記憶體以從快取指令字記憶體中讀出所需之指令字。如 果沒有，也就是指令命中失敗（instruction miss)時，則再 透過匯流排界面裝置從主記憶體中讀出此所需之指令字。 請參考第1圖，熟悉此技藝者可知習知指令快取之裝 置與方法爲’當需要存取CPU所定址的指令字時，會先到 快取標籤記憶體108，109中是否符合其所需之指令字之標 籤。此快取標籤記憶體108，109中所存之標籤，也就是存 在快取指令字記憶體106以及快取指令字記憶體1〇7中所 存指令字之標籤。再藉由快取標籤記憶體1〇8，1〇9其耦接 之比較器111以及比較器112將快取標籤記憶體108，109 中所存之標籤與可程式計數器115所輸出之信號（此信號 包括CPU所需要指令字位址之標籤）相比。如果相符，即 ·· (請先閱讀背面之注意事項再填寫本頁) 訂---------線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 538374 7 863twf. doc / 006 A7 137 經濟部智慧財產局員工消費合作社印製 五、考务明說明（1) 指令命中，比較器111就會輸出一個指令命中信號，使得 多工器104藉由對此所需指令字所在之快取指令字記憶體 做提取的動作，然後輸出此所需之指令字。 如果不符合，即指令命中失敗，CPU就會透過匯流排 界面裝置101 (buffer interface unit即BIU)對主記憶體提 出請求，等待主記憶體回應給匯流排界面裝置101。然後暫 存在指令S賈取緩衝器102 ( instruction read buffer)中。且 於匯流排界面裝置101回應一個指令字至指令讀取緩衝器 102時將原本存於指令讀取緩衝器102中之一個指令字寫 入快取指令字記憶體106或107中。 請參考第2圖，此習知之指令讀取緩衝器102爲相當 於記憶體（memory)中的一條線(line)，可存放4個指令字 (WO、Wl、W2、W3)，也就是一次同時存放四個指令字， 多工器103以多工器in輸入端之可程式計數器115以及 寫入指標信號作爲控制，當下一個指令字要暫存入指令讀 取緩衝器102時，多工器1〇3控制以一次一個指令字的方 式寫入快取指令字記憶體106或快取指令字記憶體1〇7 中，再藉由多工器104將所需之指令字由快取指令字記憶 體106或快取指令字記憶體1〇7取出給CPU使用。 因此，當指令命中失敗時，CPU就必須多花費下面的 時間來完成指派所需之指令字的動作。 所需的時間約爲：CPU對主記憶體提出要求所需的時 間+匯流排界面裝置等待回應所需的時間+寫入快取指令 字記億體所需的時間+指派所需之指令字所需的時間。 本紙張瓦度適用中國國家標準（CNS)A4規格（210 X 297公爱) ---------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 538374Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 538374 7 863twf.doc / 〇〇5, the number of instructions (/) The present invention relates to an instruction cache device and method, and in particular to an instruction read Instruction cache device and method for instruction read buffer (IRB). The cache memory is mainly composed of cache instruction word memory (cache instruction word memory) and cache tag memory (cache tag memory), and cache instruction word memory and cache The instruction words and labels stored in the tag memory are corresponding to each other. So generally, when the central processing unit (CPU) needs to access the memory, it will first check whether there is a tag of the instruction word in the cache tag memory. If there is, it means that there is a required instruction word in the cache instruction word memory, which is the so-called instruction hit, and then the cache tag memory sends an instruction hit signal to the cache instruction word memory. To read the required instruction word from the cache instruction word memory. If not, that is, when an instruction miss occurs, the required instruction word is read out from the main memory through the bus interface device. Please refer to Figure 1. Those skilled in the art will know that the device and method of the conventional instruction cache is' When it is necessary to access the instruction word addressed by the CPU, it will first go to the cache tag memory 108, 109 whether it meets its requirements. The label of the required instruction word. The tags stored in the cache tag memories 108, 109 are the tags stored in the cache word memory 106 and the cache word memory 107. Then, by using the cache tag memories 108 and 109, the comparator 111 and the comparator 112 coupled to the cache tag memories 108 and 109 will cache the tags stored in the tag memories 108 and 109 and the signals output by the programmable counter 115 (this The signal includes the label of the instruction word address required by the CPU). If they match, that is ... (Please read the precautions on the back before filling in this page) Order --------- Line · This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 538374 7 863twf. Doc / 006 A7 137 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperatives 5. Test instructions (1) When the instruction is hit, the comparator 111 will output an instruction hit signal, so that the multiplexer 104 will use the The required instruction word is stored in the cache instruction word memory, and then the required instruction word is output. If they do not match, that is, the instruction hit fails, the CPU requests the main memory through the bus interface unit 101 (buffer interface unit, BIU), and waits for the main memory to respond to the bus interface unit 101. It is then temporarily stored in the instruction read buffer 102 (instruction read buffer). And when the bus interface device 101 responds to a command word to the command read buffer 102, a command word originally stored in the command read buffer 102 is written into the cache command word memory 106 or 107. Please refer to FIG. 2. The conventional instruction read buffer 102 is equivalent to a line in memory, which can store 4 instruction words (WO, Wl, W2, W3), that is, once. Four instruction words are stored at the same time. The multiplexer 103 is controlled by the programmable counter 115 at the input of the multiplexer in and the write indicator signal. When the next instruction word is temporarily stored in the instruction read buffer 102, the multiplexer The 103 control is written to the cache instruction word memory 106 or the cache instruction word memory 107 one instruction word at a time, and the required instruction word is transferred from the cache instruction word by the multiplexer 104. The memory 106 or the cache word memory 107 is taken out for use by the CPU. Therefore, when the instruction hit fails, the CPU must spend more time to complete the action of assigning the required instruction word. The time required is approximately: the time required by the CPU to make a request to the main memory + the time required for the bus interface device to wait for a response + the time required to write the cache instruction word to record the billion bytes + the instruction word required to be assigned The time required. The paper wattage is in accordance with China National Standard (CNS) A4 (210 X 297 public love) --------------------- Order -------- -Line (please read the notes on the back before filling this page) 538374
經濟部智慧財產局員工消費合作社印製 其中’對主記憶體提出要求所需的時間約爲1〜2個時 顧週期’而匯流排界面裝置等待回應所需要的時間卻需要 十幾個時脈週期。且當匯流排界面裝置等待回應時，快取 指令字記憶體卻是閒置的狀態，因此在管理記憶體上，便 顯得沒有效率。 •有鑑於此’本發明提出一種使用指令讀取緩衝器之快 取裝置及其使用方法，可以增加指令命中的機率，且當匯 流排界面裝置等待回應時做指令字寫入的動作。 本發明藉由增加指令讀取緩衝器之輸出路徑、計數器 以及比較器，來達到更有效率地存取快取指令字記憶體中 之指令字。 本發明提供一種使用指令讀取緩衝器之指令快取裝 置’包括指令命中分析單元、指令讀取緩衝器、第一快取 指令字記憶體、第二快取指令字記憶體、第一多工器以及 第二多工器。其中，指令命中分析單元接收可程式計數器 輸出信號，經與複數個標籤比較分析後輸出包括指令讀取 緩衝器指令命中信號及第一快取指令字記憶體指令命中信 號。指令讀取緩衝器暫存匯流排界面裝置所回應之指令 字。第一快取指令字記憶體儲存匯流排所回應之指令字。 第二快取指令字記憶體儲存匯流排所回應之指令字。第一 多工器接收指令讀取緩衝器之複數個指令字輸出信號，且 經由根據指令讀取緩衝器指令命中信號及第一快取指令字 記億體指令命中信號之控制信號所控制，將指令讀取緩衝 器中包括指令字之一條指令線寫入第一快取指令字記憶體 本紙張&度適用中國國家標準（CNS)A4規格（210 x 297公釐） --------------^0--------訂---------^ IA-W1 (請先閱讀背面之注意事項再填寫本頁) A7 五 蛵濟部智慧財產局員工消費合作钍印製 538374 ' ^63twf.doc / 006 #明說明（（p 域是將指令線寫入第二快取指令字記憶體中或是將指令讀 项緩衝器中之指令字輸出至第二多工器中。而第二多工器 貝0接收並根據指令讀取緩衝器指令命中信號及第二快取指 令字記憶體指令命中信號，從第一快取指令字記憶體或是 箄二快取指令字記憶體或是指令讀取暫存器中讀出預期之 指令字。 本發明另外提出一種使用指令讀取緩衝器之指令快取 鍵置，包括：指令命中分析單元、指令讀取緩衝器、至少 一快取指令字記憶體、第一多工器以及第二多工器。其中’ 箱令命中分析單元接收可程式計數器輸出信號，經與複數 個標籤比較分析後輸出包括指令讀取緩衝器指令命中信號 及第一快取指令字記憶體指令命中信號。指令讀取緩衝器 暫存匯流排界面裝置所回應之指令字。快取指令字記憶體 儒存匯流排所回應之指令字。第一多工器接收指令讀取緩 衝器之複數個指令字輸出信號，且經由根據指令讀取緩衝 器指令命中信號及第一快取指令字記憶體指令命中信號之 控制信號所控制，將指令讀取緩衝器中包括指令字之一條 指令線寫入快取指令字記憶體或是將指令讀取緩衝器中2 指令字輸出至一第二多工器中。而第二多工器則接收並根 據指令讀取緩衝器指令命中信號及第一快取指令字記憶體 指令命中信號’從快取指令字記憶體或是指令讀取緩衝器 中讀出預期之指令字。 本發明更提出一種使用讀取暫存器之指令1夬取方法， 用於指令快取系統。此方法包括以下步驟：直接由指令快 — — — — — — — — — ϋ I I · ϋ I I n n n n I I. I ϋ ϋ I I I I 0^^ · (請先閱讀背面之注意事項再填寫本頁) 本乡氏張&後適用中國國家標準（CNS)A4規格（21〇χ 297公釐） 538374 A7 7 863twf.doc: / 0〇 B7 經濟部智慧財產局員工消費合作社印製 五、专务明說明（^) 取系統之指令讀取緩衝器，將第一指令字輸出。當指令快 取系統發生指令命中失敗，且在等待一匯流排界面裝置回 應一第二指令字時，同時將指令讀取緩衝器中包括第一指 令字之一條指令線寫入指令快取系統之快取指令字記憶體 中。 •綜上所述，本發明以增加新的路徑、計數器以及比較 器來達到，當讀取時，指令讀取緩衝器可作爲指令字來源； 當指令讀取緩衝器等待匯流排界面裝置回應時，可將存於 本身之指令字寫入快取指令字記憶體中。如此一來’增加 少數的元件，即可以達到可以增加指令命中機率以及增加 快取裝置的工作效率。 廣ς點能吏明 爲讓本發明之上述和其他目的、特徵、和1#"、、羊細 顯易懂，下文特舉較佳實施例，並配合所附_式 說明如下： 圖式之簡單說明： 第1圖繪示的是習知快取裝置的部份竃路圖’虑_ ; >、、宙磁關讲 第2圖繪示的是習知指令讀取緩衝器之^ 乂及 — 就4重使用 第3圖繪示的是根據本發明之較佳實施例& 指令讀取緩衝器之快取裝置之部分電路_。 £號說明 1Gi :匯流排界面裝置 1G2 :指令讀取緩衝器 103，104，117 :多工器The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints out that 'the time required to make a request for the main memory is about 1 to 2 clock cycles', and the time required for the bus interface device to wait for a response requires more than ten clocks cycle. And when the bus interface device is waiting for a response, the cached word memory is idle, so it appears inefficient to manage the memory. • In view of this, the present invention proposes a cache device using an instruction read buffer and a method of using the same, which can increase the probability of instruction hits, and write an instruction word when the bus interface device is waiting for a response. The present invention achieves more efficient access to the instruction words in the cache instruction word memory by increasing the output path of the instruction read buffer, the counter, and the comparator. The invention provides an instruction cache device using an instruction read buffer, which includes an instruction hit analysis unit, an instruction read buffer, a first cached instruction word memory, a second cached instruction word memory, and a first multiplexer. And a second multiplexer. The instruction hit analysis unit receives a programmable counter output signal, and after comparing and analyzing with a plurality of tags, the output includes an instruction read buffer instruction hit signal and a first cache instruction word memory instruction hit signal. The instruction read buffer temporarily stores the instruction words responded by the bus interface device. The first cached word memory stores the words returned by the bus. The second cached word memory stores the words returned by the bus. The first multiplexer receives a plurality of instruction word output signals of the instruction read buffer, and is controlled by the control signal of the instruction read buffer instruction hit signal and the first cache instruction word record billion instruction hit signal. The instruction read buffer includes one instruction line to write to the first cache instruction word memory. The paper & degree applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) ------ -------- ^ 0 -------- Order --------- ^ IA-W1 (Please read the notes on the back before filling this page) A7 Ministry of Economic Affairs Intellectual Property Bureau employee consumer cooperation print 538374 '^ 63twf.doc / 006 #Description ((p field is the instruction to write the instruction line to the second cache instruction word memory or the instruction read buffer The word is output to the second multiplexer. The second multiplexer receives and reads the buffer instruction hit signal and the second cache instruction word memory instruction hit signal according to the instruction, and memorizes from the first cache instruction word. The expected instruction word is read from the bank or the second cache instruction word memory or the instruction reading register. An instruction cache key using an instruction read buffer includes an instruction hit analysis unit, an instruction read buffer, at least one cached instruction word memory, a first multiplexer, and a second multiplexer. Among them, ' The box order hit analysis unit receives a programmable counter output signal, and after comparing and analyzing with a plurality of tags, the output includes an instruction read buffer instruction hit signal and a first cache instruction word memory instruction hit signal. The instruction read buffer is temporarily stored The command word responded by the bus interface device. The cache word memory stores the command word responded by the bus. The first multiplexer receives a plurality of command word output signals from the command read buffer, and reads the instructions according to the command. Fetch buffer instruction hit signal and control signal of first cache instruction word memory instruction hit signal, write one instruction line including instruction word in instruction read buffer to cache instruction word memory or write instruction The 2 instruction words in the read buffer are output to a second multiplexer. The second multiplexer receives and reads the instruction hit from the read buffer according to the instruction Signal and the first cached instruction word memory instruction hit signal 'reads the expected instruction word from the cached instruction word memory or the instruction read buffer. The present invention further provides an instruction 1 using a read register. The fetch method is used for the instruction cache system. This method includes the following steps: Directly by the instruction fast — — — — — — — — — — ϋ II · ϋ II nnnn I I. I ϋ ϋ IIII 0 ^^ · (Please first Read the notes on the reverse side and fill out this page) After the township Zhang & applied the Chinese National Standard (CNS) A4 specification (21〇χ 297 mm) 538374 A7 7 863twf.doc: / 0〇B7 Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the employee's consumer cooperative 5. Special instructions (^) Take the system's instruction read buffer, and output the first instruction word. When an instruction cache failure occurs in the instruction cache system, and while waiting for a second instruction word from a bus interface device, an instruction line including the first instruction word in the instruction read buffer is written into the instruction cache system. Cached word memory. • In summary, the present invention is achieved by adding new paths, counters, and comparators. When reading, the instruction read buffer can be used as the source of the instruction word; when the instruction read buffer is waiting for a response from the bus interface device , The instruction word stored in itself can be written into the cache instruction word memory. In this way, 'adding a few components can increase the probability of hitting the instruction and increase the working efficiency of the cache device. In order to make the above and other objects, features, and 1 # " of the present invention clear and easy to understand, the following is a description of the preferred embodiment and the accompanying formulas as follows: Brief description: Figure 1 shows a part of the conventional cache device's road map 'Consider'; >, and Zhou Magnetic Relations. Figure 2 shows the conventional instruction read buffer ^乂 — A part of the circuit of the cache device of the instruction read buffer according to the preferred embodiment of the present invention is shown in FIG. Description of pound sign 1Gi: bus interface device 1G2: instruction read buffer 103, 104, 117: multiplexer
本紙張尺度適嗣Γ國國家標準（CNS)A4 297公釐） (請先閱讀背面之注意事項再填寫本頁) 4 訂· •線' 經濟部智慧財產局員工消費合作社印製 538374 7 863twf.doc/006 五、令合明說明（& ) 界面裝置101取得第二要求指令字且輸入至指令讀取緩衝 器1Q2時，才將第一要求指令字寫入快取指令字記憶體1〇6 或1Q7(本發明亦非使用習知寫入快取指令字記憶體1〇6， 107之方式）。也就是，本發明可以使得寫入快取指令字記 〃噫體106或107的動作可與指令讀取緩衝器102等待匯流 担有界面裝置101回應的時間重疊，不需額外多餘的時間。 換句話說，根據本發明，寫入快取指令字記憶體的時間可 省去。 於上述中，爲配合其操作模式，多工器104受控於指 令命中分析單元120。而指令命中分析單元12〇包括第一標 籤決定單元其又包括串接的一快取標籤記憶體108及一比 車父益111。第一標數決定單兀其又包括串接的一快取標籤記 憶、體109及一比較器112。一指令讀取緩衝器決定單元其又 包括串接的一 IRB-可程式計數器（programmable counter，PC) 暫存器110及一比較器113。一可程式計數器115輸出信號 給比較器1 11，Π2，及113。比較器111的輸出信號爲第 一快取指令字記憶體指令命中信號124，同時輸入多工器 104與或閘114。比較器112的輸出信號爲第二快取指令字 記憶體指令命中信號126直接輸出給或閘114。比較器113 的輸出信號爲指令讀取緩衝器指令命中信號122，其同時輸 入給多工器104與或閘114。 當CPU對記憶體提出一個指令字請求的時候，會先檢 查快取標籤記憶體108，109中是否有與所需指令字相符之 標籤，即相當於在快取指令字記憶體106，107中是否存有 10 本紙張尺度適用中國國家標準（CNSM4規格（210 x 297公釐） --丨丨丨丨丨丨丨丨丨丨· I丨丨丨丨丨丨訂·丨！丨丨丨- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 538374 7863twf. doc / 006 五、考务明說明（(D) 以直接讀取，而不是先寫入快取指令字記憶體106或快取指 呤字記億體107之後再讀取。 如果均不符合時或沒有時，CPU透過匯流排界面裝置 101對主記憶體提出一個請求以存取主記憶體中第一要求 指令字後，等待匯流排界面裝置101回應第一要求指令字至 指令讀取緩衝區102中。匯流排界面裝置101將回應之第一 要求指令字暫存在指令讀取緩衝器102中時，此第一要求指 令字亦同時經由多工器103直接至多工器1〇4以輸出供CPU 讀取，但延後寫入快取指令字記憶體106，107。當下一次 需要存取CPU所定址之第二要求指令字時，快取標籤記憶 體1〇8或是彳央取標籤記憶體109將暫存於其中之標籤，再藉 由比較器111，112分別比較快取標籤記憶體108、1〇9是否 有符合可程式計數器11 5所輸出包括第二要求指令字標籤 之信號以及IRB-PC暫存器1 10與可程式計數器η 5藉由比較 器113去比較同週期中，指令讀取緩衝器102中是否有所需 之第二要求指令字。 如果快取指令字記憶體106或是快取指令字記憶體107 中或是指令讀取緩衝器102中，有符合第二要求指令字標籤 之第二要求指令字時，或是指令讀取緩衝器102暫存有第二 要求指令字時，則由其所儲存或暫存之裝置中讀取。 如果快取指令字記憶體106或是快取指令字記憶體1〇7 指令讀取緩衝器102中，沒有符合第二要求指令字標籤之第 二要求指令字時，同時指令讀取緩衝器102中也沒有所需之 弟一要求指令子時，CPU再透過匯流排界面裝置1 〇1對主言己 12 -------------i _ I 丨丨丨丨訂-------I JAWTi (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 137 538374 7863twf.doc / 006 五、考蚤明說明（I') 1意體提出一個請求，存取主記憶體中之第二要求指令字 後，等待匯流排界面裝置101回應第二要求指令字至指令讀 耳又緩衝器102後，直接由指令讀取緩衝器1〇2中透過多工器 103輸入至多工器104以輸出供CPU讀取，且在匯流排界面 裝置101等待第二要求指令字回應時，將在指令讀取緩衝器 102中包括第一指令字之整條線寫入快取指令字記憶體106 或是快取指令字記憶體107。對照第2圖，其中指令讀取緩 衝器1Q2作寫入快取指令字記憶體106或是快取指令字記憶 懂1〇7時，暫存於指令讀取緩衝器102的四個指令字（包栝 第一指令字）可以任何順序的方式寫入。 因此，在作指令快取之讀取動作的時候，指令讀取緩 衝器可以當作是快取指令字記憶體中的一條線，而增加了 指令命中的機率，且在下一次的指令命中失敗並在匯流排 界面裝置等待所需指令字的同時，寫入之前暫存於指令讀 取緩衝器中包括上次所需指令字之整條線，也就是利用將 原本需要匯流排界面裝置等待回應的時間加上寫入快取指 呤字記憶體的時間覆蓋在一起，而節省了此因爲指令命中 失敗後所浪費的時間，進而改善了此快取指令字記憶體在 使用上的效能。 此外，熟悉此技藝者可知，本發明實施例及其使用方 法亦可應用於具有數個快取指令字記憶體之快取裝置。 綜上所述，本發明以增加指令讀取緩衝器之輸出路徑 並加上兩個計數器的比較作爲其中之控制，使得指令讀取 緩衝器在讀取的時候作爲指令字之來源，增加指令命中的 本紙張又度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------« (請先閱讀背面之注意事項再填寫本頁) 訂---------線· 經濟部智慧財產局員工消費合作社印製 538374 A7 B7 7 863twf.doc/006 五、号务明說明（/1) 機率；在匯流排界面裝置等待回應的時候，指令讀取緩衝 器卻可以作寫入的動作，減少浪費的時間。故本發明只需 要增加少數的元件，便可以達到增加指令命中機率，減少 1决取裝置在指令命中失敗時，所需要多浪費的時間，進而 提升整個裝置運作的效率。 ‘雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 芣口範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 -------------€--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐）The size of this paper is in accordance with National Standard (CNS) A4 297 mm) (Please read the notes on the back before filling out this page) 4 Orders • Lines Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs 538374 7 863twf. doc / 006 V. & Description The interface device 101 obtains the second required instruction word and enters it into the instruction read buffer 1Q2, and then writes the first required instruction word into the cache instruction word memory 1〇 6 or 1Q7 (the present invention also does not use the conventional method of writing cache instruction word memory 106, 107). That is, the present invention can make the action of writing the cache instruction word body 106 or 107 overlap with the time that the instruction read buffer 102 waits for the response from the confluence interface device 101 without additional extra time. In other words, according to the present invention, the time for writing the cache word memory can be omitted. In the above, in accordance with its operation mode, the multiplexer 104 is controlled by the instruction hit analysis unit 120. The instruction hit analysis unit 120 includes a first tag determination unit, which further includes a cache tag memory 108 and a car driver benefit 111 connected in series. The first scalar decision unit includes a cache tag memory, a body 109, and a comparator 112 connected in series. An instruction read buffer determination unit further includes an IRB-programmable counter (PC) register 110 and a comparator 113 connected in series. A programmable counter 115 outputs signals to the comparators 11, 11, 2 and 113. The output signal of the comparator 111 is the first cache instruction word memory instruction hit signal 124, and is simultaneously input to the multiplexer 104 and the OR gate 114. The output signal of the comparator 112 is the second cache instruction word and the memory instruction hit signal 126 is directly output to the OR gate 114. The output signal of the comparator 113 is the instruction read buffer instruction hit signal 122, which is simultaneously input to the multiplexer 104 and the OR gate 114. When the CPU makes an instruction word request to the memory, it will first check whether the cache tag memory 108, 109 has a tag that matches the required instruction word, which is equivalent to the cache instruction word memory 106, 107. Whether there are 10 paper sizes applicable to the Chinese national standard (CNSM4 specification (210 x 297 mm)-丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 Ordering! 丨 丨 丨 --- ( Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 538374 7863twf. Doc / 006 V. Exam Instructions ((D) Read directly, not write to the cache first The instruction word memory 106 or the cached word memory 100 million body 107 is read again. If neither match or not, the CPU makes a request to the main memory through the bus interface device 101 to access the main memory. After the first required instruction word, wait for the bus interface device 101 to respond to the first required instruction word to the instruction reading buffer 102. The bus interface device 101 temporarily stores the first required instruction word in the response into the instruction reading buffer 102. This first requirement The command word also goes directly to the multiplexer 104 through the multiplexer 103 to output for the CPU to read, but the write to the cache instruction word memory 106, 107 is postponed. The second request for accessing the address set by the CPU is required next time In the command word, the cache tag memory 108 or the central tag memory 109 will temporarily store the tags therein, and then compare whether the cache tag memories 108 and 109 are compared with the comparators 111 and 112, respectively. There is a signal that meets the programmable counter 11 5 including the second required instruction word label and the IRB-PC register 1 10 and the programmable counter η 5 use the comparator 113 to compare the instruction read buffer 102 in the same cycle. Whether there is a required second required instruction word in the cache. If the cached instruction word memory 106 or the cached instruction word memory 107 or the instruction read buffer 102 has a When the second requested instruction word or the instruction read buffer 102 temporarily stores the second required instruction word, it is read from the device which is stored or temporarily stored. If the instruction word memory 106 or the cache is cached Instruction word memory 107 Instruction read buffer 102 When there is no second required instruction word that meets the second required instruction word label, and there is no required brother in the instruction read buffer 102 at the same time, the CPU uses the bus interface device 1 〇1 to make a speech 12 ------------- i _ I 丨 丨 丨 丨 Order ------- I JAWTi (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 Specification (210 X 297 mm) A7 137 538374 7863twf.doc / 006 V. Examination Instructions (I ') 1 The Italian body makes a request to access the second request instruction in the main memory After waiting for the word, wait for the bus interface device 101 to respond to the second request instruction word to the instruction ear reading buffer 102, and then directly input the instruction reading buffer 10 through the multiplexer 103 to the multiplexer 104 to output for the CPU Read, and when the bus interface device 101 waits for a second request command word response, the entire line including the first command word in the command read buffer 102 is written into the cache command word memory 106 or the cache Instruction word memory 107. Referring to FIG. 2, the instruction read buffer 1Q2 is used to write the cache instruction word memory 106 or the cache instruction word memory 107, and the four instruction words temporarily stored in the instruction read buffer 102 ( Including the first instruction word) can be written in any order. Therefore, when performing a read operation of the instruction cache, the instruction read buffer can be regarded as a line in the cache of the instruction word memory, which increases the probability of an instruction hit, and the next instruction hit fails and While the bus interface device is waiting for the required instruction word, the entire line temporarily stored in the instruction read buffer including the last required instruction word before writing is used, which means that the bus interface device that originally needed to wait for a response is used. The time plus the time to write the cached word memory is overlaid together, which saves the time wasted after the instruction hit fails, thereby improving the performance of the cached word memory. In addition, those skilled in the art will know that the embodiments of the present invention and the method of using the same can also be applied to a cache device having a plurality of cache instruction word memories. In summary, in the present invention, the output path of the instruction read buffer is increased and the comparison of the two counters is added as the control, so that the instruction read buffer is used as the source of the instruction word when reading, and the instruction hit is increased. This paper is again applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------- «(Please read the precautions on the back before filling this page) Order- -------- Line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 538374 A7 B7 7 863twf.doc / 006 V. Numbering instructions (/ 1) Probability; when the bus interface device is waiting for a response However, the instruction read buffer can be used for writing, reducing wasted time. Therefore, the present invention only needs to add a few components to increase the probability of instruction hits and reduce the wasteful time required by the decision device when the instruction hit fails, thereby improving the efficiency of the entire device operation. 'Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the attached patent application. ------------- € -------- Order --------- Line (Please read the notes on the back before filling out this page) Intellectual Property of the Ministry of Economic Affairs The paper size printed by the Bureau ’s Consumer Cooperative is applicable to China National Standard (CNS) A4 (210 x 297 mm)