TW536747B - Metal silicide manufacturing method - Google Patents

Abstract

A metal silicide manufacturing method is provided. First, entirely form a metal layer on the silicon substrate having gate and source/drain, and there are spacers on the gate sidewalls. Second, proceed the first thermal process to let the metal react with silicon of the gate, source and drain surfaces to form metal silicide. Third, remove the unreacted metal layer and the spacers. Fourth, proceed an ion implantation step and then proceed the second thermal process.

Description

536747 V. Description of the invention (1) Field of the invention: The present invention relates to a method of semiconductor manufacturing, especially to self-aligned silicide;

The manufacturing method of Salicide can effectively avoid the problem of junction leakage caused by excessive consumption of the silicon substrate. r Related technical description: In semiconductor technology, a metal-oxide-semiconductor (MOS) transistor is composed of three electrodes: a gate, a source, and a drain. The structure, of which M0S is the main body of the gate structure. The early system was composed of three layers of materials, such as a metal layer, silicon dioxide (with 02), and a silicon-based (siHcON-based substrate). However, due to the poor adhesion of most metals to the dioxide (a (jhesi〇n)), polycrystalline silicon (polysi 1), which has better adhesion to the dioxide, was proposed to replace the metal layer. However, the use of polycrystalline silicon has a problem of too high resistance. Even if polycrystalline silicon is doped, its resistance is still too high. It is not suitable for replacing the metal layer of MOS. Therefore, those familiar with this memory will propose a solution. That is, another layer of metal salicide (thickness of polysilicon) is added on the surface of the polycrystalline silicon, and the conductive layer is formed by using the metal silicide with better conductivity and the polycrystalline silicon. With the integration of the device (Integrity) As the size of the M0S element increases, the resistance of the drain / source will also gradually increase to the same level as its channel. In order to reduce the sheet resistance of the drain / source, Resistance) and ensure that the metal is "shallow" between M0s

Page 4 536747 V. Description of the invention (2) "Shallow Junction" & even "ultra shallow junction (ultra shaow junction)" is complete, and it is widely used in applications called self-aligned metal silicide process. Used in VLSI process below 0 · 5 // m. This process is generally referred to as the Salicide process. In the Sal i cide process, metals with good oxygen-getting ability (Oxygen Getting) are usually used, such as: titanium (Ti), platinum (Pt), cobalt (Co), nickel (Ni), etc., at an appropriate temperature It is very easy to form a compound with low resistance due to interdiffusion with Shi Xi (Si). Therefore, a good ohmic contact can be formed at the interface between the metal and Shi Xi. ° 1 A-1E It is a cross-sectional view showing the process of the conventional Salic ide process. As shown in Figure 1A, a basic MOS architecture is shown, in which 10 represents a semiconductor substrate, and a polycrystalline silicon gate structure is defined on this substrate 丨 2 (丨 丨 is the gate oxide layer), the drain / source 14, and the interval And a field oxide layer 22 (FOX). First, a hydrofluoric acid-based solvent is used to remove all possible contaminations on the Mos structure, and then a metal layer 30 is deposited on the Mos structure, as shown in Figure 1B. Next, in an environment with an ambient temperature of 65-7000c and nitrogen (N2), the first rapid heating process (RTP) is used to perform annealing. The metal layer 30 will It will react with the polycrystalline silicon on the gate 12 and the single crystal silicon (CrystalUne SiHon on the gate 14) to form the metal silicide 31, while the metal on the spacer 20 and the field oxide layer 22 remains as it is. Participate in the reaction, as shown in Figure 丨 c. In the next step, a selective wet etching step is used to remove the aforementioned unreacted silicon 30 and etch it. The result is shown in Figure 1D. Then, depending on the needs of the actual application, under 800 C still temperature, air pressure of 76〇mt〇rr and full environment

IH 0702-7476TWF (N); 90P127; Felicia.ptd Page 5 536747 V. Description of the invention (3) Speed: Tempering in the manufacturing process to 'make the aforementioned metal lithophyte 31-' historical 'phase transformation The phase 32 with lower resistance becomes the second one. In this way, the conventional SaHcide process is completed. Consumption: During the process, the silicon on the drain / source 14 will be reversed = winter metal / xide 31. Taking a metal inscription (㈤ as an example, the reaction is calculated as 彳 β ^ 〇Sl2, which is pushed to. ° through material characteristics and conventional techniques. 'The material thickness consumption ratio is approximately Co: Si: CoSi2 = 1: degree 3 6〇 The S of 3 people is 5. That is, the mother must form a thickness of 35 0 A and the thickness of 00 ^ 2 must be consumed. At this time, there will be a "and potential 3 conductor W" with a thickness of about 0.04 microns (" m). Loss of personnel, so 'As the semiconductor line width shrinks, the field + conductor I process technology evolves to 0 1 3 _, after the sa 1 ici de process is familiar, it is combined with the problem of leakage. Occurrence, as shown in Fig. 2 r / j No. In order to solve the above problem, the main purpose of the present invention is to fluorinate the material, which can be applied to semiconductors with a high degree of accumulation, to The need for shallow junctions. Summary of the invention: The purpose of the present invention is to provide a method for manufacturing a metal silicide ^ j ^ s yu ^ a LV The problem and skin of joint leakage: To achieve the above-mentioned object, the present invention proposes a method for manufacturing a metal silicide W square f. The steps of this method are mainly Comprising: stoneware / II:,: Maersk end, 'the above-mentioned bottom surface is formed with a silicon based - and gate - source > ... In the above-described gate having a sidewall spacer; Comprehensive formed

536747 V. Description of the invention (4) The metal layer is on the surface of the gate, the spacer and the source / drain, and a first heat treatment process is performed to make the metal layer and the gate and the source / drain The silicon on the electrode surface reacts to form a metal silicide; remove the part of the metal layer and the spacer that are not involved in the reaction; introduce a silicon ion into the drain / source surface; perform a second heat treatment procedure; and remove the Part of the above-mentioned metal layer participating in the reaction. • As mentioned above, the first and second heat treatments are rapid heating and tempering (RTP), and the temperature range is, for example, 600 to 800 cc. And the above

The introduction of silicon-containing ions can be accomplished by an ion implantation method to provide an additional silicon-containing ion source to reduce the consumption of silicon in the substrate. Embodiments: The following is a description of an embodiment according to the present invention with reference to the process cross-sectional views of FIGS. 3A to 3F and the flowchart of FIG. 4. First, in step S600, referring to FIG. 3A, the basic structure of a MOS is displayed. Among them, reference numeral 100 is a silicon substrate, and a gate electrode 120, a source / drain electrode 14 and a field oxide 220 have been formed on the surface of the silicon substrate 100. The material of the gate electrode 120 is, for example, polycrystalline silicon. Preferably, a gate oxide layer is formed between the polycrystalline silicon gate 120 and the substrate 100, and the upper source / drain 140 is formed by an appropriate doping process. In addition, a spacer 200 is provided on the sidewall of the upper electrode 120, and the material is, for example, an oxide. A Next, in step S602, for example, a full-scale formation of sputtering is performed by a DC plasma method—a metal layer 300 is formed on the MOS structure, that is, the metal layer 300 covers the gate electrode 12. , The spacer 200, the source / drain 140, and the surface of the field oxide 22o,

536747 Description of the invention (5) Among materials such as nickel and platinum, and the material of the metal layer 300 is, for example, one of titanium and cobalt ', as shown in FIG. 3B. king. Next: In step S604, please refer to FIG. 3C, and execute a private sequence in the first thermal place 'preferably using a rapid heating process (RTP) to perform a heat treatment at a temperature of about 6 00-800 0 =' so that the above-mentioned metal layer 3 〇〇Reacts with the gate 12 and the silicon on the surface of the source and electrode 140 to form a metal silicide 310, and covers the field oxide 22 and the metal above the spacer 200. Part 0 〇 did not participate in the reaction and remained intact. • In step s 6 06 after J, 'implement an appropriate selective surname engraving procedure, such as the wet etching method, to remove the 300 metal blades of the above-mentioned metal layer that have not participated in the reaction' and the above-mentioned spacers 200, such as Figure 3D. / 无极 然 / 面 ^ In Step 8, it is to introduce all ions into the above source 1 = shown where '㈣ 子 can be imported using the-ion implantation program, order, plus: =) Figure into the second heat treatment for Γ The upper surface (ίTP) is driven at a temperature of about 600 to 800 ° C. The upper metal silicide 3 1 0 causes a phase change, and the phase has a lower resistance value of 32 °. Branch formation — Although the present invention is disclosed in the preferred embodiment as above, the scope of the present invention is lacking. Any 孰 f = /, is not within the spirit and scope defined by U, when; it should be regarded as not departing from the scope of protection of the present invention. Attachment ::: = 2 and: Decoration 'Therefore, the invention defined by the Jiaming Patent Rail shall prevail.

In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible under the simple description of the drawings, Wen Wen cites a preferred embodiment in conjunction with the accompanying drawings for detailed description, as shown in FIGS. 1A to 1E. The diagram is a cross-section of a conventional metal silicide process. The second diagram is a joint leakage problem that may be encountered in the conventional metal silicide process. Figures 3A to 3F are cross-sectional views showing the process of the metal silicide according to the present invention. Fig. 4 is a flow chart showing the process of the metal silicide according to the present invention. Explanation of symbols: 10 ~ 100 ~ semiconductor substrate; 11, 110 ~ gate oxide layer; 12, 120 ~ polycrystalline seconds; 14, 140 ~ non-polar / source; 20 >200-spacer; 22 > 220 ~ field oxide layer; 30 '300 ~ metal layer; 30a, 30a ~ are gold participating in the reaction; 31 ~ 310 ~ metal silicide; 32 > 320 ~ metal with new phase 700 ^ 900 production ~ heating Procedure; 800 ~ ion implantation procedure.

〇702-7476TWF (N)-90P127; Felicia.ptd page 9

Claims (1)

536747 6. Application scope \ A method for manufacturing a metal silicide, comprising: a gate and a drain to provide a silicon substrate, the surface of the silicon substrate forming a pole / source, wherein the side wall of the gate has a spacer; compliant formation A metal layer is on the surface of the gate, source / drain; the spacer and the t, f, and @th heat treatment procedures make the metal layer react with silicon on the surface of the gate and the source / source Forming a metal silicide; removing the metal layer and the spacer that are not involved in the reaction; introducing a stone-containing ion on the surface of the drain / source; and performing a second heat treatment procedure. Wherein the above 〇 among the above among the above among the above among the above among the above 2 · The manufacturing method as described in item 1 of the scope of patent application: The metal layer is composed of one of titanium, cobalt, nickel, and platinum 3 · as the patent is applied for In the manufacturing method described in the first item of the scope, the first heat treatment is a rapid heating and tempering process (RTP). 4 · The manufacturing method described in item 1 of Shenyan's patent scope, the second heat treatment is the rapid heating and tempering process (RTP). 5 · The manufacturing method described in item 1 of the scope of patent application, the silicon-containing ions are introduced by ion implantation. 6 · The manufacturing method described in item 1 of the scope of patent application, wherein the metal layer is formed by a sputtering method. 7. The manufacturing method as described in item 6 of the scope of the patent application, wherein the above-mentioned sputtering method is performed by a direct current (D C p 1 a s m a) method. 8. The manufacturing method according to item 1 of the scope of patent application, wherein the removal of the above metal layer is performed by a wet-etching method. 0702-74761 ^ (N): 90P127; Felicia.ptd No. 10 Buy 536747 Apply for a patent scope 9 As described in the patent application scope, the surface of the substrate has a gate oxide scale method, wherein the above 10 · Manufacture of a metal silicide_, under the gate. Provide a silicon substrate, the above silicon substrate table includes ... a pole / source, wherein the gate side wall has, a shape is formed-the gate and a drain are formed comprehensively-a metal layer is formed on the gate and the spacer Electrode / source surface; the spacer and the above-mentioned first rapid heating and tempering process, the gate and the above-mentioned drain / diode are reacted from the metal layer of A * on the silicon surface with the silicon on the surface of the source And the formation of metal visits to foreign countries to remove the non-reactive part of the above-mentioned metal layer part of the fish species, the implementation of-Shixian ion implantation program n "spacers; a second rapid heating and tempering process. 11 · The manufacturing method described in item 10 of the scope of the patent application consists of one of titanium, cobalt, and nickel. 1 2 · The manufacturing method described in item 10 of the scope of patent application The above metal layer is formed by a sputtering method. 1 3 · The manufacturing method according to item 12 of the scope of application for a patent, wherein the above sputtering method is performed by a direct current plasma (DC pi asma) method. 1 4 · 如Manufacturing method described in the scope of patent application No. 10 Wherein the metal layer is to be based in addition to using a wet etching method. 0702-7476TWF (N); 90P127; Felicia.ptd 11th tribute