TW536685B - Group rename allocation for multiple register instructions - Google Patents

Abstract

A microprocessor and a method of processing instructions therein are disclosed. Initially, the microprocessor determines whether a dispatched instruction requires multiple register allocations. If the instruction requires only a single register allocation, the microprocessor allocates a register for the instruction in a first portion of a physical register pool. If the instruction requires multiple register allocations, a set of physical registers in a second portion of the register pool are allocated as a block after determining that the second portion is available. In one embodiment, the block allocation is performed only if the instruction requiring multiple register allocations is an eligible instruction, such as a load multiple word (LMW) instruction in an instruction set such as the PowerPC(R) instruction set. The set of registers that are block allocated may correspond to a fixed set of architected registers to simplify the allocation logic. In this embodiment, the registers allocated in response to a complex instruction are independent of the architected registers affected by the instruction. If the architected registers affected by the instruction exceed the number of registers in the second portion of the register pool, a portion of the registers affected by the instruction may be allocated to the first portion of the register pool. The portion of the physical register pool selected for block assignments may be moved following a block allocation.

Description

536685 A7 B7 V. Description of the invention (1) Background of the invention 1. Field of the invention The present invention is generally related to the field of microprocessors, especially with a register allocation mechanism (can be customized to simultaneously allocate registers to multiple temporary registers Register instructions). 2. Relevant technical records In the field of microprocessor architecture, the rename register is widely used to help out-of-order and theoretically executed instructions. In a register renaming methodology, this is called the table mapping register renaming. When needed, the registers from the physical register pool will be allocated to structured registers (visible in the program's Register). A comparison table is used to record the association between each structured register and its corresponding physical register. When the instruction requires a specific structured register, the structured register is allocated to the physical register pool. One of the registers in the register and records this allocation in the lookup table. For example, an instruction to load the structured register R5 from memory would cause a physical register to be allocated to R5. If the seventh entity register is allocated, the R5 position in the comparison table will indicate that R5 is currently allocated to the seventh entity register. When the content from the memory is taken out, the data will be stored in the physical register 7. If the next instruction updates the contents of R5, logically R5 will be allocated to the new physical register and update the contents of the lookup table. The contents of the lookup table are subject to change at any time to reflect the current register configuration. In addition, the registers in the physical register file can be committed to a specific structured register, allocated or available. Therefore, complex logic is usually required to determine which physical register is available for allocation, and to choose one when issuing an order. -4- This paper size applies to the Chinese National Standard (CNS) A4 specification (210X 297 mm)

Line 536685 A7 B7 V. Description of the invention (2) Register for allocation. The complexity of the allocation logic is limited to the number of scratchpads that can be allocated within the ring. Early-Cycle In most microprocessor instruction sets, most instructions only affect the contents of the registers. In this case, the instructions issued in the -loop = less than the number of registers that must be allocated. However, in some instruction sets:-Instructions (referred to herein as complex instructions) can affect multiple scratchpads: This requires multiple scratchpad allocations. If you assign logical processing to the coercive factor: the processor may not be able to compete in a single cycle with the extra registers required for complex instructions, and must issue less than the maximum number of cycles in which two heterogeneous instructions are issued The instruction ^ helps to maximize the number of instructions issued per cycle, because it simplifies the allocation processing of complex instructions: the most instructions are issued in each cycle. The outline of the invention of Li Li is published here-a microprocessor that processes instructions and the instructions that determine whether multiple registers need to be allocated are divided into two: If the register is allocated, the microprocessor will store the physical register pool. : A register in ^ is assigned to this instruction. If the instruction requires multiple; -ϋΓ ′ will be implemented after the first part of the 11th pool of the shirt is available: two = real :: The memory is configured as a block. In a specific example + 1 there is "the instruction to be allocated by multiple registers is suitable for the execution of the block allocation, such as the instruction set (such as PowerPC® instruction ^ internal multi-character load (LMW) Instructions. Block allocation register set ° to a fixed set of structured registers to simplify the allocation logic. _5 X297 ^ i) 3 V. Description of the invention (in: having :: in the embodiment 'assigned for The complex response refers to the structured register that is affected by the text deduction order. The Roussen temporary storage register exceeds the register ice Λ # and g 又 the structure of the impact of the structure is affected by the instruction m # 轻 & & I ^ σ number 1, then part of the internal. Select the heart Si to move to the physical register assigned by the Tiancheng block in the-part of the register pool. Brief description of the formula _ 'The present invention will have a comprehensive understanding of the following detailed description of the present invention and other objects and advantages of the present invention with reference to the drawings, in which: Figure 1 > Block diagram of a material processing system; Figure 2 is a general application for Figure 丨 the block diagram of the processor of the data processing system, Figure 3 is a detailed implementation of the present invention. Figure 4 is a block diagram showing the details of the problem unit. Figure 4 illustrates the physical register pool before the block register allocation as expected by the present invention; and Figure 5 illustrates the block register allocation according to a specific embodiment of the present invention. The physical register pool of the invention. The present invention can accept many modifications and other forms, so the specific embodiments are shown and explained in detail by examples in the drawings. However, I should understand that the drawings and details here The description does not intend to limit the invention to the specific form disclosed. On the contrary, the invention will cover all modifications, homogeneity, and changes within the scope and spirit of the invention as defined by the scope of the patent application. Detailed description of the embodiment -6- The paper size is suitable for financial standards (CNS) A4 specifications (210X297 male I) 536685 A7 _____ B7 V. Description of the invention (4) ~ " — Please refer to Figure 1, this figure Shows a specific embodiment of the data processing system 100 according to the present invention. The system 100-one or more central processing units (processors) 101a, 101b, 10c, etc. (collectively referred to as processing ίο!). In a specific embodiment, 'each processor 101 includes a reduced instruction set computer (RISC) microprocessor. Additional information about RISC processors is generally available in C. May et al. PowerPC Architecture: A Specification for a New Family of RISC Processors 5 (Morgan Kaufmann, 1994 second edition). The processor is coupled to the system memory 25 and to other components through the system bus 113. Read-only memory (ROM) 102 is coupled to the system bus 113 and contains a basic input / output system (BIOS), which is used to control certain basic functions of the system 100. FIG. 1 further illustrates a 1/0 adapter card 107 and a network adapter card 106 coupled to the system bus 113. I / O adapter card 107 can be a small computer system interface (SCSI) adapter card, and can communicate with hard disk 103 and / or tape storage device 105. The I / O adapter card 107, the hard disk 103, and the tape storage device 105 are collectively referred to as a main storage device 104 herein. The network adapter card 106 interconnects the bus 113 with an external network, and allows the data processing system 100 to communicate with other similar systems. The display monitor 136 is connected to the system bus 113 using a display adapter card 112. The adapter card may include a graphics adapter card and a video controller for improving the performance of a large number of graphics applications. In a specific embodiment, the adapter cards 107, 106, and 112 are connected to one or more I / O buses connected to the system bus 113 through an intermediate bus bridge (not shown). Suitable for connecting peripheral devices (such as 疋 hard disk controller, network adapter card and Figure-7- This paper size applies to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 536685 A7 B7 V. Description of the invention (5 ) -Shaped adapter card) I / 0 buses include peripheral component interface (P CI) buses in accordance with the PCI Local Bus Specification Version 2.2 published by PCI Special International Organization Hillsboro OR, and are incorporated herein by reference. The other input / output devices shown here are connected to the system bus 113 through the user interface adapter card 108 and the display adapter card 112. The keyboard 109, the mouse 110, and the speaker 111 are all connected to the bus 113 through a user interface adapter card 108 (which may include a Superl / O chip that integrates multiple device adapter cards into a single integrated circuit). For more information about such chips, please refer to the National Semiconductor's PC87338 / PC97338 ACPI 1.0 and PC98 / 99 Compliant Superl / O datasheets (November 1998) at www.national · com ο So as shown in Figure 1 The system 100 includes a processor 101 type processing device, a storage device including a system memory 250 and a main storage device 104, an input device such as a keyboard 109 and a mouse 110, and an output including a raid 111 and a display 136. Device. In a specific embodiment, part of the system memory 250 and the main storage device 104 collectively store an operating system, such as the IBM Corporation's AIX® operating system, to coordinate the functions of many components shown in FIG. For more information about the AIX operating system, refer to AIX Version 4.3 Technical Reference: Base Operating System and Extensions, Volumes 1 and 2 (order numbers SC23-4159 and SC23-4160), AIX Version 4.3 System User Guide, published by IBM Corporation. Communications and Networks (Order No. SC23-4 122) and AIX Version 4.3 System Usage Guide: Operating System and Devices (Order No. SC 23-4121) at www.ibm.com and incorporated herein by reference. -8-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) _ Packing

536685 A7 B7 V. Description of the Invention (6) Please refer to FIG. 2 at this time. Here, a simplified block diagram of a specific embodiment suitable for the processor 101 in the system 100 is presented. In the specific embodiment described here, the processor 101 includes an integrated circuit ultra-microprocessor made on a single-layer semiconductor substrate. The processor 101 includes many execution units, registers, buffers, memory, and other functional units, which will be explained in detail below. As shown in FIG. 2, the processor 101 is coupled to the system bus 113 through a bus interface unit (BIU) 212 and a processor bus 213 (such as a system bus 113 including an address, data, and control bus). The BIU 212 controls the conversion of information between the processor 101 and other devices (such as the system memory 250 and the main storage device 104) coupled to the system bus 113. I can understand that the processor 101 may include other devices coupled to the system bus 113. These devices do not need to be described further, so they are omitted for simplicity. The BIU 212 is connected to an instruction cache and memory management unit 214 and a data cache and memory management unit 216 in the processor 101. High-speed caches, such as those located in the instruction cache 214 and the data cache 216, allow the processor 101 to achieve fairly fast access to a subset or instruction of data previously transmitted from the system memory 250, thereby improving the performance of the data processing system 100. Speed of operation. The data and instructions stored in the data cache 216 and the instruction cache 214, respectively, are identified and accessed using address tags, each of which contains the bits (usually high-level) of the physical address of the system memory where the data or instruction is located Bits). The sequential fetch unit 217 fetches the instruction to be executed from the instruction cache 214 in each clock cycle. In a specific embodiment, if the sequential fetch unit 217 obtains a branch instruction from the instruction cache 214, the branch instruction will be forwarded to the sub-9-this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public Centimeters)

536685 A7 B7 V. Description of the invention (BPU) 218 for execution. Sequential fetch unit 2 17 transfers unbranched instructions to instruction queue 219, where the instructions are temporarily stored and waiting for other functional units of processor 101 A distribution unit 220 will fetch the stored instructions from the queue 219 and transfer the instructions to the problem unit (ISU) 221. The distribution unit 220 will schedule the instructions to be distributed to the instruction completion information received from the completion unit 240. Question unit 22 1. The specific embodiment of ISU 22 1 described includes one or more question queues 222a, 222b, 222c, etc. (collectively referred to as question queue 222). ISU 221 utilizes new The instructions issued to the conformal unit are responsible for maintaining the complete load pipeline. In a specific embodiment, the instructions issued by the ISU 22 1 have no order. In the specific embodiment described, the execution circuit of the processor 101 except the BPU In addition to 218 (including multiple execution units), it also includes a multi-purpose fixed point unit execution unit (FXU) 223, a load / storage unit (LSU) 228, and a floating point execution unit (FPU) 230. F XU 223 uses a source operator from a specific general-purpose register (GPR) 232 to represent a dedicated fixed-point structure and a logical unit that can perform fixed-point addition, subtraction, AND, OR, and XOR operations. In other specific implementations For example, the execution unit 223 may include a load / storage unit and a calculation / logic unit. After the execution of the fixed-point instruction, the fixed-point execution unit 223 outputs the result of the instruction to the GPR buffer 232, and the result is provided here Storage space for results received on bus 262. FPU 230 can perform single and double precision floating point arithmetic and logical operations on source operators received from floating point register (FPR) 236, such as floating point multiplication- 10- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Binding

Line 536685 A7 B7 ___ V. Description of the invention (8) Method and division. The FPU 230 stores the data result output from the execution of the floating-point instruction to the selected FPR buffer 236. LSU 228 typically executes floating point data loading from data cache 216, low-level cache memory (not shown), or system memory 250 to selected GPR 232 or FPR 236 and / or floating point and fixed point storage instructions With the fixed-point load command, it stores data from one of the selected GPR 232 or FPR 236 to the data cache 216, and finally to the system memory 250. In a preferred embodiment, the processor 101 uses out-of-order instruction execution to further improve the performance of its superscalar architecture. Therefore, the FXU 223 'LSU 228 and FPU 230 can execute the order by changing the order of the original order of the command, and can know that the data are independent of each other. As previously noted, the FXU 223, LSU 228, and FPU 230 process instructions in the order of the pipeline stages. In a specific embodiment, the processor 101 includes five distinct pipeline stages, in other words fetch, decode / distribute, execute, end, and complete. During the fetch phase, the sequential fetch unit 217 obtains one or more unbranched instructions from the instruction bounce 214, and stores the fetched instructions in the instruction queue 219. In contrast, the sequential fetch unit 217 forwards branch instructions from the instruction stream to the BPU 218 for execution. The BPU 218 includes a branch forecasting mechanism, which in a specific embodiment includes a dynamic forecasting mechanism, such as a branch record table, which allows the BPU 218 to risk executing unresolved conditional branch instructions by predicting whether a branch is accepted. In the decoding / distribution phase, the distribution unit 220 and ISU 221 will decode and usually send one or more instructions to the execution order from the question queue 222 in program order-11-This paper size applies the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) 536685 A7 B7 5. Description of the invention (9) Yuan 223, 228 and 230. In a specific embodiment, the ISU 221 may allocate one or more physical registers to the general purpose register (GPR) pool 232 and the floating point register (FPR) pool 236 to store the results before the instruction and Record the allocation in the comparison table. In addition, the instruction (or instruction identification code or label representing the instruction) can be stored in the multi-slot completion buffer (or completion table) of the completion unit 240 as a device to track which instruction has been completed. During the execution phase, execution units 223, 228, and 230 will opportunistically execute instructions issued from ISU 220 as operators and execution resources to indicate that operations are already available. Execution units 223, 228, and 230 include reservation stations that store instructions distributed to the execution unit until the operator or execution resource becomes available. After the execution of the instruction is terminated, if there is a result, the execution units 223, 228, and 230 will store the data result in the GPR or FPR according to the type of instruction. In the specific embodiment of delivery, the execution units 223, 228, and 230 will remind the completion unit 240 that the instructions have been executed. Finally, the data results of the instructions from the GPR rename buffer 233 and the FPR rename buffer 237 are transmitted to the GPR 232 and FPR 236, respectively, so that the instructions are completed in the program sequence in the completion table of the non-complete unit 240. The processor 101 preferably supports the execution of out-of-order theoretical instructions. The instructions can be theoretically executed according to a predicted branch or overrun instruction that would cause an interruption. In the event of an unforeseen or interrupted branch, the hardware will automatically clear the unwanted instructions from the pipeline and ignore the unwanted results. Incorrect clock results from all units are selectively cleared in one clock cycle, and instructions issued are resumed in the next clock cycle. When an order has been issued, ISU 221 can easily decide between any two orders. -12- This paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) binding

Line 536685 A7 B7 V. Description of the Invention (1Q) Relative age marks the instructions. In one embodiment, sequential instructions are marked with an integer value (ITAG). In other specific embodiments, for tracking purposes, multiple instructions may be grouped into a group and assigned a common identification code, which is referred to herein as a group tag (GTAG). In addition to the organization that provides the order and relative age of the instructions issued, ITAG and GTAG also provide shorthand representatives of their corresponding instructions. The label value of the instruction is accompanied by a queued item and the pipeline phase it is in. The use of tags is helpful to the instruction clearing mechanism (in response to a clear instruction generated by the processor), which executes the range between the ITAG or GTAG with a clear instruction and the ITAG or GTAG with a specific queue item or execution unit Compare, and if it is used to be younger or the same as a cleared instruction (that is, issued at the same time or later), the item will be invalidated. All remaining cleared instructions (and all subsequent instructions) are "cleared" from the machine, and the fetch unit will point back to the address of the "cleared" instruction to start fetching. Please refer to FIG. 3 at this time, which shows another detailed view of the microprocessor 101 according to a specific embodiment of the present invention. In the illustrated specific embodiment, the distribution unit 220 is configured to receive an instruction retrieved from the instruction cache 214 (as shown in FIG. 2). The distribution unit 220 includes allocation logic 302 that is set to determine whether the received instruction requires a single register allocation or multiple register allocations, and allocates an appropriate number of items in the physical register pool 306. The number of structured general-purpose registers that will be affected by determining the instruction can be used to determine the number of register allocations required by the instruction. In addition, the allocation logic 302 will associate the allocated registers with the structured registers. Recorded in the comparison table 304. In this way, the comparison table 304 contains information indicating the relationship between the structured register and the physical register. -13- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

Hold

536685 A7

Although the specific embodiment described above illustrates that the distribution logic 302 is equipped with a single unit 220'-partial portion 'for the issuing unit, those familiar with the microprocessor architecture will understand that the distribution logic 302 may be located on the processor. (For example, the unit 221 is issued according to the implementation). Knife: Logic 302 can be used to allocate all required result registers in one cycle. 'The maximum processor performance has been achieved. In a single cycle, you can issue a deduction order, and the allocation logic is 302. It should be possible to allocate sufficient registers in the register pool 306 to accommodate the largest continuous distribution and dispatch rate. However, as processor cycle time decreases, it becomes more difficult to allocate a sufficient number of scratchpads within the allocated time. In most instruction sets, most of the microprocessor instructions only affect the internal # of the single- scratchpad. Usually, the allocation logic has been optimized. N scratchpads can be allocated in a single cycle, where N is micro The maximum number of instructions that the processor 101 can distribute and issue in a single cycle. In this case, usually, if one or more instructions affect the contents of multiple scratchpads, the allocation logic cannot allocate enough scratchpads in a single cycle. However, the allocation logic 302 will be set to accommodate situations where multiple result register allocations are required for an instruction, but this will not negatively affect the number of instructions that can be issued or dispatched during that period. An example of an instruction that requires multiple result registers is the pOWerpC instruction set attached to a multi-character (LMW) instruction. The LMW instruction affects the inner valley of the specific destination register 'and all registers larger than the specific destination register. The contents of the register of the register. For example, the command LMW R26, EA will load six consecutive characters (four-byte segments) from memory starting at effective address (EA) into R26 to R3 i (PowerPC® command and support 32 structured Register). To be limited time -14-This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 536685 A7 B7 V. Description of the invention (12) The number of registers required to allocate each instruction, implying the use of The processor cycle time of traditional configuration methods is usually not achievable. The allocation logic 302 according to the present invention uses the detection of complex instructions when a register has been allocated, and allocates the registers in another way when a complex instruction is detected to locate allocation for multiple result registers. Issue with register of instructions (complex instructions). Generally, another allocation method used is to speed up the allocation process by allocating a scratchpad that is large enough to hold at least part of the register affected by complex instructions. In order to ensure that there are sufficient scratchpads available for block allocation, the allocation logic 302 sets the physical scratchpad pool containing the main scratchpad pool as a priority that has been allocated by the single-response scratchpad instruction (simple instruction) Registers, and register reserve pools that allocate block registers to complex instructions. Referring to FIG. 4 at this time, the physical register pool 306 will be distributed to include the first part identified as the main register pool 404 and the second part identified as the retained register pool 402. In a specific embodiment, when a register is allocated to a simple instruction, the allocation logic 302 preferentially allocates a register in the main register 404. For example, when there is a simple order at the time of delivery and no register can be allocated in the main pool 404, this priority will be ignored. However, in general, the result register of a simple instruction is allocated to the main pool 404 using a traditional allocation algorithm. Whenever possible, the simple instruction register is allocated to the main pool 404, while the allocation logic 302 reserves the registers in the reservation pool 402 to the complex instruction register. The allocation logic 302 will be set to detect Delivery of complex orders. In a specific embodiment, the opcode of the distributed instruction and the complex instruction opcode are used. _- 15-_ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

Binding

Line 536685 A7 B7 V. Comparison of the predetermined set of invention description (13), the detection of complex instructions can be achieved. In this manner, the opcode that triggers the use of the reserve pool 402 can be agreed by the designer. In other specific embodiments, the allocation logic 302 includes a programmable programming table of opcode, which can trigger block allocation and use of the reserve pool 402. As shown in the example, because the LMW instruction can affect more registers than other instructions, the allocation logic 302 will allocate the registers in the reservation pool 402 only when the LMW instruction is detected. In addition to the logic that detects the distribution of complex instructions, the allocation logic 302 also tracks the allocation of registers in the physical register pool 306. When a complex instruction is detected, the allocation logic 302 determines whether there are enough registers in the reserve pool 402 to hold the registers affected by the complex instruction. If there are enough registers, the allocation logic 302 will allocate a physical register in the reserve pool 402 to the complex instruction. The physical register is allocated by the allocation logic 302. The logical register block preferably contains a part of the structured register affected by the complex instructions. In a specific embodiment, if the complex instruction is a suitable complex instruction, the scratchpad in the reserve pool 402 will be allocated as a block. Limiting the application of the block allocation mechanism described here to a subset of complex instructions can be explained in specific applications. For example, using traditional scratchpad allocation logic may more efficiently handle complex instructions that only affect the contents of the two scratchpads. Register allocation. In this specific embodiment, generally suitable complex instructions include these instructions, such as LMW instructions in the PowerPC® instruction set that can affect the contents of multiple registers. In a specific embodiment, a predetermined or fixed structured register block is allocated every time a suitable complex instruction is detected, which can simplify the block allocation mechanism. For example, when the allocation logic 302 detects the LMW indicator -16- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm).

Line 536685 A7 B7 V. Description of the invention (14) When ordered, the structured register that is actually affected by the instruction will allocate a predetermined set of structured registers in blocks. For example, in one implementation, the physical register pool 302 can be divided into 16 registers into the reserve pool 402, and the other is in the main pool 404. When the LMW instruction is distributed, the "average" LMW instruction requires 16 or less register allocations. In theory, the allocation logic will automatically allocate the structured registers R16 to R 31 in the reserve pool 402. In this specific embodiment, the previously discussed LM W R26, EA instruction will allocate the structured registers R16 to R31 in the reserve pool 402 for the first time, even if the registers R17 to R25 are not affected by the instruction. Although there is no need to allocate registers in some cases, this implementation greatly simplifies the allocation process by eliminating the need to precisely determine which register is affected by a particular instruction. Figure 4 illustrates the state of the physical register pool 306 and the comparison table 304 before the appropriate complex instruction is dispatched. In this figure, the reserve pool 402 contains 16 physical registers, and no registers are allocated at the time of delivery of complex instructions. The main register pool 404 contains 64 registers (registers 16 to 79), and one or more registers can be allocated. In the illustrated example, the comparison table 304 indicates that the current R 17 structured register is allocated to the physical register 51 and the corresponding value is stored in the physical register 51. Please refer to Figure 5 at this time, which will illustrate the diagram of the physical register pool 306 and the comparison table 304 after the delivery of appropriate complex instructions (such as the LMW R26, EA instruction that has appeared in the previous example). In the illustrated example, the allocation logic 302 detects the LMW instruction to determine that the reserved pool 402 is available for block allocation (that is, the entire block has not yet been allocated). After deciding that the reservation pool 402 is available for allocation, the allocation logic 302 will automatically allocate the structured registers R16 to R31 to the reservation -17- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

Hold

Line 536685 A7 B7 V. Description of the invention (15) Continuous physical registers in the pool 402 (in the illustrated embodiment, the physical registers 0 to 15). After the physical register in the reserve pool 402 is allocated, the allocation logic 302 performs internal management of the comparison table 304 and the physical register pool 306 to illustrate that it is not affected by complex instructions but the allocation logic 302 is not allocated to the reserve pool 402 Register. In the illustrated example, the structured registers R26 to R31 are affected by complex instructions. Therefore, after allocating to the reserve pool 402, the processor 101 will start to get the value from the memory (or cache) to store it in the corresponding physical register. However, the structured registers R16 to R 25 are not affected by complex instructions. The allocation logic 302 must decide if there are unaffected but allocated scratchpads already allocated in the main pool 404. In the illustrated example, the structured register R17 is allocated to the physical register 51 (as shown in Figure 4) before the complex instruction is dispatched. In a specific embodiment, the block allocation that occurs when a complex instruction is dispatched updates the lookup table 304, mapping the structured register 17 to the physical register 1. In addition, the contents of the physical register 51 are copied to the physical register 1 (assuming that the physical register 51 has a valid value). If the result in the register 51 is not yet valid, the copy to the physical register 1 will be delayed. In other specific embodiments suitable for remapping overly complex applications that are not affected by complex instructions (presentation time constraints) (such as the structured register 17 in the example), unaffected temporary registers The memory is not remapped. In this embodiment, the structured registers 16 to 25 in the previous example are not remapped to the reserved pool. If the complex instruction requires more register allocation than the predetermined allocation amount, in the traditional way, the allocation logic 302 will allocate the unused block allocation method. -18- This paper standard applies to China National Standard (CNS) A4 specifications ( 210X297 mm)

Hold

Line 536685 A7 B7 V. Register of Invention Description (16). After the reservation pool 402 is allocated, the allocation logic 302 will continue to allocate the registers in the main pool 404. After the time has elapsed, the scratchpad allocation in the reserve pool 402 will be invalidated or reclaimed, and then the reserve pool will be opened to subsequent block allocations. In a specific embodiment, the allocation logic 302 may be configured to reposition the reserve pool 402 to improve the ability to accommodate space-constrained complex instructions. In this specific embodiment, the reservation pool 402 may contain any adjacent physical register blocks. After the block allocation is completed, the boundaries of the reserve pool are moved to any adjacent blocks of unallocated scratchpad. Without such a block, the reserve pool 402 is moved to an adjacent block with the least allocated scratchpad, and the allocated scratchpad is re-allocated in the newly defined reserve pool. Those who are proficient in this technique and know the benefits will understand that the present invention uses a simple way to allocate multiple registers to accommodate instructions that affect the contents of multiple registers, and Predictive can improve the performance of the microprocessor. efficacy. I can understand that the type, detailed description and drawings shown in the present invention are only for presenting better examples, so it can be interpreted that the scope of the following application patents encompasses all the changes disclosed in the better specific embodiments. -19- This paper size is applicable to China National Standard (CNS) A4 (210X 297mm) binding

line

Claims (1)

536685 AB c D 7. Scope of Patent Application 1. A method for processing instructions in a microprocessor, including: whether the instructions to be distributed are complex instructions that require multiple registers to be allocated; if the deduction order requires only a single register Allocation, the physical register of the distributed instruction is allocated to the first part of the register pool, and if the instruction requires multiple register allocation, a group is allocated to the second part of the register pool The physical register in the share is allocated as a block. 2 · If the method of the first item of the scope of patent application is applied, if the instruction affects the contents of multiple general-purpose registers, the instruction requires multiple register allocations. 3. The method of item 1 in the scope of patent application, wherein the block allocation will only start when the instruction requiring multiple temporary register allocation is a suitable instruction '. 4. The method of claim 3, wherein the appropriate instruction includes a load multiple character (LMW) instruction. 5 · The method according to item 1 of the patent application scope, wherein the block group of the allocation physical register corresponds to a group of structured registers, and further wherein the group of structured registers is independent of the structured structure affected by the instruction Register. 6 · If the method according to item 5 of the scope of patent application, further includes that if the number of structured registers affected by the instruction exceeds the number of registers in the second part of the register pool, part of the structured temporary registers affected by the instruction Registers are allocated to the first part of the register pool. 7 · The method of claiming item 1 of the patent gas, further comprising selecting the third part of the register pool after distributing the second part of the register pool in response to an instruction requiring multiple register allocation. Used as a reserve pool for the allocation of subsequent complex instructions. -20-This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 mm) 536685 AB c D 6. Patent application scope 8. — A type of microprocessor, including: a suitable for receiving from the instruction memory The instruction is transferred to the distribution unit of the issuing unit; a physical register pool; allocation logic, which is set to determine whether the instruction is a complex instruction that requires multiple register allocations, and further set that if the instruction requires only a single register allocation , The first part of the register in the register pool is preferentially allocated to the instruction, and if the instruction is a complex instruction, a group of registers in the second part of the register pool is allocated as a block. 9 • If the processor of item 8 of the scope of patent application, if the instruction affects the contents of multiple general-purpose registers, the instruction requires multiple register allocation. 10. If the processor of the patent application No. 8 range, the block allocation will only start when the complex instruction is a suitable instruction. 11. The processor of claim 8 in which the appropriate complex instruction includes a load multiple character (LMW) instruction. 12. The processor according to item 8 of the patent application, wherein if a complex instruction is detected, the allocation logic block will allocate a group of physical registers to a group of structured registers, and further wherein the group of structures The structured register is independent of the structured register affected by the instruction. 13. If the processor of item 12 of the patent application scope, the allocation logic or setting is such that if the structured register affected by the instruction exceeds the number of the second part of the register in the register pool, part of the instruction is subject to the instruction The affected structured registers are allocated to the first part of the register pool. -21-This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 536685 8 8 8 8 A BCD, patent application scope 14. If the processor of patent scope item 8 is applied, the allocation logic will be After the second part of the register pool is allocated in response to an instruction that requires multiple register allocation, the third part of the register pool is selected as a reserved pool for allocating registers for subsequent complex instructions. 15. —A data processing system including a processor, a memory, an input device, and a display, the microprocessor includes: a distribution unit adapted to forward instructions received from the instruction memory to the issuing unit; a physical register pool ; Allocation logic, which is set to determine whether the instruction is a complex instruction that requires multiple register allocation, and further sets that if the instruction requires only a single register allocation, the first part of the register in the register pool is preferentially allocated Register, and if the instruction is a complex instruction, a group of registers in the second part of the register pool is allocated as a block. 16. If the data processing system of the scope of application for item 15 of the patent, where the instruction affects the contents of multiple general-purpose registers, the instruction requires multiple register allocation. 17. In the case of the data processing system in the scope of patent application No. 15, the block allocation will start only when the complex instruction is a suitable instruction. 18. The data processing system of claim 15 in which the appropriate complex instruction includes a load multiple character (LMW) instruction. 19. If the data processing system of the scope of application for patent No.15, if a complex instruction is detected, the allocation logic block will allocate a group of physical registers to a group of structured registers, and further where the group Structured temporary storage-22- This paper size applies to Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 536685 8 8 8 8 A B c D • The scope of patent application is independent of the structured register affected by the directive. 20 · If the data processing system of item 19 of the patent application scope, the allocation logic or setting is such that if the structured register affected by the instruction exceeds the number of the second part of the register in the register pool, part of the The structured registers affected by the instruction are allocated to the first part of the register pool. -23- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)