經濟部智慧財產局員工消費合作社印製 533576 6787twf.doc/006 pj B7 五、發明說明（ί ) 本發明是有關於一種半導體元件及其製造方法，且特 別是有關於一種在半導體元件上的靜電放電（ESD)保護電 路及其製作方法。 對現在的積體電路來說，靜電放電造成的損害是一種 很顯見的損害原因，特別是在積體電路的尺寸持續的縮 小，往次微米的領域發展時。靜電放電通常發生在主體的 一或多個1C終端相接觸，而主體以蓄積儲存到高電壓的 狀態（達到幾千個伏特），靜電蓄電的程度通常是由摩擦生 電的效應，以及其他與人類或製作設備運作來產生。透過 接觸，積體電路會經由其主動區域與DC電流的路徑將主 體蓄積的電荷釋放掉，假如電荷的量過多，放電的電流密 度將會損害積體電路，使其無法長期使用，或者是使其在 後續有失效的狀況產生，因此在製程上ESD損害是良率損 失的一個原因，也會造成使用時低的可靠度。 在這個產業中，將ESD保護元件連接到每一個積體電 路的外部終端是熟習此技藝者常應用的方式，ESD保護元 件被設計來提供足夠容量的電流路徑，以在一個ESD情況 下使畜SS的主體可以女全的將電何浅漏掉，但是不會影響 到積體電路在正常操作下的功能，ESD保護元件額外的寄 生效果會導致電路的效能降低，在一些像是串聯電阻的例 子中，直接加入ESD保護元件會對電性效能有延遲，因此 使用ESD保護元件的一個理想目標是提供一個高容量的電 流路徑，在一個ESD情況下很容易觸發，但是在正常的情 況下並不會引發，且對電路效能的影響達到最小。 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ----------貼4 ———I—-訂——— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 533576 6787twf.doc/006 A7 B7 五、發明說明（之） 第1圖爲一個習知ESD保護電路的結構剖面圖。 提供一個基底1〇〇,在基底1〇〇中有多個場氧化層102 ’ 用以作爲隔離結構，並定義出主動區，這些場氧化層102 可以利用LOCOS(區域矽氧化法）或是淺溝渠隔離（STI)製 程，先在基底100中形成溝渠然後在進行化學氣相沈積 (CVD)在溝渠中沈積氧化物來形成，依序在基底100上形 成閘極氧化層112、多晶矽層114、間隙壁116、以及具有 輕摻雜汲極區(LDD)的源極/汲極區118(所繪示的源極/汲極 區包括N+摻雜區與N·摻雜區）。接著，在多晶矽層114與 源極/汲極區118上，以自動金屬矽化物製程分別形成自動 對準金屬矽化物層120,接著形成一層定義過的光阻層覆 蓋在主動區上，利用定義過的光阻將金屬矽化物層暴露的 部分以乾蝕刻移除掉，直到暴露出源極/汲極區，然後移除 光阻。接著，在整個晶圓的表面上形成一層厚的內層介電 層122(ILD)，再選擇性的移除以形成一個接觸窗開口暴露 出源極/汲極區。 在製作ESD保護元件的傳統製程上，源極/汲極區會被 作成具有輕摻雜汲極區的結構，以避免在積體電路中產生 短通道效應，但是這些LDD結構在較高的基納崩潰電壓 會使二極體的開啓速度變慢，並且使ESD保護元件的ESD 回應變慢。 而且，在製作ESD保護元件的傳統製程上，當積體電 路的積集度提昇時，必須使用到更薄的閘極氧化層，這樣 可能會造成閘極雹薄化與導致更高的缺陷密度，並增加弱 4 ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------411^· I--------^------1— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 533576 6787twf.doc/006 幻 B7 五、發明說明（$ ) 點（weak point)的可能性。 有鑑於此，本發明的目的在於提供一種具有增進的靜 電放電回應的靜電放電保護元件，及其製作方法。 本發明提供一種半導體元件中靜電放電保護元件的改 良結構與其改良的製造方法，其中靜電放電保護元件包括 一個基底，在基底上有一層氧化矽層，並有η型的離子植 入基底形成源極/汲極區，以及在基底上有一層金屬層，進 行一道熱製程以在源極/汲極區上形成金屬矽化物層。 本發明更提供一種製作ESD保護元件的方法，在基底 上形成一層氧化矽層，於其上覆蓋一層光阻層，將η型離 子植入基底表面，以在ESD保護區域中型成源極/汲極區， 在移除光阻層以後，沈積一層金屬層覆蓋整個基底表面， 進行一道熱製程以在源極/汲極區上形成金屬矽化物，再進 行一道蝕刻製程以剝除未反應的金屬層。 如上所述，新的靜電放電保護元件具有源極/汲極區， 係以自動擴散的形式形成，而非形成LDD結構的傳統方 式。沒有LDD結構，就可以避免因爲使二極體開啓速度 變慢的較高的基納崩潰電壓，會導致在保護元件中的靜電 放電回應變慢的結果產生。此外，因爲不需要LDD結構， 可以省略一道進行離子植入製程所需的罩幕步驟，因此可 以降低製作成本。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝--------訂-------— (請先閱讀背面之注音3事項再填寫本頁) A7 533576 6787twf·doc/006 __B7_ 五、發明說明（沭） 圖式之簡單說明： 第1圖爲一個習知ESD保護電路的結構剖面圖； 第2圖繪示爲本發明一較佳實施例之一種靜電放電保 護元件結構的上視圖；以及 第3A圖至第3E圖繪示爲沿著第2圖中的線段M’之 靜電放電保護元件的製作流程剖面圖。 圖示標記說明： 100, 300 基底 102 場氧化層 112 閘極氧化層 114 多晶矽層 116 間隙壁 118, 208, 308 源極/汲極區 122, 314 內層介電層120, 312 金屬矽化物 204 主動區 202, 302 淺溝渠隔離 301 井區 304 氧化層 306 光阻層 307 開口 310 金屬層 316 金屬插塞 318 金屬內連線 眚施例 以下將參考圖示詳細說明本發明之較佳實施例，在圖 示與敘述中將會使用相同的標號來代表相同或相似的部 分0 第2圖繪示爲本發明一較佳實施例之一種靜電放電保 護元件結構的上視圖。請參照第2圖，在基底300上有一 個靜電放電保護元件結構，基底300可能包括一個井區， 像是P井或N井’在基底300中也定義出主動區204，這 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 533576 6787twf.doc/006 pj B7 五、發明說明（γ) 些主動區204被淺溝渠隔離結構202給區隔開。Ρ井可以 用植入像是硼的雜質來形成，而Ν井可以利用植入像是磷 的雜質來完成，以Ρ井爲例，會進一步在基底300的主動 區204中形成Ν摻雜的源極/汲極區，其中以一個交互的 順序排列，比如源極/汲極/源極/汲極等。有複數個內連線 插塞2Q8會分別與這些源極/汲極區206作電性接觸，每一 個源極會與另一個源極電性接觸，同樣的每一個汲極也會 也令一個汲極作電性接觸。 以下參照第3Α圖至第3Ε圖說明本發明之較佳實施 例，其繪示爲沿著第2圖中的線段1-1’之靜電放電保護元 件的製作流程剖面圖。 首先，請參照第3Α圖，提供一個矽的半導體基底300， 在基底300中也形成一個摻雜的井區301，在基底300中 有一個淺溝渠隔離結構302(就是第2圖中結構202)，用以 定義出主動區204。利用熱氧化法形成一層氧化層304, 此氧化層304會在後續形成自動對準的金屬矽化物層時有 用到。 請參照第3Β圖，在氧化層304的表面上覆蓋上一層光 阻層306,接著定義以形成暴露部分氧化層304的開口 307， 利用光阻層306作爲蝕刻罩幕，蝕刻氧化層3〇4暴露出來 的部分，結果會暴露出一部份的基底3〇〇，在後續會有源 極/汲極區形成於其中。 請參照第3C圖，利用光阻層3〇6作爲罩幕進行離子植 入步驟，將離子植入到基底300中以形成摻雜區308，比 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱) (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 533576 6787twf.doc / 006 pj B7 V. Description of the invention (ί) The present invention relates to a semiconductor element and a method for manufacturing the same, and more particularly to a static electricity on the semiconductor element Discharge (ESD) protection circuit and manufacturing method thereof. For today's integrated circuits, the damage caused by electrostatic discharge is a very obvious cause of damage, especially when the size of integrated circuits continues to shrink and develops in the sub-micron field. Electrostatic discharge usually occurs when one or more 1C terminals of the main body are in contact with each other, and the main body is stored to a high voltage state (up to several thousand volts). The degree of static electricity storage is usually the effect of triboelectricity, and other Human or production equipment operates to produce. Through contact, the integrated circuit will release the charge accumulated by the main body through its active area and the path of the DC current. If the amount of charge is too large, the current density of the discharge will damage the integrated circuit, making it impossible to use it for a long time, or It has a subsequent failure condition, so ESD damage in the process is a cause of yield loss, and it will also cause low reliability during use. In this industry, connecting ESD protection elements to the external terminals of each integrated circuit is a method often used by those skilled in the art. ESD protection elements are designed to provide a current path of sufficient capacity to enable animals in an ESD situation. The main body of the SS can drain the electric current, but it will not affect the function of the integrated circuit under normal operation. The extra parasitic effect of the ESD protection element will cause the circuit's efficiency to decrease. In the example, directly adding ESD protection elements will delay the electrical performance. Therefore, an ideal goal of using ESD protection elements is to provide a high-capacity current path. It is easy to trigger in an ESD situation, but under normal conditions and Does not trigger, and has minimal impact on circuit performance. 3 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 public love) ---------- Post 4 ——— I—-Order ——— (Please read the notes on the back first (Fill in this page again) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 533576 6787twf.doc / 006 A7 B7 V. Description of the Invention (the) Figure 1 is a structural cross-sectional view of a conventional ESD protection circuit. A substrate 100 is provided. In the substrate 100, a plurality of field oxide layers 102 ′ are used as an isolation structure, and an active region is defined. These field oxide layers 102 may be LOCOS (Local Silicon Oxidation) or shallow. In the trench isolation (STI) process, a trench is first formed in the substrate 100 and then an oxide is deposited in the trench by chemical vapor deposition (CVD). A gate oxide layer 112, a polycrystalline silicon layer 114, and a silicon oxide layer 114 are sequentially formed on the substrate 100. The spacer 116 and the source / drain region 118 having a lightly doped drain region (LDD) (the illustrated source / drain region includes N + doped regions and N · doped regions). Next, an auto-aligned metal silicide layer 120 is formed on the polycrystalline silicon layer 114 and the source / drain region 118 by an automatic metal silicide process, and then a defined photoresist layer is formed to cover the active region. The exposed photoresist removes the exposed portion of the metal silicide layer by dry etching until the source / drain region is exposed, and then the photoresist is removed. Next, a thick inner dielectric layer 122 (ILD) is formed on the entire surface of the wafer, and then selectively removed to form a contact window opening to expose the source / drain regions. In the traditional manufacturing process of ESD protection devices, the source / drain region will be structured with a lightly doped drain region to avoid short-channel effects in integrated circuits, but these LDD structures are at a higher base. Nano breakdown voltage slows down the diode's turn-on speed and slows the ESD return of the ESD protection element. Moreover, in the traditional manufacturing process of ESD protection elements, when the integration degree of integrated circuits is improved, a thinner gate oxide layer must be used, which may cause gate hail thinning and higher defect density. And increase the weak 4 ^ paper size to apply Chinese National Standard (CNS) A4 specifications (210 X 297 mm) ---------- 411 ^ · I -------- ^ --- --- 1— (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 533576 6787twf.doc / 006 Magic B7 V. The possibility of invention ($) weak point Sex. In view of this, an object of the present invention is to provide an electrostatic discharge protection element having an improved electrostatic discharge response, and a method for manufacturing the same. The invention provides an improved structure of an electrostatic discharge protection element in a semiconductor element and an improved manufacturing method thereof. The electrostatic discharge protection element includes a substrate, a silicon oxide layer on the substrate, and an η-type ion implantation substrate to form a source. The drain / drain region and a metal layer on the substrate are subjected to a thermal process to form a metal silicide layer on the source / drain region. The invention further provides a method for manufacturing an ESD protection element. A silicon oxide layer is formed on a substrate, and a photoresist layer is covered thereon. An n-type ion is implanted on the surface of the substrate to form a source / drain in the ESD protection area. In the polar region, after removing the photoresist layer, a metal layer is deposited to cover the entire substrate surface. A thermal process is performed to form a metal silicide on the source / drain region, and an etching process is performed to strip unreacted metal. Floor. As mentioned above, the new ESD protection element has a source / drain region, which is formed in the form of auto-diffusion instead of the traditional way of forming an LDD structure. Without the LDD structure, it is possible to avoid the result of a slower electrostatic discharge response in the protection element due to the higher Gina breakdown voltage which slows down the diode turn-on speed. In addition, because the LDD structure is not required, a mask step required for performing the ion implantation process can be omitted, so that the manufacturing cost can be reduced. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed descriptions as follows: 5 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----------- install -------- order ----------- (Please read the note 3 on the back before filling in this (Page) A7 533576 6787twf · doc / 006 __B7_ V. Description of the invention (沭) Brief description of the drawings: Figure 1 is a sectional view of the structure of a conventional ESD protection circuit; Figure 2 shows a preferred implementation of the present invention An example is a top view of the structure of an electrostatic discharge protection element; and FIGS. 3A to 3E are cross-sectional views showing a manufacturing process of the electrostatic discharge protection element along the line segment M ′ in FIG. 2. Description of icons: 100, 300 substrate 102 field oxide layer 112 gate oxide layer 114 polycrystalline silicon layer 116 spacer 118, 208, 308 source / drain region 122, 314 inner dielectric layer 120, 312 metal silicide 204 Active area 202, 302 Shallow trench isolation 301 Well area 304 Oxidation layer 306 Photoresist layer 307 Opening 310 Metal layer 316 Metal plug 318 Metal interconnects. Examples The following will describe the preferred embodiment of the present invention in detail with reference to the drawings. The same reference numerals will be used in the illustrations and descriptions to represent the same or similar parts. FIG. 2 is a top view of a structure of an electrostatic discharge protection element according to a preferred embodiment of the present invention. Please refer to Fig. 2. There is an electrostatic discharge protection element structure on the substrate 300. The substrate 300 may include a well region, such as well P or N. The active region 204 is also defined in the substrate 300. These 6 paper sizes Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ---------- install -------- order --------- (Please read the back first Please note this page, please fill in this page) Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by 533576 6787twf.doc / 006 pj B7 V. Description of the invention (γ) Some active areas 204 are shallow The isolation structure 202 is partitioned. The P well can be formed by implanting impurities such as boron, and the N well can be completed by implanting impurities such as phosphorus. Taking the P well as an example, N doping is further formed in the active region 204 of the substrate 300. Source / drain regions, which are arranged in an interactive order, such as source / drain / source / drain. A plurality of interconnect plugs 2Q8 will make electrical contact with these source / drain regions 206 respectively, and each source will be in electrical contact with another source, and each drain will also make one The drain is in electrical contact. Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 3A to 3E, which are shown as cross-sectional views of the manufacturing process of the electrostatic discharge protection element along line 1-1 'in FIG. First, referring to FIG. 3A, a silicon semiconductor substrate 300 is provided. A doped well region 301 is also formed in the substrate 300, and a shallow trench isolation structure 302 is formed in the substrate 300 (that is, the structure 202 in FIG. 2). To define the active area 204. An oxide layer 304 is formed by a thermal oxidation method, and this oxide layer 304 is useful in the subsequent formation of an auto-aligned metal silicide layer. Referring to FIG. 3B, a surface of the oxide layer 304 is covered with a photoresist layer 306, and then an opening 307 is defined to form an exposed portion of the oxide layer 304. The photoresist layer 306 is used as an etching mask to etch the oxide layer 304. As a result, a part of the substrate 300 will be exposed as a result, and a source / drain region will be formed in the subsequent part. Please refer to FIG. 3C, using the photoresist layer 306 as a mask for the ion implantation step, and implanting ions into the substrate 300 to form a doped region 308, which is more than 7 paper standards applicable to Chinese National Standard (CNS) A4 Specifications (210 X 297 public love) (Please read the precautions on the back before filling this page)
— 11----訂·！I 華 533576 67 87twf. doc/006 A7 ___ B7 五、發明說明（β) 如用以作爲源極/汲極區308,欲形成n形摻雜區308的話， 就要植入N型摻質像是磷離子、砷離子或是兩種同時植 入。在第3B圖中蝕刻氧化層的步驟也可以在植入步驟以 後才進行。 請參照第3D圖，在離子植入步驟以後移除光阻層， 然後在基底300上沈積覆蓋一層稀有金屬或貴重金屬層 31〇(比如鈦、鎢、鈷、鎳、鉑、鉻、鈀或其組合），金屬層 310比如用化學氣相沈積法或用濺鍍技術沈積而成，再進 行一道熱製程，利用金屬層310與矽基底300之間的反應 以形成金屬矽化物層312，之後將未反應的金屬層剝除， 比如利用乾蝕刻來進行，僅留下覆蓋在源極/汲極區上的金 屬矽化物層，氧化層304也可以在此步驟中加以移除，但 在本實施例中仍舊保留氧化層304。 在另一個方法中，在形成源極/汲極區以後，會形成一 層定義的光阻層覆蓋部分的源極/汲極區，留下中央暴露的 區域，然後沈積覆蓋一層稀有金屬或貴重金屬層（比如鈦、 鎢、鈷、鎳、鈾、鉻、鈀或其組合），金屬層比如用化學 氣相沈積法或用濺鍍技術沈積而成，再進行一道熱製程， 利用金屬層與矽基底之間的反應以形成金屬矽化物層，之 後將未反應的金屬層剝除，比如利用乾蝕刻來進行，僅留 下覆蓋在源極/汲極區中心區域上的金屬矽化物層，此金屬 矽化物層可以增進源極/汲極區與金屬內連線之間的導電 性。 請參照第3E圖，在基底300上形成內層介電層314， 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -I ϋ n ϋ ββββ I n B1-· 一一OJ all I ϋ #. 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 533576 6787twf.doc/006 ^ B7 五、發明說明（1) 此內層介電層314可以爲氧化矽。接著形成金屬插塞316 與金屬內連線318，因爲這些步驟並非本發明之重點，且 熟習此技藝者均應熟知其方法，故在此不予贅述。如第2 圖所示，所有用以作爲源極區的摻雜區308會透過金屬插 塞316，也就是第2圖中的208，與內連線318被耦接在一 起，所有作爲汲極區的摻雜區308也會被耦接在一起。 本發明的指狀ESD結構僅包括幾個摻雜區，用以作爲 沒有LDD結構的源極區與汲極區，在本發明中包括不連 貫的接合結構，因此基納崩潰電壓可以比習知具有LDD 結構的NM〇S ESD電路來的低，因此可以得到較高的二極 體開啓速度，且藉以使靜電放電保護的達到更好的效果。 在本發明中，因爲實際上沒有包括閘極結構，相較於 一般在內部電路中的MOS電晶體的閘極長度，本發明之 閘極長度，也就是源極/汲極之間的距離，可以被調到較小 的程度。 在本發明中，僅需要修改光阻定義的圖案就可以形成 摻雜區308以及可以包括井區，並不需要使用額外的光阻， 因此不會提高製作成本與製程複雜度。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 9 -----------裝-----丨丨訂-------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱）— 11 ---- Order! I Hua 533576 67 87twf. Doc / 006 A7 ___ B7 V. Description of the invention (β) If it is used as the source / drain region 308, if an n-type doped region 308 is to be formed, an N-type dopant image must be implanted. Is it phosphorus, arsenic, or both. The step of etching the oxide layer in FIG. 3B may be performed after the implantation step. Referring to FIG. 3D, the photoresist layer is removed after the ion implantation step, and a layer of rare or precious metal 31 (such as titanium, tungsten, cobalt, nickel, platinum, chromium, palladium or (Combination), the metal layer 310 is deposited by, for example, chemical vapor deposition or sputtering, and then a thermal process is performed to form a metal silicide layer 312 by using a reaction between the metal layer 310 and the silicon substrate 300. Strip the unreacted metal layer, for example, by dry etching, leaving only the metal silicide layer covering the source / drain region. The oxide layer 304 can also be removed in this step, but in this step The oxide layer 304 remains in the embodiment. In another method, after forming the source / drain region, a defined photoresist layer is formed to cover the source / drain region, leaving the centrally exposed area, and then depositing and covering a layer of rare or precious metal Layer (such as titanium, tungsten, cobalt, nickel, uranium, chromium, palladium, or a combination thereof). The metal layer is deposited by, for example, chemical vapor deposition or sputtering, and then a thermal process is performed using the metal layer and silicon. The reaction between the substrates forms a metal silicide layer, and then the unreacted metal layer is stripped off, for example, using dry etching to leave only the metal silicide layer covering the center area of the source / drain region. The metal silicide layer can improve the conductivity between the source / drain region and the metal interconnect. Please refer to Figure 3E to form an inner dielectric layer 314 on the substrate 300. 8 This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page ) -I ϋ n ϋ ββββ I n B1- · 一一 OJ all Iϋ DESCRIPTION OF THE INVENTION (1) The inner dielectric layer 314 may be silicon oxide. Metal plugs 316 and metal interconnects 318 are formed next, because these steps are not the focus of the present invention, and those skilled in the art should be familiar with their methods, so they will not be repeated here. As shown in FIG. 2, all the doped regions 308 used as source regions pass through the metal plug 316, that is, 208 in FIG. 2, and are connected to the interconnect 318, all of which serve as drain electrodes. The doped regions 308 of the regions are also coupled together. The finger-like ESD structure of the present invention includes only a few doped regions, which are used as the source region and the drain region without the LDD structure. In the present invention, the discontinuous bonding structure is included. The NMOS ESD circuit with the LDD structure is low, so a higher diode turn-on speed can be obtained, and the electrostatic discharge protection can achieve better results. In the present invention, because the gate structure is not actually included, compared to the gate length of a MOS transistor generally used in internal circuits, the gate length of the present invention, that is, the distance between the source and the drain, Can be adjusted to a lesser extent. In the present invention, only the pattern defined by the photoresist needs to be modified to form the doped region 308 and may include a well region. No additional photoresist is required, so the manufacturing cost and process complexity are not increased. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 9 ----------- Loading ----- 丨 丨 Order -------- (Please read the precautions on the back before filling this page) This paper size applies Chinese national standards ( CNS) A4 size (210 X 297 public love)