TW533543B - Structure of metal interconnect and the manufacturing method thereof - Google Patents

Abstract

The present invention provides a manufacturing method for metal interconnect, which includes the following steps: first, providing a substrate; forming a dielectric layer on the substrate, and forming a trench on the surface of the dielectric layer; next, correspondingly forming a first barrier layer on the dielectric layer, correspondingly forming a first metal layer on the first barrier layer, and correspondingly forming a second barrier layer on the first metal layer; then, forming a second metal layer on the second barrier layer, and filling up the trench with the second metal layer; and finally, conducting the chemical mechanical polishing on the first barrier layer, the first metal layer, the second barrier layer and the second metal layer to expose the surface of the dielectric layer.

Description

533543-^ Case No. 91101924 __Meng Zhengyi ______ V. Description of the Invention (1) The technical field to which the invention belongs The invention relates to a semiconductor process technology, and in particular to a method for reducing copper metal interconnection A method of improving the reliability of a circuit by the volume of copper mounds on the wire surface. With the increase of the integration degree of the integrated circuit in the prior art, the chip surface cannot provide enough area to make the required interconnections. In order to meet the increased interconnection requirements after the reduction in the size of the MOS device, two or more metal layers Design has gradually become the way that many integrated circuits must be used, especially-more complex. Mouth-to-mouth, like a microprocessor, even requires four to five layers to complete the connection between the various components in the microprocessor. In a word, 'the production of multiple metal interconnects was made after the main body of Mos was completed:' therefore a system • 'can be considered-individual independent semiconductors made in order to prevent younger brothers from contacting a layer of metal In the event of a short circuit, the metal internal dielectric layer (IMD) is used to isolate the wires. The wire method is mainly to define the contact channel by using the conventional metal interconnection technology of the plug, and then to increase the adhesion of the subsequently filled gold. After that, the crane and then the formation of the above, the, and the mouth layer, and finally, a ig flip interconnection and the second layer of metal interconnection straight connection must be a dielectric layer, that is, Inner ^ It is used to connect the upper and lower layers of metal inside i, such as tungsten plugs, aluminum plugs, etc. The process is mainly to first form a lithography process and then contact the channel surface to form one. Dielectric; P early mask back etch method fills the surface of gold in the trench, and then re-titanium ———————— 〆 reactivity

0503-7166TWF1; TSMC2001-1145; Claire.ptc Deposited on the surface of the structure for isolation, black, 533543

The tea number is 1U1924. 5. Description of the invention (2) Ion 1 worm-cut method is used to define the double-ditch connection channel consisting of the crane plug and the upper and lower metal interconnects. , Small, the conventional metal interconnection process can no longer be applied. After inlay ^ ί = aSCen can overcome the conventional metal interconnection process. The person who described the inlay trenches is mainly used to isolate metal. Interconnecting shape i: 'ΐ Ϊ: A mosaic that penetrates the dielectric layer and connects the metal interconnects and then fills the barrier layer in the trench after inlaying and has better conductivity: Coincidentally, it can be formed— Mosaic junctions used to connect metal interconnects: Second, because copper has better electrical conductivity, 彳 is used to improve the phenomenon of κ delay caused by the small size of the component, and its trench filling f is higher than that of 2 The metal is better, so the copper damascene structure has become a type of inlay I wire widely used in sub-micron process technology. * The following is the first la-le diagram to illustrate the manufacturing process of forming metal-insulated yoke type interconnects using conventional techniques. First, please refer to FIG. 1a. First, a semiconductor substrate 101 is provided, such as a silicon substrate. On the semiconductor substrate 101, there are two layers 102, a dielectric layer 103, and a pattern τ 止 104 which has been pattern-transferred in order. Among them, the known stop layer 102 is, for example, nitride nitride; dielectric acoustic, > resist layer oxide layer. Letter 103 is for example

0503-7166IWl; TSMC2001-1145; Claire.ptc Please refer to Figure ib. Then, patterned photoresist 10 is used to etch the dielectric layer 103 on the exposed surface to form a trench 105I screen. Etching stops Stop at level 02. Dielectric layer 丨 〇3 is to avoid = etched to or the metal conductor is short-circuited due to direct contact. It is necessary for the dielectric lower layer element 4 to be connected between the upper and lower interconnects, so you must use ^ 科; 龟 ^ 533543 Amendment. Case No. 91101924 V. Metal plug (meta 1 p 1 ug) of the description of the invention (3) Lightning, Secret ·, Girl ^, + ^ Yier (raw connection, groove 10 5 such as contact window (contact ) Or via window (via;). U Please refer to Figure lc to remove Xia ψ main; ^. Stop layer 1 〇2 on the exit surface, the removal method such as wet etching, in which thorium, etched The money engraving liquid is, for example, hydrofluoric acid (HF), and then removes the dielectric formed > ^ ^ ^ ^ ^ ^ ^ ^ 丨 patterned photoresist on the surface of 1U4 10 5 0 A barrier layer 106 is compliantly formed on the surface of the trench 105 and the dielectric layer 103. The function of the barrier layer 106 is to prevent copper metal from penetrating into the dielectric during the subsequent copper filling step. Among the electric reeds 103; among them, the barrier layer 1G6 is, for example, a button or titanium or a nitride group or an iJ titanium. Please refer to the figure below, and then use the A good deposition method with a good gap fiiHng forms a metal layer 107 on the surface of the trench 丨 0 5 and the barrier layer 〇 06. The metal layer 107 fills the trench 105; among them, the gold layer 1 0 7 is, for example, a copper metal layer. Finally, please refer to the figure, a patterned photoresist 105 and a metal layer 107 on the surface of the chemical mechanical polishing dielectric layer 103 are planarized until the dielectric layer 103 is exposed. As far as the surface is concerned, a copper interconnect 107a will be formed to fill the trench 〇05. When the size of the 7L part is reduced, the thickness and width of the interconnect between the TL parts will also decrease, while the current density through the lead will It rises with it, causing electromigrathn problems. Because electromigration is caused by the interaction of electrical carriers with metal atoms, and metal atoms mainly move along the grain boundary, making the connection One end protrudes like a small hill (hiu〇ck). The process is performed in the formation of 'U eitUt, and after heat treatment or high temperature

0503-7166TWFl; TSMC2001-1145; Claire.ptc Page 6 533543 _Case No. 91101924_Year Month__ V. Description of the invention (4) During the deposition of silicon nitride, the surface of the copper interconnects that are too thick will A copper hill (Cu hi 1 lock) is formed. The copper hill will make it difficult to pull wires with the circuit board, and will cause interference during defect detection, leading to a reduction in reliability. SUMMARY OF THE INVENTION In view of this, the object of the present invention is to provide a method for manufacturing metal interconnects, which can effectively prevent the surface of copper metal interconnects from being affected by heat treatment, reduce the volume of copper mounds, and make the drawing of wires difficult. This improves the reliability of the circuit. According to the above object, the present invention provides a method for manufacturing a metal interconnect including the following steps: providing a substrate; forming a dielectric layer on the substrate, forming a trench on the surface of the dielectric layer; and conforming to the dielectric layer Forming a first barrier layer; compliantly forming a first metal layer on the first barrier layer; compliantly forming a second barrier layer on the first metal layer; forming a first barrier layer on the second barrier layer Two metal layers, and the second metal layer fills the trench; and chemically and mechanically polishing the first barrier layer, the first metal layer, the second barrier layer, and the second metal layer to expose the surface of the dielectric layer. Another object of the present invention is to provide a metal interconnection for improving the copper mound phenomenon, so that there is no difficulty in pulling the cable, thereby improving the reliability of the circuit. According to the above object, the present invention provides a metal interconnect structure suitable for a semiconductor substrate, including: a dielectric layer disposed on the semiconductor substrate, the dielectric layer having a trench, and a first barrier layer, The compliance is disposed on the sidewall and the bottom of the trench; a first metal layer is disposed on the surface of the first barrier layer; the second barrier layer is disposed on the first metal layer

0503-7166TWFl; TSMC2001-1145; Claire.ptc Page 7 ^ 3543 month --- No. 91101924 V. Description of the invention ^ ------------ Surface, and a second metal layer, set- Trench. Make a prescription; the younger one blocks the surface of the early layer and fills it with easy-to-understand, $ ^: = 上 $ Ϊ other purposes, features, and advantages can be explained in more detail: In conjunction with the attached drawings, a detailed implementation is made: Please refer to Figs. 2a-2h, Fig. 9] n 闰 Technical & The a-2 h diagram is the copper metal forming method of the present invention. Please refer to Fig. 2 & first, provide a semiconductor substrate 2m, such as a silicon substrate. On the semiconductor substrate 201, there are two layers of 202, a dielectric layer of 203, and -y to L only 204. Among them, the stop layer 202 is, for example, a patterned photoresist layer oxide layer turned to J. "The female layer is siliconized, and the dielectric layer 2 0 3 is shown in Fig. 2b, for example. Then, the dielectric layer 2 Q 3 exposed on the surface is engraved with r 〇 on the zigzag pattern ;; / 图 / 化 / ;; = Numeral 4 is a veil, which is stopped when the Qianda stop layer m is reached; it is when the dielectric layer 2 0 3 is reached to avoid the ice degree of the upper and lower sulcus center 5 is about 3 em. The short circuit is necessary for the dielectric layer Λ or the metal conductor to be in direct contact 7: it must be electrically connected through a metal plug "etal Pug" in the trench, such as a contact window or dielectric Layer window (via) 〇 清 * 考 第 2. Figure 'remove the stop layer 2 2 exposed surface, the method of removal such as wet engraving, where the wet etching solution is chloric acid (HF); then 'Remove the dielectric layer 2 (h table

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2 0 5. Please refer to FIG. 2d. A first barrier Uyer 20 is formed on the surface of the trench 205 and the dielectric layer 203; During the copper filling step, it is possible to avoid early / infiltration into the dielectric layer 203; among them, the first barrier layer is a metal or nitride button or titanium nitride. For H or titanium, please refer to Figure 2e, and then use the trench filling ability (gap fiUlnd best deposition method) to comprehensively form a first factory metal layer on the surface of the trench 2 0 5 and the barrier layer 2 0 7 The thickness of the first metal layer 207 is about 2.5, ^ m, wherein the first metal layer 207 is, for example, a copper metal layer. Please refer to FIG. 2f, compliance on the first metal layer 207 A second barrier layer 208 is formed, and the second barrier layer 208 is, for example, a button, a giant nitride, titanium, or a titanium compound. Please refer to FIG. 2g and use a deposition method with a good gap filling capacity (gap fUHng). A second metal layer 209 is formed on the second barrier layer 208 in a comprehensive manner. The second metal layer 209 will fill the trench. The second metal layer 209 is, for example, a copper metal layer and has a thickness of about 0 · 5 _ 1 # ^ Finally, please refer to FIG. 2h to sequentially align the second metal layer 209, the second barrier layer 208, the first metal layer 2〇γ on the surface of the dielectric layer 203, and The first resistive P early layer 206 is subjected to a chemical mechanical polishing step to planarize until the surface of the dielectric layer 203 is exposed, so as to leave the metal interconnects 207a at the trench 205a, 209 a 'and the first barrier layer 206a and the second barrier layer 208a. According to the manufacturing method of the metal interconnects provided by the present invention, the volume of the copper metal interconnects can be cut to make the copper metal interconnects The volume is not too thick, which effectively reduces the volume of the Cu hi 11 ock, which improves the circuit

0503-7166T \ VFl; TSMC2001-1145; Claire.ptc Page 9 533543 Amendment No. 91101924 V. Description of the invention (7) Difficulty of drawing the cable, thereby improving the reliability of the circuit. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone familiar with the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. Brief description of the diagrams: Figures 1a-1f are conventional manufacturing process schematic diagrams for forming metal interconnects. Figures 2a-2h are schematic illustrations of the manufacturing process for forming metal interconnects in the present invention. Layer. Symbol description: 101 ~ semiconductor substrate; 103 ~ dielectric layer; 105 ~ trench; 107 ~ metal layer; 201 ~ semiconductor substrate; 230 ~ dielectric layer; 05 ~ trench; 2 0 7 to the first metal layer; 208, 208a to the second 1¾ 209a to the metal interconnect 1 102 to the stop layer; 104 to the patterned photoresist; 106 to the barrier layer; 10 7 a ~ Metal interconnect; 202 ~ stop layer; 204 ~ patterned photoresist; 206, 206a ~ first barrier layer 207a ~ metal interconnect; 209 ~ second metal layer;

0503-7166TWFl; TSMC2001-1145; Claire.ptc Page 10

Claims (1)

533543 _ Case No. 91101924_ Year Month Date __16. Application scope 1. A method for manufacturing metal interconnects, including the following steps: providing a semiconductor substrate, a dielectric layer is formed on the surface of the semiconductor substrate; A dielectric layer forms a trench; a first barrier layer, a first metal layer, and a second barrier layer are sequentially conformably formed on the trench and the surface of the dielectric layer; on the second barrier Forming a second metal layer on the layer, and the second metal layer filling the trench; and removing the first barrier layer, the first metal layer, the second barrier layer, and the second metal layer until exposed The dielectric layer surface. 2. The method for manufacturing a metal interconnect as described in item 1 of the scope of patent application, wherein the depth of the groove is 3 // m. 3. The method for manufacturing a metal interconnect as described in item 1 of the scope of patent application, wherein the thickness of the first metal layer is 2.5 // m. 4. The method for manufacturing a metal interconnect as described in item 1 of the scope of the patent application, wherein the thickness of the second metal layer is 0.5 // m to 1 // m. 5. The method for manufacturing a metal interconnect as described in item 1 of the scope of patent application, wherein the first barrier layer is a button. 6. The method for manufacturing a metal interconnect as described in item 1 of the patent application scope, wherein the first barrier layer is titanium. 7. The method for manufacturing a metal interconnect as described in item 1 of the scope of patent application, wherein the first barrier layer is a nitride button. 8. The method for manufacturing a metal interconnect as described in item 1 of the patent application scope, wherein the first barrier layer is titanium nitride. 9. Manufacturer of metal interconnects as described in item 1 of the scope of patent application 0503-7166TWFl; TSMC2001-1145; Claire.ptc page 11 533543 _ case number 91101924_ year month__: VI. Patent application method, wherein the first metal layer is a copper metal layer. 10. The method for manufacturing a metal interconnect as described in item 1 of the scope of patent application, wherein the second barrier layer is a button. 1 1. The method for manufacturing a metal interconnect as described in item 1 of the patent application scope, wherein the second barrier layer is titanium. 12. The method for manufacturing a metal interconnect as described in item 1 of the scope of the patent application, wherein the second barrier layer is nitrided nitride. 1 3. The method for manufacturing a metal interconnect as described in item 1 of the scope of patent application, wherein the second barrier layer is titanium nitride. 1 4. The method for manufacturing a metal interconnect as described in item 1 of the scope of patent application, wherein the second metal layer is a copper metal layer. 1 5. The method for manufacturing a metal interconnect as described in item 1 of the scope of patent application, further comprising removing the first barrier layer, the first metal layer, the second barrier layer and the dielectric layer. Step of the second metal layer. 16. A metal interconnect structure suitable for a semiconductor substrate includes: a dielectric layer disposed on the semiconductor substrate, the dielectric layer having a trench; a first barrier layer, compliant Disposed on the sidewall and bottom of the trench; a first metal layer compliantly disposed on the surface of the first barrier layer; a second barrier layer compliantly disposed on the surface of the first metal layer; and a first Two metal layers are disposed on the surface of the second barrier layer and fill the trench. 17. The structure of the metal interconnects as described in item 16 of the scope of the patent application, wherein the depth of the trench is 3 // m. 0503-7166TWF1; TSMC2001-1145; Claire.ptc Page 12 533543 _Case No. 91101924_Year_Month__ Sixth, the scope of patent application 1 8. The structure of the metal interconnect as described in item 16 of the scope of patent application , Wherein the thickness of the first metal layer is 2.5 // m. 19. The structure of the metal interconnects as described in item 16 of the scope of the patent application, wherein the thickness of the second metal layer is 0.5 // m to 1 // m. 20. The structure of a metal interconnect as described in item 16 of the patent application scope, wherein the first barrier layer is tantalum. 2 1. The structure of a metal interconnect as described in item 16 of the scope of patent application, wherein the first barrier layer is titanium. 2 2. The structure of a metal interconnect as described in item 16 of the scope of patent application, wherein the first barrier layer is tantalum nitride. 2 3. The structure of a metal interconnect as described in item 16 of the scope of patent application, wherein the first barrier layer is titanium nitride. 2 4. The structure of the metal interconnects as described in item 16 of the scope of the patent application, wherein the first metal layer is a copper metal layer. 25. The structure of a metal interconnect as described in item 16 of the scope of patent application, wherein the second barrier layer is tantalum. 26. The structure of a metal interconnect as described in item 16 of the scope of patent application, wherein the second barrier layer is titanium. 27. The structure of a metal interconnect as described in item 16 of the patent application scope, wherein the second barrier layer is tantalum nitride. 28. The structure of a metal interconnect as described in item 16 of the patent application scope, wherein the second barrier layer is titanium nitride. 29. The structure of a metal interconnect as described in item 16 of the scope of the patent application, wherein the second metal layer is a copper metal layer. 0503-7166TWFl; TSMC2001-1145; Claire.ptc Page 13