TW532021B - Automatic calibration and synchronization method applied in asynchronous communication transmission system - Google Patents

Abstract

An automatic calibration and synchronization method applied in asynchronous communication transmission system at least comprises the following procedures: (a) initialize a target system; (b) start counting after target detects the falling edge signal of a start bit; (c) stop counting after target detects a rising edge signal of start bit; (d) store a counting result; (e) set up the sampling pointer time period as counting result divided by 2; (f) compensate a delay time and go through a wait loop time period as counting result divided by 2; (g) sample and store first data bit; (h) compensate a delay time and go through a wait loop time period as counting result; (i) sequentially sample and store sequential data bits; (j) confirm sampling and store 8 data bits; (k) locate an inter character region in accordance with the initialization and repeatedly execute procedure (b) to (k).

Description

532021 V. Description of the invention (1) [Field of the invention] The present invention relates to a method for automatic calibration and synchronization in a gray-level asynchronous communication transmission system, and particularly refers to a method A method that can achieve automatic calibration and synchronization without the need for a universal asynchronous receiver and transmitter (Universal Asynchrnousus Receiver and Transmitter; UART), or a receiver that does not have a precise time-base Background] Kai βyushe φ 鞛 represents the beginning and end of the data transfer wheel by the start and end positions, and is transmitted on 丄 through a serial line. Generally speaking, for asynchronous communication, it is necessary to recognize Hr back: ί = when you do not need to wait for the receiving end (target) to return that the extension is non-standard and high-level, so it has better data processing capabilities. 4 In the asynchronous communication, the clock is sent accurately. (E slice) 'Really must = "fine asynchronous transmission and reception wheel (UART), _, the universal locking device has become an inaccurate clock generator or frequency. Device. It is common to maintain accurate clock in a 4-step communication system. However, because of the asynchronous communication (RT) = because of the characteristics of asynchronous communication, the transmission rate is too high, and the baud rate is the same. It ’s difficult to set the transmission speed. The helmeted hardware equipment ca n’t provide or reverse the transmission rate. The real transmission rate is $ 532021.

A rate mismatch occurs. Therefore, a method that does not require asynchronous transmit / receive transmitters (UARTs) and can achieve automatic calibration and synchronization has become a topic of concern. [Summary and Purpose of the Invention] The main purpose of the present invention is to provide a universal asynchronous receiver and receiver

Transmitter; UART), or a receiver that does not have an accurate clock can achieve automatic calibration and synchronization. The method for automatic calibration and synchronization applied in a digital asynchronous communication transmission system provided by the present invention includes at least the following steps: (a) initializing a target system; (b) the receiving end detects a Start counting after a falling edge (faiHng edge) signal of the START bit ('c) The receiver end counts after detecting a rising edge signal of the starting bit; (d) Store a counting result; (e) Set the time length of a sampling pointer to (counting result / 2); (f) Compensate for a delay time and pass a waiting loop (wait 100p) to (counting result) / 2) the length of time; (g) the first data bit is sampled and stored; (h) the length of time that compensates for a delay time and passes through a waiting loop (wai) (count result); (i) ) Sequentially sample and store sequential data bits; (D determines to sample and store 8 data bits; (k) based on the initial Luhuan 'locating' — inter character region; and Repeat steps (b) to (k). [Details of the invention The present invention provides a bright applied to digital transmission systems asynchronous communication from

Page 6 532021 V. Description of the invention (3) The method of dynamic calibration and synchronization is based on the IEEE-232 protocol in a point-to-point (pint tο pint) asynchronous transmission system. The standard is a preferred embodiment. , To illustrate the feasibility of the present invention, but not to limit the scope of application of the present invention. Among them, Fig. 1 is a schematic diagram of a conventional point-to-point asynchronous transmission system. According to the IEEE-232 protocol standard, when an initiator 100 wants to transmit a piece of data to a receiver ( target) 12 (), the transmitting end 100 must define a start bit (START bit) in advance and send it to the receiving end 120. When the receiving end 1 2 0 detects a falling edge of the starting bit ( "falling edge" signal indicates that the receiving end 120 will synchronize with the transmitting end 100, and is ready to receive data after detecting the rising edge signal of the start bit. Here it must be emphasized that the present invention The method must be based on that the sending end 100 needs to have a steady-state time base. Figure 2 is a bit frame waveform diagram of the IEEE-2 32 protocol standard, which is a non-synchronous transmission signal transmitted through a wire and transmitted at a frequency of 9600 Hz. Generally speaking, the receiving end uses 16 times the frequency to sample the data to be received. If the baud rate is 9600Hz as an example, a sampling frequency of 9600 X 1 6 = 1 53 · 6KHz is required. The preferred embodiment 'uses the U sub-element as the transmission character of the transmitting end, because the binary code of the "u" character is "01010101", and the signal transmitted through the transmission line has better data channel balance characteristics, such as "" When the character "u" is transmitted at a frequency of 9600Hz, each bit-frame is equivalent to 1/9600 = 104us; if transmitted at a frequency of 4800Hz, each bit-frame (bit-f raine) is equivalent to 1/480 0 = 20 8us. And a complete " u ,, character frame 20 0 has a 104us start bit 21, and every _ bit information

532021

: 220 has a time interval of 104US, and the figure also shows a sub-interval (Inter Character Region) end interval 230 with mus. Figure ^ is a waveform diagram of a sampling pulse that simulates a data reception. For better steady-state sampling, the sampling pulse occurs at the center of each bit frame, that is, 104/2 = 52us spacing. In fact, the sampling pulse may not exist in the center position of each bit frame. If the receiving end has an accurate clock or frequency mechanism, the sampling interval is easy to reach. In contrast, if the receiving end does not have a With precise clock or frequency mechanisms, the sampling interval is difficult to achieve. As shown in the figure, the sampling pulse 300 that simulates a data reception occurs at the center of each bit frame. When the receiving end _ picks up a falling edge signal 310, it interrupts the receiving end and The first bit 320 is the beginning, followed by the Least Significant Bit (LSB) of the} th bit (bit 丨) 330 to the Most Significant Bit of the 8th bit (bit 8). ; MSB) 340, until the receiving end detects a rising edge signal 35 °, ending a stop bit 360 'because each bit frame has a time interval of 10413, so 8 bits With a time interval of 〇4usx 8 = 832us 370. FIG. 4 is a main flowchart of automatic calibration and synchronization of the present invention. First, a receiving end system is initialized (step 400); when the receiving end detects a falling edge of a START bit (falling edgeMf) After the number, start counting (step 401); when the receiving end detects the rising edge signal of the START bit, the counting ends (step 4202); then the counting result is stored (step 403) ); And set the time length of a sampling indicator (samp 1 ing pointer) to (count result / 2) (step

Page 532021

404) 'and compensate a delay time and pass a waiting loop (wait ι〇〇ρ) for a time length of (count result / 2) (step 4 · 05); sample and store the first data bit (step 4 0 6); then compensating for a delay time and passing a waiting loop (count result) for a length of time (step 407); sequentially sampling and storing the sequential data bits (step 4 08), Make sure to sample and store 8 data bits (step 409); finally, according to the initialization, set (locating) — Inter Character Regi zon (step 41 0), ', where' the character spacing is Based on the initialization result, set the width to one, one, half, or two bit frames to repeat the next data flow. Figure 5 is a schematic diagram of the sampling clock drift generated by the receiving end in an asynchronous transmission system, where S1 ~ S8 represent 8 bit frames, and one bit frame illustrates the sampling clock drift state. After the terminal detects a falling edge signal 500, it interrupts the receiving end. This hum, the receiving end starts counting and generates a response time 5 丨 enters the count, that is, a first delay time 520, When the real time of counting starts from 53 to the receiving end detects a rising edge signal of 54, a start bit is ended. At this time, the counting ends after a reaction time, which results in a first: delay = = 550, finish the receiving end count of 56. One of the time frame width of a bit frame is 5 7 0. After drifting, the time width of the real bit frame is-a delay time) + (-bit frame) + (Second delay time). Fig. 6 is a schematic diagram of a 2 clock drift generated by time variation in an asynchronous transmission system. 'After the above description, * a one-element frame will cause a delay phenomenon.' Therefore, the central position of the in-place element frame is 600. Words, every

532021 V. Description of the invention (6)-*-After one bit frame, a delay time of 61 ° and a waiting loop of 6 2 0 will be added. Therefore, as far as the second bit frame is concerned, there is no time compensation. (compensation) time t (s2) = (sl + wait loop + delay time), for the 8th bit frame, time t (s8) without time compensation (c〇inpensati〇n) = (sl + Waiting loop + 7x delay time), where the ideal error and difference margin 630 is half of the bit frame. If the delay time of 7 χ is greater than half of the bit frame, errors will occur. Figure 7 is a schematic diagram of the drift margin and pre-sampling technology in an asynchronous transmission system. The figure shows that after 7 delay times, the cumulative error time of nearly 40% at the 8th bit frame (located in the 8th bit) 90% of the starting point of the bit frame), and the pre-sampling technology is used to compensate 20% of the compensation time before the center position of the bit frame, so that the sampling time of the 8th bit frame is close to the 8th bit 20% of the center position of the element frame, making its drift margin closer to the center position of the bit frame. Therefore, it is better to use the pre-sampling time = (counting result / 2)-(counting result X 20%) . The counting result is the sampling period of the bit frame. [Simulation test of the present invention] FIG. 8 is a waveform diagram of the accumulated delay time measured by the present invention at an 8 MHz processing rate, illustrating that the first sampling pulse is generated at 52 · 33us at the beginning of the bit frame. At 8 bits, the accumulated delay time is 58.32us at the beginning of the bit frame. Therefore, it means that the accumulated delay time can be cancelled before the next starting bit. FIG. 9 is a waveform diagram of the sampling time calibration method for the different drift amount of the first bit frame according to the method proposed in the present invention.

Page 10 532021 V. Description of the invention (7) The amount of shift (4MHz) and + 50% drift (12MHz) respectively explain the state of time error. Take 9600Hz for example. Each bit-frame is equivalent to 1/960 0 = 1 04us, and the center position of the bit-frame is 104us / 2 = 52us. Sampling time is 52.33us' Therefore, the error = (52.33-52) / 52 = (+ 0.6%); the sampling time of the 4MHz processing rate is 53 · 36us, so the error = (53 · 36-52) / 52 = ( + 2.6%); The sampling time for the 12MHz processing rate is 52.39us, so the error = (52.39-52) / 52 = (+ 0.75%).

Figure 10 is a waveform diagram of the cumulative delay time of the method of the present invention for different drift amounts of the 8th bit frame. The sampling time of the 8MHz processing rate is 58.32US, so the error = (58 · 32 -52) / 52 = (+ 1 2%); the sampling time of the 4MHz processing rate is 64.56us, so the error = (64 · 56-52) / 52 = (+ 24%); the sampling time of the 12MHz processing rate is 51.4〇us, so , Error = (5 1.40-52) / 52 = (-1%). Although 'according to Figure 9 and Figure 10, although there is an error of up to + 24%, it is still within the allowable error range ^ Figure 11 is the method proposed in the present invention to cancel different drift amounts The cumulative delay time waveform, the reset time (re-timing) of the 8MHz processing rate is 51.95us, so the error = (51, 95-5 2) / 52 = (-〇 · 0 9%); the 4MHz processing rate The weight is 51.88us, so the error = (51 · 88-52) / 52 = (-〇 · 2%) The sampling time of the processing rate is 51 · 99us, so the error setting time is ϊ 12MHz 4

= (51,99-52) / 52 = (-0.02%). Therefore, the method of the present invention can reset the previous 24% error to close to 0%.

Page 11 532021 V. Description of the invention (8) Finally, Fig. 12 is a schematic diagram for verifying the feasibility of the present invention using a ^ Bit Error Rate Test (BERT) program. In this test, a " The quick brown fox jumps over the lazy dog 丨, zigzag string, test the receiving result that the receiving end responds to the sending end. Due to the limitation of the buffering size of the receiving end, the message presented in the figure contains two strings, but this The verification results still show the feasibility of the method proposed by the present invention, and indeed have good results. [Advantages of the present invention] (1) No universal asynchronous transmission and reception transmitter (U ART) such as an accurate clock generator or frequency locking device is needed, and the purpose of automatic calibration and synchronization can be achieved, and the transmission device can be reduced. Manufacturing cost; (2) In an asynchronous communication transmission system, before the next start bit, only a single signal bit width needs to be automatically calibrated once to eliminate the accumulated marginal error (marr err); and ( 3) Applicable to any transmission rate in asynchronous communication transmission system (1) Buckle (1 Although the present invention is used to define the present invention as compared to the foregoing, any familiarity and scope can be used as a guarantee for compliance. The preferred embodiment of the application is disclosed as above, but it is not the artist, without departing from the modifications and retouching of the present invention, so the definition of the scope of the present invention shall prevail.

532021 The simple description of the detailed content and technology of the present invention will be described in conjunction with the drawings: [Simplified description of the drawings] 'Figure 1 is a schematic diagram of a conventional point-to-point asynchronous transmission system; Figure 2 is a waveform diagram of the bit frame of the IEEE-232 protocol standard; Figure 3 is a waveform diagram of a sampling pulse that simulates a data reception; Figure 4 is a main flowchart of the automatic calibration and synchronization of the present invention; Fig. 5 is a schematic diagram of sampling clock drift generated by a receiver in an asynchronous transmission system; Fig. 6 is a schematic diagram of sampling clock drift generated by a time variation in an asynchronous transmission system; and Fig. 7 is an asynchronous transmission Schematic diagram of the drift margin and pre-sampling technology in the system; Figure 8 is a waveform diagram of the cumulative delay time measured at an 8MHz transfer rate according to the present invention; Figure 9 is the difference between the method according to the present invention and the bit element frame Drift amount calibration sampling time waveform diagram; Figure 10 is the cumulative delay time waveform diagram of the method proposed in the present invention for different drift amounts of the 8th bit frame; Figure 11 is the present invention Method cancel integrated waveform diagram for different delay time drift amount; and

Figure 12 shows the use of a one-bit error rate tears. 丨 Xi Guang D · F D μ Bit Error Rate

Test; BERT) program to verify the feasibility of the invention. 【Symbol Description】 ~

532021 " 丨 _ " .... " 1 Schematic description 100 sender (initiator) 120 receiver (target) 20 0nU " character frame 21 0 start bit 2 2 0 bit frame 2 3 0 End interval 3 0 0 Simulates a data receiving sampling pulse 310 Falling edge signal 3 2 0 Start bit

330 Least Significant Bit (LSB) 340 Most Significant Bit (MSB) 350 rising edge signal 3 6 0 Stop bit 3 70 Time interval / Step 40 0 Initialize a receiving end Step 401 of the system: The receiving end detects a start bit (fal 1 ing edge) signal and starts counting.

Step 402: The receiving end detects the rising edge signal of the START bit and ends counting. Step 403 stores the counting result. Step 404 sets a sampling pointer time length as (counting result / 2. Step 405 compensates for a delay time and passes a length of time that a wait loop is (count result / 2)

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The formula is briefly explained. Step 4 06 samples and stores the first data bit. Step 407 compensates for a delay time and passes a length of time that a wait loop is (counting result). Step 408 sequentially samples and stores the sequential data bits. Meta-step 409 determines to sample and store 8 data bits. Step 410 According to the initialization, locating-Inter Character Region 500 falling edge signal 51 0 response time 520 first delay time 5 3 0 start counting real time 540 rising edge signal 550 second delay time 560 end counting; 5 7 0 bit frame time width 580 real bit frame time width 600 bit center of the frame Position 6 1 0 delay time 6 2 0 waiting loop 630 error margin

Claims (1)

532021 6. Scope of patent application [Scope of patent application] The method for automatic calibration and synchronization in the digital asynchronous communication wheel system includes at least the following steps: 7 (a) Initializing a target system ; (B) the receiver detects a start bit (a falling edge of start signal) and starts counting; (c) the receiver detects a rising edge of a start bit Counting ends after the signal; (d) Store a counting result; (e) e Time length of a sampling index (sampHng p〇inter) is (counting result / 2); (f) Compensate for a delay time and elapse The waiting loop (wait ι〇〇ρ) is the time length of (count result / 2); (g) sample and save the first data bit; (h) compensate a delay time and pass a waiting loop (wait ι〇〇 ρ) is the time length of (counting result); (i) sequentially sampling and storing sequential data bits; (j) determining sampling and storing 8 data bits; (k) Set (iocating) -Inter Character Region according to the initialization; and repeat steps (b) to (k). 2. The method for automatic calibration and synchronization in a digital asynchronous communication transmission system as described in item 1 of the scope of patent application, wherein the digital asynchronous communication transmission system is suitable for point-to-point asynchronous Page 16 6. Applying for a patent Fan Gu transfer wheel system. 3. The method for automatic calibration and synchronization in a digital asynchronous communication transmission system as described in item 1 of the patent claim, which further includes a sender (ini ti at or) system. 4. The method for automatic calibration and synchronization in a digital asynchronous communication transmission system as described in item i of the scope of patent application, wherein the start bit 1 can be selected from any one of the asynchronous communication transmission protocol standards. 5. Apply to digital asynchronous communication as described in item 4 of the scope of patent application A method for automatic calibration and synchronization in a transmission system, wherein the asynchronous communication transmission protocol standard may be an IEEE-232 protocol standard. 6. The method for automatic calibration and synchronization in a digital asynchronous communication transmission system as described in item 1 of the scope of the patent application, wherein the distance is the width between two characters. This you horse