TW532021B - Automatic calibration and synchronization method applied in asynchronous communication transmission system - Google Patents
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Description
532021 五、發明說明(1) 【發明領域】 本發明係有關於一種應用於灰位非同步 (Asynchronous)通訊傳輸系統中自動校準(calibrati〇n) 及同步化(synchronization)的方法,特別是指一種不需 要通用非同步收發傳輸器(Universal Asynchr〇n〇us Receiver and Transmitter ;UART),或不具有精確時脈 (time-base)之接收端即可達到自動校準及同步化的 法0 【發明背景】 開β愈社φ 鞛由起始與終止位兀來表示資料傳輪的 開始與結束,且經由序列線路傳遞 丄上的,。般而言,非同步通訊的時 認Hr回:ί =時不須等待接收端(target)傳回確 伸是在非Η、丰w,所以擁有較佳的資料處理能力。 4一疋在非同步通訊中,發 確的時脈⑹e slice) ’以正必=持「精 非同步收發傳輪器(UART) , _ ,通用 鎖定裝置遂成為非精確的時脈產生器或頻率 裝置。成4㈣步通訊系統中保持精確的時脈常用之 然而,由於非同步收發傳輸器 由於非同步通訊的特性 RT)=過高,再者 速率(baud rate)相同, 確疋發送鳊與接收端的傳4 難以設定傳輪速率, 有盔硬體設備無法提供或 逆羊&成硬想的傳輸速率與真正的傳輸$ 532021532021 V. Description of the invention (1) [Field of the invention] The present invention relates to a method for automatic calibration and synchronization in a gray-level asynchronous communication transmission system, and particularly refers to a method A method that can achieve automatic calibration and synchronization without the need for a universal asynchronous receiver and transmitter (Universal Asynchrnousus Receiver and Transmitter; UART), or a receiver that does not have a precise time-base Background] Kai βyushe φ 鞛 represents the beginning and end of the data transfer wheel by the start and end positions, and is transmitted on 丄 through a serial line. Generally speaking, for asynchronous communication, it is necessary to recognize Hr back: ί = when you do not need to wait for the receiving end (target) to return that the extension is non-standard and high-level, so it has better data processing capabilities. 4 In the asynchronous communication, the clock is sent accurately. (E slice) 'Really must = "fine asynchronous transmission and reception wheel (UART), _, the universal locking device has become an inaccurate clock generator or frequency. Device. It is common to maintain accurate clock in a 4-step communication system. However, because of the asynchronous communication (RT) = because of the characteristics of asynchronous communication, the transmission rate is too high, and the baud rate is the same. It ’s difficult to set the transmission speed. The helmeted hardware equipment ca n’t provide or reverse the transmission rate. The real transmission rate is $ 532021.
率不匹配的情況發生。 因此,一種不需非同步收發傳’輸器(UART),且能達到 自動校準及同步化的方法,遂成為一被關注的議題。 【發明之概述及目的】 本發明之主要目的在於一種不需要通用非同步收發傳 輸器(Universal Asynchronous Receiver andA rate mismatch occurs. Therefore, a method that does not require asynchronous transmit / receive transmitters (UARTs) and can achieve automatic calibration and synchronization has become a topic of concern. [Summary and Purpose of the Invention] The main purpose of the present invention is to provide a universal asynchronous receiver and receiver
Transmitter ; UART),或不具有精確時脈之接收端即可達 到自動校準及同步化的方法。 本發明所提之應用於數位非同步通訊傳輸系統中自動 校準及同步化的方法,至少包含下列步驟:(a)初始化一 _ 接收端(target)系統;(b)該接收端偵測到一開始位元 (START bit)之一下降緣(faiHng edge)信號後開始計 數’(c)該接收端彳貞測到該開始位元之一上升緣(rising edge)信號後結束計數;(d)儲存一計數結果;(e)設定一 取樣指標(sampling pointer)的時間長度為(計數結果 /2) ;(f)補償一延遲時間並經過一等待迴路(wait 1〇〇p) 為(計數結果/2)的時間長度;(g)取樣並儲存第1資料位 元;(h)補償一延遲時間並經過一等待迴路(wai七ι〇〇ρ)為 (計數結果)的時間長度;(i )依序取樣並儲存依序之資料 位元;(D確定取樣並儲存8個資料位元;(k)依據該初始 鲁 化’汉置(locating) — 字元間距(inter Character Region);及重複執行步驟(b)〜步驟(k)。 【發明之詳細說明】 本發明提出一種應用於數位非同步通訊傳輸系統中自Transmitter; UART), or a receiver that does not have an accurate clock can achieve automatic calibration and synchronization. The method for automatic calibration and synchronization applied in a digital asynchronous communication transmission system provided by the present invention includes at least the following steps: (a) initializing a target system; (b) the receiving end detects a Start counting after a falling edge (faiHng edge) signal of the START bit ('c) The receiver end counts after detecting a rising edge signal of the starting bit; (d) Store a counting result; (e) Set the time length of a sampling pointer to (counting result / 2); (f) Compensate for a delay time and pass a waiting loop (wait 100p) to (counting result) / 2) the length of time; (g) the first data bit is sampled and stored; (h) the length of time that compensates for a delay time and passes through a waiting loop (wai) (count result); (i) ) Sequentially sample and store sequential data bits; (D determines to sample and store 8 data bits; (k) based on the initial Luhuan 'locating' — inter character region; and Repeat steps (b) to (k). [Details of the invention The present invention provides a bright applied to digital transmission systems asynchronous communication from
第6頁 532021 五、發明說明(3) 動校準及同步化的方法,係以點對點(p〇int t〇 p〇int)的 非同步傳輸系統中之IEEE - 232協定,標準為較佳實施例,說 明本發明之可行性,然非以用於限定本發明之應用範圍。 其中,第1圖為習知點對點(point t〇 p〇int)的非同步傳 輸系統示意圖,依據IEEE-232協定標準,當一發送端 (initiator) 1〇〇欲傳遞一筆資料至一接收端(target)12() 時,發送端1〇〇需事先定義一開始位元(START bi t)並發送 至接收端1 2 0,當接收端1 2 0偵測到一開始位元之下降緣 (falling edge)信號後’表示接收端12〇將與發送端1〇〇同 步化,並等待偵測到開始位元之上升緣(rising edge)信 號後準備接收資料,在此必須強調,本發明之方法必須建 立在發送端100需具有穩態時脈(time base)的基礎上。 第2圖為IEEE-2 32協定標準之位元訊框波形圖,係透 過有線傳輸之非同步發射訊號,並以96〇〇Hz的頻率進行傳 送。一般而言,接收端利用16倍頻率以針對待接收資料進 行取樣,若以傳輸速率(baud rate)為9600Hz為例,須 9600 X 1 6 = 1 53· 6KHz的取樣頻率,本發明提出一較佳實施 例’採用U子元當作發送端之傳送字元,原因在於"u"字 元的二進位碼為”01010101 ”,其透過傳輸線傳遞訊號具有 較佳的資料通道平衡特性,如” u”字元以9600Hz的頻率進 行傳送時,每一位元訊框(bit-frame)相當於 l/9600 = 104us ;若以4800Hz的頻率進行傳送時,每一位元 訊框(bit-f raine)相當於1 /480 0 = 20 8us。而一個完整的"u,, 字元訊框20 0具有一104us的開始位元21〇,且每_位元訊Page 6 532021 V. Description of the invention (3) The method of dynamic calibration and synchronization is based on the IEEE-232 protocol in a point-to-point (pint tο pint) asynchronous transmission system. The standard is a preferred embodiment. , To illustrate the feasibility of the present invention, but not to limit the scope of application of the present invention. Among them, Fig. 1 is a schematic diagram of a conventional point-to-point asynchronous transmission system. According to the IEEE-232 protocol standard, when an initiator 100 wants to transmit a piece of data to a receiver ( target) 12 (), the transmitting end 100 must define a start bit (START bit) in advance and send it to the receiving end 120. When the receiving end 1 2 0 detects a falling edge of the starting bit ( "falling edge" signal indicates that the receiving end 120 will synchronize with the transmitting end 100, and is ready to receive data after detecting the rising edge signal of the start bit. Here it must be emphasized that the present invention The method must be based on that the sending end 100 needs to have a steady-state time base. Figure 2 is a bit frame waveform diagram of the IEEE-2 32 protocol standard, which is a non-synchronous transmission signal transmitted through a wire and transmitted at a frequency of 9600 Hz. Generally speaking, the receiving end uses 16 times the frequency to sample the data to be received. If the baud rate is 9600Hz as an example, a sampling frequency of 9600 X 1 6 = 1 53 · 6KHz is required. The preferred embodiment 'uses the U sub-element as the transmission character of the transmitting end, because the binary code of the "u" character is "01010101", and the signal transmitted through the transmission line has better data channel balance characteristics, such as "" When the character "u" is transmitted at a frequency of 9600Hz, each bit-frame is equivalent to 1/9600 = 104us; if transmitted at a frequency of 4800Hz, each bit-frame (bit-f raine) is equivalent to 1/480 0 = 20 8us. And a complete " u ,, character frame 20 0 has a 104us start bit 21, and every _ bit information
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:220具有l〇4US的時間間距,圖中更顯示一具有mus的 子元間距(Inter Character Region)結束區間 230。 第^圖為模擬一資料接收之取樣脈衝之波形圖,就較 佳之穩態取樣而言,取樣脈衝係發生在每一位元訊框的中 央位置,亦即l〇4/2 = 52us間距,實際上,取樣脈衝可能不 存在每一位元訊框的中央位置,如果接收端具有一精確的 ♦ 時脈或頻率機制,則取樣間距是很容易達到的;相對地, 如果接收端不具有一精確的時脈或頻率機制,則取樣間距 是很難以達到的。圖中所示,模擬一資料接收之取樣脈衝 300係發生在每一位元訊框的中央位置,其中,當接收端 _ 摘測到一下降緣(falling edge)信號310後,中斷接收端 並啟始一開始位元320,緊接著第}位元(bit丨)之最低效 位元(Least Significant Bit ;LSB)330 至第 8 位元(bit 8)之最咼效位元(Most Significant Bit ;MSB)340,直到 接收端偵測到一上升緣(rising edge)信號35〇後,結束一 終止位疋360 ’由於每一位元訊框具有1〇4113的時間間距, 因此8個位元具有i〇4usx 8 = 832us的時間間距370。 第4圖為本發明之自動校準及同步化的主要流程圖, 首先初始化一接收端系統(步驟4〇〇 );當接收端偵測到一 開始位元(START bit)之下降緣(falling edgeMf號後開 _ 始計數(步驟401);當接收端偵測到該開始位元(START bit)之上升緣(rising edge)信號後結束計數(步驟4〇2); 接著儲存計數結果(步驟403);並設定一取樣指標 (samp 1 ing pointer)的時間長度為(計數結果/2)(步驟: 220 has a time interval of 104US, and the figure also shows a sub-interval (Inter Character Region) end interval 230 with mus. Figure ^ is a waveform diagram of a sampling pulse that simulates a data reception. For better steady-state sampling, the sampling pulse occurs at the center of each bit frame, that is, 104/2 = 52us spacing. In fact, the sampling pulse may not exist in the center position of each bit frame. If the receiving end has an accurate clock or frequency mechanism, the sampling interval is easy to reach. In contrast, if the receiving end does not have a With precise clock or frequency mechanisms, the sampling interval is difficult to achieve. As shown in the figure, the sampling pulse 300 that simulates a data reception occurs at the center of each bit frame. When the receiving end _ picks up a falling edge signal 310, it interrupts the receiving end and The first bit 320 is the beginning, followed by the Least Significant Bit (LSB) of the} th bit (bit 丨) 330 to the Most Significant Bit of the 8th bit (bit 8). ; MSB) 340, until the receiving end detects a rising edge signal 35 °, ending a stop bit 360 'because each bit frame has a time interval of 10413, so 8 bits With a time interval of 〇4usx 8 = 832us 370. FIG. 4 is a main flowchart of automatic calibration and synchronization of the present invention. First, a receiving end system is initialized (step 400); when the receiving end detects a falling edge of a START bit (falling edgeMf) After the number, start counting (step 401); when the receiving end detects the rising edge signal of the START bit, the counting ends (step 4202); then the counting result is stored (step 403) ); And set the time length of a sampling indicator (samp 1 ing pointer) to (count result / 2) (step
第8頁 532021Page 532021
404) ’並補償一延遲時間並經過一等待迴路(wait ι〇〇ρ) 為(計數結果/2)的時間長度(步驟4·〇5);取樣並儲存第1資 料位元(步驟4 0 6 );接著補償一延遲時間並經過一等待迴 路(wait loop)為(計數結果)的時間長度(步驟4〇7);依序 取樣並儲存依序之資料位元(步驟4 〇8),確定取樣並儲存8 個資料位元(步驟409);最後,依據該初始化,設置 (locating) — 字元間距(Inter Character Regi〇n)(步驟 41 0 )、’,其中’該字元間距係以初始化結果,設置為一個、 一個半或是二個位元訊框寬度,以重複進行下一資 流程。 第5圖為非同步傳輸系統中藉由接收端所產生之取樣 時脈漂移示意圖,其中S1〜S8代表8個位元訊框,以其中一 位元訊框說明取樣時脈漂移狀態,當接收端偵測到一下降 緣(falling edge)信號5〇〇後,中斷接收端,此哼,接收 端開始計數,並產生一反應時間5丨〇進入計數,亦即產生 一第一延遲時間520,當開始計數真正時間53〇至接收端偵 測到一上升緣(rising edge)信號54〇後,結束一開始位 疋,此時,經一反應時間結束計數,亦即產生一第:延遲 = =550,完成接收端結束計數56〇,其中一位元訊框的時 a寬度5 7 0經漂移後,真正的位元訊框的時間寬度為— 一延遲時間)+(—位元訊框)+ (第二延遲時間)。 第6圖為非同步傳輸系統中藉由時間變動所產生 2時脈漂移示意圖’經由上述說明,*一位元訊框會產生 延遲現象’因此’就位元訊框之中央位置6〇〇而言,每404) 'and compensate a delay time and pass a waiting loop (wait ι〇〇ρ) for a time length of (count result / 2) (step 4 · 05); sample and store the first data bit (step 4 0 6); then compensating for a delay time and passing a waiting loop (count result) for a length of time (step 407); sequentially sampling and storing the sequential data bits (step 4 08), Make sure to sample and store 8 data bits (step 409); finally, according to the initialization, set (locating) — Inter Character Regi zon (step 41 0), ', where' the character spacing is Based on the initialization result, set the width to one, one, half, or two bit frames to repeat the next data flow. Figure 5 is a schematic diagram of the sampling clock drift generated by the receiving end in an asynchronous transmission system, where S1 ~ S8 represent 8 bit frames, and one bit frame illustrates the sampling clock drift state. After the terminal detects a falling edge signal 500, it interrupts the receiving end. This hum, the receiving end starts counting and generates a response time 5 丨 enters the count, that is, a first delay time 520, When the real time of counting starts from 53 to the receiving end detects a rising edge signal of 54, a start bit is ended. At this time, the counting ends after a reaction time, which results in a first: delay = = 550, finish the receiving end count of 56. One of the time frame width of a bit frame is 5 7 0. After drifting, the time width of the real bit frame is-a delay time) + (-bit frame) + (Second delay time). Fig. 6 is a schematic diagram of a 2 clock drift generated by time variation in an asynchronous transmission system. 'After the above description, * a one-element frame will cause a delay phenomenon.' Therefore, the central position of the in-place element frame is 600. Words, every
532021 五、發明說明(6) --*- 經過一位元訊框就會增加一延遲時間61〇與一等待迴路 6 2 0,因此,就第2位元訊框而言,未經時間補償 (compensation)的時間t(s2) = (sl +等待迴路+延遲時間), 至第8位元訊框而言,未經時間補償(c〇inpensati〇n)的時 間t(s8) = (sl+等待迴路+ 7x延遲時間),其中,理想的誤、 差邊際630為位元訊框的一半,如果7 χ延遲時間大j於位元 訊框的一半,則會導致錯誤發生。 第7圖為非同步傳輸系統中漂移邊際與預先取樣技術 示意圖,圖中顯示經7個延遲時間後,在第8個位元訊框 時’產生將近40%的累計誤差時間(位於第8個位元訊框起 始點的90%),經預先取樣技術以位元訊框的中央位置前 2 0 %補償時間進行補償,使第8個位元訊框的取樣時間接近 在第8個位元訊框的中央位置的2〇%,使其漂移邊際更靠近 位元訊框的中央位置,因此,較佳者,以預先取樣時間 =(計數結果/2)-(計數結果X 20%)。其中,計數結果為位 元訊框的取樣週期。 【本發明之模擬測試】 第8圖為本發明以8MHz處理速率所測出的累計延遲時 間波形圖,說明第1取樣脈衝產生在該位元訊框啟始的52· 33us,當接收到第8位元時,所累計延遲時間產生在該位 元訊框啟始的58.32us,因此,代表著所累計延遲時間能 在下一開始位元前取消。 第9圖為本發明所提之方法針對第1位元訊框之不同漂 移量校準取樣時間波形圖,其中以8MHz處理速率、_50%漂532021 V. Description of the invention (6)-*-After one bit frame, a delay time of 61 ° and a waiting loop of 6 2 0 will be added. Therefore, as far as the second bit frame is concerned, there is no time compensation. (compensation) time t (s2) = (sl + wait loop + delay time), for the 8th bit frame, time t (s8) without time compensation (c〇inpensati〇n) = (sl + Waiting loop + 7x delay time), where the ideal error and difference margin 630 is half of the bit frame. If the delay time of 7 χ is greater than half of the bit frame, errors will occur. Figure 7 is a schematic diagram of the drift margin and pre-sampling technology in an asynchronous transmission system. The figure shows that after 7 delay times, the cumulative error time of nearly 40% at the 8th bit frame (located in the 8th bit) 90% of the starting point of the bit frame), and the pre-sampling technology is used to compensate 20% of the compensation time before the center position of the bit frame, so that the sampling time of the 8th bit frame is close to the 8th bit 20% of the center position of the element frame, making its drift margin closer to the center position of the bit frame. Therefore, it is better to use the pre-sampling time = (counting result / 2)-(counting result X 20%) . The counting result is the sampling period of the bit frame. [Simulation test of the present invention] FIG. 8 is a waveform diagram of the accumulated delay time measured by the present invention at an 8 MHz processing rate, illustrating that the first sampling pulse is generated at 52 · 33us at the beginning of the bit frame. At 8 bits, the accumulated delay time is 58.32us at the beginning of the bit frame. Therefore, it means that the accumulated delay time can be cancelled before the next starting bit. FIG. 9 is a waveform diagram of the sampling time calibration method for the different drift amount of the first bit frame according to the method proposed in the present invention.
第10頁 532021 五、發明說明(7) 移量(4MHz)及+ 5 0%漂移量(12MHz)分別說明時間誤差狀 態。其中以9600Hz的頻率進行傳送為例,每一位元訊框 (bit-frame)相當於l/960 0 = 1 04us,其位元訊框的中央位 置為104us/2 = 52us,8MHz處理速率的取樣時間為 52.33us ’ 因此,誤差= (52.33 - 52 )/52 = ( + 0.6%) ;4MHz 處 理速率的取樣時間為53· 36us,因此,誤差 = (53·36-52)/52 = ( + 2·6%) ;12MHz處理速率的取樣時間為 52.39us,因此,誤差= ( 52.39-52 )/52 = ( + 0.75%)。Page 10 532021 V. Description of the invention (7) The amount of shift (4MHz) and + 50% drift (12MHz) respectively explain the state of time error. Take 9600Hz for example. Each bit-frame is equivalent to 1/960 0 = 1 04us, and the center position of the bit-frame is 104us / 2 = 52us. Sampling time is 52.33us' Therefore, the error = (52.33-52) / 52 = (+ 0.6%); the sampling time of the 4MHz processing rate is 53 · 36us, so the error = (53 · 36-52) / 52 = ( + 2.6%); The sampling time for the 12MHz processing rate is 52.39us, so the error = (52.39-52) / 52 = (+ 0.75%).
第10圖為本發明所提之方法針對第8位元訊框之不同 漂移量累計延遲時間波形圖,8MHz處理速率的取樣時間為 58.32US,因此,誤差= (58·32 一 52 )/52 = ( + 1 2%) ;4MHz 處理 速率的取樣時間為64.56us,因此,誤差 = (64· 56-52)/52 = ( + 24%) ; 12MHz處理速率的取樣時間為 51.4〇us,因此,誤差= (5 1.40-52 )/52 = (-1%)。 縱然’依據第9圖及第1〇圖所示,雖有最高達+ 24%的誤差 存在,但仍然在允許的誤差範圍内^ 第11圖為本發明所提之方法針對不同漂移量進行取消 累計延遲時間波形圖,8MHz處理速率的重置時間 (re-timing)為 51.95us,因此,誤差 = ( 51, 95-5 2 )/52 = (-〇· 0 9%) ; 4MHz 處理速率的重 51.88us,因此,誤差= (51·88-52 )/52 = (-〇·2%) 理速率的取樣時間為51· 99us,因此,誤差 置時間為ϊ 12MHz 4Figure 10 is a waveform diagram of the cumulative delay time of the method of the present invention for different drift amounts of the 8th bit frame. The sampling time of the 8MHz processing rate is 58.32US, so the error = (58 · 32 -52) / 52 = (+ 1 2%); the sampling time of the 4MHz processing rate is 64.56us, so the error = (64 · 56-52) / 52 = (+ 24%); the sampling time of the 12MHz processing rate is 51.4〇us, so , Error = (5 1.40-52) / 52 = (-1%). Although 'according to Figure 9 and Figure 10, although there is an error of up to + 24%, it is still within the allowable error range ^ Figure 11 is the method proposed in the present invention to cancel different drift amounts The cumulative delay time waveform, the reset time (re-timing) of the 8MHz processing rate is 51.95us, so the error = (51, 95-5 2) / 52 = (-〇 · 0 9%); the 4MHz processing rate The weight is 51.88us, so the error = (51 · 88-52) / 52 = (-〇 · 2%) The sampling time of the processing rate is 51 · 99us, so the error setting time is ϊ 12MHz 4
=(51,99-52)/52 = (-〇.〇2%)。因此,藉由本發明所提之方 法’可將先前24%的誤差重置接近〇 %。= (51,99-52) / 52 = (-0.02%). Therefore, the method of the present invention can reset the previous 24% error to close to 0%.
第11頁 532021 五、發明說明(8) 最後,第1 2圖為利用^一位疋錯誤率測試(Bit Error Rate Test ; BERT)程式驗證本發明的可行性示意圖,此測試中 以一"The quick brown fox jumps over the lazy dog丨, 之字串,測試接收端所回應給發送端之接收結果,由於接 收端緩衝大小的限制’因此圖中所呈現的訊息包含二個字 串,但此驗證結果仍說明本發明所提之方法的可行性,確 實有不錯的結果。 【本發明之優點】 (1)不需要如精確的時脈產生器或頻率鎖定裝置之通 用非同步收發傳輸器(U ART),即可以達到自動校 準及同步化的目的,可降低傳輸裝置之製造成 本; (2 )在非同步通訊傳輸系統中,下一開始位元前,只 須就單一信號位元寬度做一次自動校準,即可消 除累積的邊際錯誤(margin err〇r);及 (3)適用於非同步通訊傳輸系統中任何傳輸速率(1)扣(1 雖然本發明以前述之較 用以限定本發明,任何熟習 精神和範圍内,當可作些許 保遵範圍當視後附之申請專 佳實施例揭露如上,然其並非 此技藝者,在不脫離本發明之 之更動與潤飾,因此本發明之 利範圍所界定者為準。Page 11 532021 V. Description of the invention (8) Finally, Fig. 12 is a schematic diagram for verifying the feasibility of the present invention using a ^ Bit Error Rate Test (BERT) program. In this test, a " The quick brown fox jumps over the lazy dog 丨, zigzag string, test the receiving result that the receiving end responds to the sending end. Due to the limitation of the buffering size of the receiving end, the message presented in the figure contains two strings, but this The verification results still show the feasibility of the method proposed by the present invention, and indeed have good results. [Advantages of the present invention] (1) No universal asynchronous transmission and reception transmitter (U ART) such as an accurate clock generator or frequency locking device is needed, and the purpose of automatic calibration and synchronization can be achieved, and the transmission device can be reduced. Manufacturing cost; (2) In an asynchronous communication transmission system, before the next start bit, only a single signal bit width needs to be automatically calibrated once to eliminate the accumulated marginal error (marr err); and ( 3) Applicable to any transmission rate in asynchronous communication transmission system (1) Buckle (1 Although the present invention is used to define the present invention as compared to the foregoing, any familiarity and scope can be used as a guarantee for compliance. The preferred embodiment of the application is disclosed as above, but it is not the artist, without departing from the modifications and retouching of the present invention, so the definition of the scope of the present invention shall prevail.
532021 囷式簡單說明 有關本發明之詳細内容及技術,茲就配合圖式說明如下: 【圖式簡單說明】 ’ 第1圖為習知點對點(p〇int to point)的非同步傳輸 系統示意圖; 第2圖為IEEE-232協定標準之位元訊框波形圖; 第3圖為模擬一資料接收之取樣脈衝之波形圖; 第4圖為本發明之自動校準及同步化的主要流程圖; 第5圖為非同步傳輸系統中藉由接收端所產生之取樣 時脈漂移示意圖; 第6圖為非同步傳輸系統中藉由時間變動所產生之取 樣時脈漂移示意圖; 第7圖為非同步傳輸系統中漂移邊際與預先取樣技術 示意圖; 第8圖為本發明以8MHz傳輪速率所測出的累計延遲時 間波形圖; 第9圖為本發明所提之方法針對第丨位元訊框之不同漂 移量校準取樣時間波形圖; 第10圖為本發明所提之方法針對第8位元訊框之不同 漂移量累計延遲時間波形圖; 第11圖為本發明所提之方法針對不同漂移量進行取消 累計延遲時間波形圖;及532021 The simple description of the detailed content and technology of the present invention will be described in conjunction with the drawings: [Simplified description of the drawings] 'Figure 1 is a schematic diagram of a conventional point-to-point asynchronous transmission system; Figure 2 is a waveform diagram of the bit frame of the IEEE-232 protocol standard; Figure 3 is a waveform diagram of a sampling pulse that simulates a data reception; Figure 4 is a main flowchart of the automatic calibration and synchronization of the present invention; Fig. 5 is a schematic diagram of sampling clock drift generated by a receiver in an asynchronous transmission system; Fig. 6 is a schematic diagram of sampling clock drift generated by a time variation in an asynchronous transmission system; and Fig. 7 is an asynchronous transmission Schematic diagram of the drift margin and pre-sampling technology in the system; Figure 8 is a waveform diagram of the cumulative delay time measured at an 8MHz transfer rate according to the present invention; Figure 9 is the difference between the method according to the present invention and the bit element frame Drift amount calibration sampling time waveform diagram; Figure 10 is the cumulative delay time waveform diagram of the method proposed in the present invention for different drift amounts of the 8th bit frame; Figure 11 is the present invention Method cancel integrated waveform diagram for different delay time drift amount; and
第1 2圖為利用一位元錯誤率泪丨丨兮广D · F D μ 千州试(Bit Error RateFigure 12 shows the use of a one-bit error rate tears. 丨 Xi Guang D · F D μ Bit Error Rate
Test ;BERT)程式驗證本發明的可行性示音圖。 【符號說明】 〜Test; BERT) program to verify the feasibility of the invention. 【Symbol Description】 ~
532021 "丨_" .…"1 圖式簡單說明 100 發送端(initiator) 120 接收端(target) 20 0nU"字元訊框 21 0開始位元 2 2 0位元訊框 2 3 0結束區間 3 0 0模擬一資料接收之取樣脈衝 310 下降緣(falling edge)信號 3 2 0開始位元532021 " 丨 _ " .... " 1 Schematic description 100 sender (initiator) 120 receiver (target) 20 0nU " character frame 21 0 start bit 2 2 0 bit frame 2 3 0 End interval 3 0 0 Simulates a data receiving sampling pulse 310 Falling edge signal 3 2 0 Start bit
330 最低效位元(Least Significant Bit ;LSB) 340 最高效位元(Most Significant Bit ;MSB) 350上升緣(rising edge)信號 3 6 0終止位元 3 70時間間距/ 步驟40 0初始化一接收端系統 步驟401接收端偵測到一開始位元(START bit)之丁降 緣(f al 1 ing edge)信號後開始計數330 Least Significant Bit (LSB) 340 Most Significant Bit (MSB) 350 rising edge signal 3 6 0 Stop bit 3 70 Time interval / Step 40 0 Initialize a receiving end Step 401 of the system: The receiving end detects a start bit (fal 1 ing edge) signal and starts counting.
步驟402接收端偵測到該開始位元(START bit)之上升 緣(rising edge)信號後結束計數 步驟403儲存計數結果 步驟404設定一取樣指標(sampling pointer)的時間 長度為(計數結果/2) 步驟405補償一延遲時間並經過一等待迴路(wait loop)為(計數結果/2)的時間長度Step 402: The receiving end detects the rising edge signal of the START bit and ends counting. Step 403 stores the counting result. Step 404 sets a sampling pointer time length as (counting result / 2. Step 405 compensates for a delay time and passes a length of time that a wait loop is (count result / 2)
第14頁 532021Page 532021
囷式簡單說明 步驟4 06取樣並儲存第1資料位元 步驟407補償一延遲時間並經過一等待迴路(wait loop)為(計數結果)的時間長度 步驟408依序取樣並儲存依序之資料位元 步驟409確定取樣並儲存8個資料位元 步驟410依據該初始化,設置(locating) —字元間距 (Inter Character Region) 500 下降緣(falling edge)信號 51 0反應時間 520第一延遲時間 5 3 0開始計數真正時間 540上升緣(rising edge)信號 550第二延遲時間 560結束計藥; 5 7 0位元訊框的時間寬度 580真正的位元訊框的時間寬度 600位元訊框之中央位置 6 1 0延遲時間 6 2 0等待迴路 630誤差邊際The formula is briefly explained. Step 4 06 samples and stores the first data bit. Step 407 compensates for a delay time and passes a length of time that a wait loop is (counting result). Step 408 sequentially samples and stores the sequential data bits. Meta-step 409 determines to sample and store 8 data bits. Step 410 According to the initialization, locating-Inter Character Region 500 falling edge signal 51 0 response time 520 first delay time 5 3 0 start counting real time 540 rising edge signal 550 second delay time 560 end counting; 5 7 0 bit frame time width 580 real bit frame time width 600 bit center of the frame Position 6 1 0 delay time 6 2 0 waiting loop 630 error margin
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