TW531972B - Embedded built-in self-test core and its approach for digital-to-analog converters - Google Patents

Abstract

This invention ""embedded built-in self-test core and its approach for digital-to-analog converters"" can test the parameters of offset error, gain error, differential nonlinearity, and integral nonlinearity in DACs (digital-to-analog converters) that are deeply embedded in SoC (system on a chip) environment. The main technology of this invention is to apply a negative ramp or expected value of voltages for comparisons with the outputs of DAC-under-test. On the other hand, the main characteristic of the invention is to start with the MSB down to the LSB with the negative ramp when measuring the INL, and compare the outputs of DAC under test with expected range.

Description

531972)

V. Description of the invention (1) Background of the invention: The "digital built-in self-test device and test method of the digital-to-analog converter" is a single-chip system built on millions of logic gates. (RS〇C ), A self-testing device and method for designing a log-to-analog converter (DAC) to measure four parameter values to offset error, gain error, differential nonlinear error, and integrated nonlinear error are designed. '' Due to the rapid evolution of semiconductor process technology, # 100 million transistors are built HH C3 1 J 1 port Γ-1. «The era of single-chip systems (SOC) produced on an earlier wafer has arrived. The original 7L pieces on the PC board became the core of the single-chip system (^ ㈣). In the tens of millions of transistor towels, the car driver is difficult to control and observe from the outside, so it is the single-chip system. Board level measurement and measurement are more difficult. Some data show that the total area of the single-chip, single-chip system is 20 ° / ◦ hybrid circuit, but it takes 70% of the test time. 7 Moreover, the high-speed test equipment required is very expensive, in addition to the load effect (a〇adlng Effect), and because of the pins and the winding itself

There are effects of resistance: valley, inductance, etc. The measured parameter values are not accurate and are for reference only. This invention g | 7 # 4U

The recognition is to research the embedded self-test device and test method for the digital to analog car I T: ’in the chip system. In order to reduce the cost of intelligence testing (reducing testing time and reducing the demand for testing machines and equipment), Xiaoganecki controls and observes nodes to increase testing accuracy and accuracy. For more details about the prior art, please refer to references [1 ~ 5].

531972 * > V. Description of the invention (2) '' Voltage comparison method [1-3], using resistor array method [4], and single-bit analog-to-digital converter and ramp voltage method [5]. For the ν-bit digital-to-analog conversion state, multiple accurate reference voltages require about 2 ν reference voltages. This method is impractical when N is large (see Reference [6], section 'I' for details). The problem with the resistor array method is the resistance matching. If it is not accurate, the accurate reference voltage is not accurate, and the error is large (for details, see reference [6], section 3.2). The problem with the single-bit analog-to-digital converter and ramp voltage method is the conversion of voltage to time measurement points, and under certain errors, 'important parameters will not be measured (for details, see reference [6], 3 · 3 Section). 'Thus', the present invention researches and designs a self-contained self-test device and test method for digital-to-analog converters that are integrated in the CMOS technology compared to the previous technology. References Π] K. Arabi, Beta Kaminska, and J. Rzeszut, " BIST for D / A and A / D Converters. In IEEE Design and Test of Computers, pages 40 -49, 1996.

[2] K. Arab i, B. Kaminska, and J. Rzeszut, n A New Built-In-Self-Test Approach for Digital-1〇-Analog and Analog-to-Digital Converters, 丨 丨 Proc. Of Int. Conf. Computer-Aided Design (ICCAD), pages 49 1-494, 1 9 94 ·

D: \ nthu \ patent \ ats01 \ ats01.ptd Page 6 531972 V. Description of the invention (3) [3] K. Arabi, B. Kaminska, and J. Rzeszut, " A Bu i 11-In-Se1f- Test Approach for Medium to High-Resolution Digital-t〇-Analog Converters,

Proc. Of the Third As i an i Test Sympos i um, pages 373-378, 1994.

[4] Y.-C. Wen and K.-J. Lee, " BIST Structure for DAC Testing, " Electronics Letters, 34 (12): pp. 1173-1174, June 1998.

[5] J.-L. Huang, C.-K. Ong, and K.-T. Cheng, " A BIST Scheme for On-Chip ADC and DAC Testing, "

Proc. Of Design, Automation and Test in Europe Conference and Exhibition, pages 216 -220, 2 0 0 0.

[6] Zhenghong Cai, n — Embedded built-in self-test method of digital-to-analog converter π Master's thesis, Department of Electrical Engineering, Tsinghua University, 2001. The present invention is a master's thesis of Mr. Cai Zhenghong, titled π-Embedded built-in self-test method of digital-to-analog converters. And published on November 20, 2001 in Kyoto, Japan ATS (Asian Test Symposium), titled nAn Embedded

Built-In-Self-Test Approach for Digital-to-Analog Converters 丨, ° According to Article 20 (1) of the Patent Law,

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"But those who applied for patents within 矣, months due to research, experiment, clothing, or use 'applied for 6 or 6 days before the date of publication or use, that is, the death of the husband is limited." Therefore, the case was filed in the Republic of China in 1990. Women lost their new sexuality in February. The content of the case of Xing Tian was applied for before the writing, so it was accepted by the International Conference on Ankuren, and in the Republic of China in 1990: 1: The practicality, progress, and novelty of the Mufu industry: Summary of the invention The main purpose is to reduce the cost of testing equipment and research and design embedded devices. I test the digital-to-analog converter device, that is, reduce the test time and reduce the test machine type self-testing digital-to-analog converter. The embedded built-in self-testing digital-to-analog conversion technology of the present invention is to provide a negative slope voltage. Or other known: = Qianlai and the digital-to-analog converter to be tested compare the four parameters (offset error, gain error, and non-linear error of the two-position to analog swivel) of the gross converter. The result is that the built-in built-in self-test digits of the present invention are converted to analog ... The main feature is that the switch is used to set the embedded self-test number to 1 and then test the self-test number.

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531972 V. Description of the invention (5) — ~ A one-to-analog converter device is connected to use the switch's cut 4 奂 to transform into the required test parameter device to test the required offset error, gain error, and differential non-linear error, respectively. , The non-linear error of the product and other four parameters. ^ ^ Inside the built-in self-test digital-to-analog converter device, another special feature of the analog-to-digital converter device; use known techniques to store the DAC output voltage under test as the previous value to the negative amplifier input of the difference amplifier, so as to communicate with Compare the output voltage to be tested next time. Another purpose of this document is to provide a test method for embedded self-testing digital-to-analog converter devices. The main technical content of the embedded self-testing digital-to-analog converter device test method of the present invention is to provide a test method that compares the negative slope voltage or other known expected voltage with the output of the digital-to-analog converter to be tested. The test method of the embedded self-testing digital-to-analog converter device of the present invention is characterized in that when measuring the non-linear error of the integrated product, it starts from the highest bit to the lowest bit, generates a desired value with a negative ramp voltage, and then measures the digital value to be measured. The conversion from the ratio to the output value is compared to obtain the digital-to-analog converter parameter value.

D: \ nthu \ patent \ ats01 \ ats01. Ptd page 9 — 531972 5. Description of the invention (6) Detailed description of the invention: The “embedded built-in self of the digital-to-analog converter” of the present invention The preferred embodiment of the "testing device and test method" is described below in order to explain the present invention in detail. It is hoped that the reviewing committee can easily understand the advantages, purposes, and characteristics of the present invention and obtain the invention patent at an early date. This is an embodiment of an embedded built-in self-test device of a digital-to-analog converter according to the present invention. The second figure is an embodiment of a differential non-linear error testing device in the present invention. The third figure is an embodiment of an offset error testing device in the present invention. The fourth figure is an embodiment of a gain error testing device in the present invention. The fifth figure is an embodiment of a self-test device in the present invention. The sixth figure is an embodiment of the integrated nonlinear error test device in the present invention.

D: \ nthu \ patent \ ats01 \ ats01.ptd Page 10 531972 V. Description of the invention (7) Component symbol description: 10 DAC under test 100 DAC normal input 11 White switch I 101 DAC output 12 Offset switch 102 DAC current output voltage 13 DAC switch two 103 DAC previous output voltage 14 DAC switch one 200 error amplifier one m out 15 measure gain switch 201 error amplifier one negative terminal% \ input 16 start signal 202 error amplifier one positive terminal input 17 Measure the DAC switch 300 error amplifier two output 18 Measure too low switch 301 error. Amplifier two negative terminal input 19 Measure too high switch 302 error amplifier two positive terminal m input 20 error amplifier one 400 error amplifier two output 21 reference voltage — 401 error Amplifier two negative terminal m into 22 reference voltage — 402 error amplifier two positive terminal into 23 reference voltage two 410 comparator one output 24 reference voltage four 411 comparator one negative terminal m into 30 error amplifier two 412 comparator one positive Input 40 Error amplifier three 420 Comparator two out 41 Comparator one 421 Comparator two negative terminal input 42 Comparator two 422 Comparator two positive terminal input 43 South speed comparator 430 Speed comparator out 50 Negative ramp voltage generator 431 South Speed comparator negative input 60 test pattern 432 Speed comparator positive input

D: \ nthu \ patent \ ats01 \ ats01.ptd Page 11 53 ^ 1972, description of the invention (8) 7 〇 controller 8 〇 clock signal 9 〇 test permission signal 92 multiplexer W switch group 9 5 error amplifier group 9 6 Comparator group 9 7 Switch group control signal 9 9 Total clock signal number Digital to analog conversion of the present invention 5 0 0 DAC output under test 5 0 1 Negative ramp voltage generation permission signal 11 0 0 Test self-switch 2 11 5 0 Test start switch 1 3 0 0 Forward and reverse return to zero signal 1 3 0 1 Delayed return to zero signal 1 3 0 2 Inversion and delay to return to zero signal 5 0 0 0 DAC input under test 0 Output 5 0 0 9 The output of the highest value of the DAC under test is 50 1 0 The embedded built-in self-test device of the previous output of the DAC under test is shown in the first figure. The embodiment of the digital self-test device of the present invention is based on (9 5), the comparator group (9 6), negative slope (92), control circuit (70), sum (2 1), reference voltage two (2 2), reference (24), clock signal (80), test under test DAC ( 10). Built-in built-in to analog converter 丨 Guan group (9 4), error amplifier group slope voltage generator (50), multiplexer main inputs: reference voltage one test voltage three (23), reference voltage four σ It can be composed of §§ (90) to test the DAC (10) under test. The start signal (16) controls multiplexing (92) to select the normal DAC input (100) or the control circuit (7). 〇) Production / test

531972 V. Description of the invention (9) Mouth pattern (60). During the test, the test pattern (6.) generated by the start-up control circuit ⑽ ":: = ⑼) Select ⑴50) to close, and the DAC output to be tested (5 0 0) That is to pass to the start switch to the error amplification cry, know the heart to the switch group (94), send a large text ... group (95) or comparator group (96) test parameters required. The voltage value is 1/2 the lowest effective LSB); the reference voltage two (22) voltage value is Leoch (recognize the minus minus-a least significant bit (= V (G) —: SBA is the? (23) The voltage value is the ideal DAC input as the most significant bit ;: wheel = J LSB), ... test the pen pressure four (24) is 3/2 the least significant bit? 5 5 comparator group (96) is controlled by The circuit (70) generates a positive-inverting return-to-zero signal two: "three comparators controlled by the comparator: comparator-⑷), comparison cry 1 ^), and a high-speed comparator (43). Related symbols are connected to control 2 ^ comparison state 1 output (4 1 0), comparator 2 output (4 2 0), and t, pro-comparator output (43G); high & comparator positive end input ⑷ 2) Connected to the switch ^ () 鬲 is also compared to the negative input (4 3 1) connected to the negative ramp voltage to produce a cry (50) 'Comparative benefit-negative input (4 11), comparator-positive input (12) The comparison is that a negative input (4 2 1) and two positive ends of the comparator (422) are connected to the error amplifier group (95). The positive input of the comparator (4 1 2) is connected to the positive input of the comparator (4 2 2).

D: \ nthu \ patent \ ats01 \ ats01.ptci 帛 page 531972 5. Description of the invention (10)

The 2-slope voltage generator (50) is controlled by a negative ® generation permission signal (501) generated by the control circuit (70). The positive-inverted burst signal (1 300), the delayed-return-to-zero signal (1301), and the inverted-re-return-to-zero ^ sign ( 1 3 0 2) The three error amplifiers controlled are composed of an error amplifier one (20), a delta difference amplifier of two (30), and an error amplifier three (40). The related symbols are an error amplifier output (2 0 0) connected to a negative input (4 1 1) of the comparator, an error amplifier input (2 0 1) connected to the ground of the error amplifier, and a reference voltage four ( 24) of the error amplifier one positive input (202); connected to the comparator one positive input (41 2) and the comparator two positive input (422) error amplifier two output (3 0 0), error amplifier two The negative terminal input (301) and the second positive terminal input (302) of the error amplifier are connected to the switch group (94); the third error amplifier output (40 0) connected to the second negative terminal input (421) of the comparator is connected to Three negative terminal inputs (4 0 1) of the error amplifier of the ground wire and three positive terminal inputs (402) of the error amplifier connected to the reference voltage one (2 1). The switch group (9 4) is composed of a self-test switch (11), an offset switch (1 2), a DAC switch (2 3), a DAC switch (1 4), and a gain switch (1 5). The test group consisting of self-test switch two (1100), low-test switch (1 8), high-test switch (19), and DAC switch (17), and a switch group generated by the control circuit (70) A control signal (97) controls its opening and closing. The connection method of the switch group (94) switches is detailed as follows:

Page 14 D: \ nthu \ patent \ ats01 \ ats01. Ptd 53.197¾ 5. Description of the invention (11) ~~ One test self-switch 1 (11) Connect the reference voltage one (2 丨) and the two negative input of the error amplifier ( 301). The offset switch (12) is connected to the reference voltage two (22) and the error amplifier two negative input (3 0 1). The second test DAC switch (13) is connected to the test start switch (115), so that the mc output (50 0) to be tested can be passed to the second negative input (301) of the error amplifier, and because the second negative input (301) of the error amplifier ) Can store the previous value, which can be compared with the voltage of the next test _ output (50 0). The input of the negative terminal of the error amplifier (3 0) is stored in the prior art, which will not be repeated here. The test D AC switch-(1 4) depends on the start switch ⑴ 5 Q), so that the DAC output (50 0) to be tested can be passed to the two positive input (302) of the error amplifier. The gain measuring switch (15) is connected to the reference voltage three (23) and the second positive input (3 0 2) of the error amplifier. The test self switch two (1100) is connected to the reference voltage four (24) and the error amplifier two positive input (30 2). The over-measurement low switch (18) is connected to the reference voltage two (22) and the high-speed comparison input (43 2).

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Connect to the reference voltage 531972 V. Description of the invention (12) The over-high switch (1 9) is connected to the input (43 2). Three (2 3) and high-speed comparator positive-end test DAC switch (1 7) connected (50 0) can be passed to the high-speed test start switch (11 50), so that the DAC under test inputs the comparator positive-end input (4 3 2 ). The control circuit (70) turns on the clock signal (80), the test permission signal (20), and? Fruit input: Comparator 1 output (41〇), Comparator 2 round

And n-speed comparator output (43 0). The output includes a switch group control signal 97), a positive and negative phase return to zero signal (13 0 0), a delayed return to zero signal (130), and an inverted and delayed return to zero signal (130 2). The error amplifier one (20), the error amplifier one (30), the error amplifier three (40), and the comparator one (41), the comparator (g6) of the error amplifier group (95) The internal structures of the second (42) and the high-speed comparator (43) are all known techniques, which will not be repeated here. The comparator group (96) is connected before and after the stage: it is as described above, so in the various test embodiments described below, only the switch group control signal (9 7) generated by the control circuit (70) is required to control the switch The input of the error amplifier group (95) of (94) is sufficient. '' Differential non-linear error test device See the second figure, the embodiment of the differential non-linear error test in the present invention is an embedded built-in self-test device of the digital-to-analog converter of the present invention.

531972

The connection is as follows: 1. The reference voltage one (21) is connected to the surgeon κ 0 4 ^ 哽 The raft block is an amplified three positive terminal input (4 0 2); 2 • The previous output of the DAC under test (5 〇1 〇) 糸 $ Benzene L, 9Π1, & νΰυίϋ) is definitely the second negative input of the amplifier (301); Now the output of the DAC under test (50 0 0) is the positive input of the error amplifier v 〇UZ y, the positive input (202) 4. The reference voltage is four (24) connected to the error amplifier. A differential nonlinear error test device is used to compare the two adjacent DAC input codes, that is, the output of the DAC under test (50 0 0) and the Test DA (: (5010), whether it is only (1/2) to (3/2) jl handles " J ，,, c T onx take the low effective bit voltage (0. to 1.5 LSB ). See the second example of the offset error test device @ 'The embodiment of the offset error test device in the present invention is a digital-to-analog converter of the present invention. The built-in built-in self-test device is connected as 1. 1. test voltage one (2 1) Connect the three positive inputs of the error amplifier (4 〇2); 2. The reference voltage two (22) is the two negative inputs of the error amplifier (3 0); 3. The output of the DAC input 0 to be tested (5 0 0 0 ) Is wrong Di-n-input terminal of the amplifier (302);

D: \ nthu \ patent \ ats01 \ ats01. Ptd Page 17 531972 V. Description of the invention (14) 4 'Reference voltage Four (24) Connected to error amplifier-Positive input (202) The offset test device is used for comparison The output of the DAC under test (500) and whether the difference is only (1/2) to 1.5 LSB). Modular I (22) (= output voltage when ideal input is 0 minus one least significant bit (= V (0) -LSB) voltage) to (3/2) least significant bit voltage (0 · The test device for increasing the error is as follows: 1 • Tea test voltage one (21) connection error amplification cry — + 2 DAr to be measured at the input-/ + positive input (40 2); • output of the load DAC input orientation value (5〇09) terminal input (3 0 1); in order to enlarge it as a shoulder 3 reference voltage three (23) for error amplification cry τ 4 夂 go to Φ-positive terminal input (3 0 2); 4 . Tea test electric four (24) connection error amplifier-positive input (202). The gain error test device is used to compare the output voltage when the reference electric DAC input is the highest bit plus-: (23 ^- Management '' CV (2-D + LSB) voltage) and the highest output value of the MC input under test

531972 V. Description of the invention (15) '(50 0 9), is it only a difference of (1/2) to (3/2) least significant bit voltages (0.5 to 1.5 LSB). Self-testing device. As shown in the fifth figure, an embodiment of the self-test device in the present invention converts the digital-to-analog analogue of the present invention into a post-entry built-in self-test device. The connection is as follows: 1. Reference voltage (21) is connected to the three positive terminals of the error amplifier ( 402) and the two negative input (301) of the error amplifier; 2. The reference voltage four (24) is connected to the two positive input of the error amplifier (302) and the positive input of the error amplifier (2 0 2). The self-test device is used to Test whether the comparator one (4 1), the comparator two (4 2), and related connections in the error amplifier group (9 5) and the comparator group (9 6) are correct. The integrated non-linear error test device is shown in Figure 6. The integrated non-linear error test example in the present invention connects the embedded built-in self-test device of the digital-to-analog converter of the present invention as follows: 4 3 2) Controllable by the control circuit (70)

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Reference voltage two (22) "Reference power generation three (23) & dac output under test (50)." The integrated nonlinear error test device is used to compare whether the ideal DAC output value is equal to + M / 9η Ώ ^ j The value is no, and it is ± (1/2) the least significant bit voltage (+ 0 · 5 JLSB). This error is used in the test of the embedded built-in self-test device of the digital-to-analog converter. Both the amplifier and the comparator need three steps in sequence: the amplification step is the offset error canceling step, the clock reflow (c 丨 oc Fed-t hi ough) canceling step, and the test step. These three steps are learning techniques, which will not be repeated here. The differential non-linear error test method is shown in the second figure. The differential non-linear error test method of the present invention is a built-in self-test device of the digital-to-analog converter of the present invention. The method is as follows: Step 1.1 First send the code to be tested]) A c input code output (50 〇 〇) to the error amplification to the two negative input (3 0 1) to save the previous value, so as to be compared with the next test D a C output (5 0 0) voltage comparison;

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Step 1 · 2 of the lowest error amplifier then output the next round-in code (increasing the effective bit) of the DAC under test, that is, the D AC output (50 0) under test is now sent to the two positive inputs (302) At step 1.3, observe whether the output of comparator one (410) is high and the output of comparator two (420) is low. If yes, then two adjacent dac input two codes pass the differential non-linear error test; if not, Then it fails; otherwise, step 1 · 4 repeats steps i 丄 to 1 · 3 for each adjacent two DAC input codes, and the differential nonlinear error test is completed. Offset error test method The number of the present invention is as shown in the third figure above. In the present invention, the offset error test method is based on a built-in self-test device of a bit-to-analog converter connected to a shift error test device. The test method is as follows: Step 2.1 Take the output of the DAC under test (5 0 0 0) as the error amplifying two positive terminal input (302); Observe whether the output of the comparator 1 (410) is high at step 2.2 and the output of the comparator 2 (4 2 0) Whether it is low potential, if yes, pass the offset error, then try; if not, fail.

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531972 V. Description of the invention (18) The gain error test method is shown in the fourth figure. The gain error test method in the present invention is an embedded built-in self-test device of the digital-to-analog converter of the present invention, and is connected to the aforementioned gain error test device. The test method is as follows: Step 3. 1 The output of the DAC input under test (50 0 9) is the input of the two negative terminals of the error amplifier (301); Step 3. 2. Observe the output of the comparator (4 1 0) Whether it is a high potential and whether the output of the second comparator (4 2 0) is a low potential. If it is, the gain error test is passed; if not, the pass is not passed. The self-test method is shown in the fifth figure. The self-test method in the present invention is a built-in self-test device that connects the digital-to-analog converter of the present invention as the aforementioned self-test device. The test method is as follows: Step 4.1 Reference Voltage One (2 1) Connect the two negative input (301) of the error amplifier and the reference voltage four (24) connect the two positive input (3 0 2) of the error amplifier;

D: \ nthu \ patent \ ats01 \ ats01.ptd Page 22, 53,1972 V. Description of the invention (19) Step 4.2 Observe whether the output of the comparator (410) is the high lightning return potential and I; check the output of the second processor ( 420) Whether it is low potential, if yes, pass self, and no, fail. I test; if the integrated nonlinear error test method is shown in Figure 6, the integrated nonlinear error test method in the present invention, 〃 — the embedded built-in self-test of the digital-to-analog converter of the present invention will be as described above Integrated non-linear error test device, the test method is as follows: 1. Connect the positive terminal input (432) of the high-speed comparator to three (23) 'that is the output of the highest value of the ideal DAC input to be tested; Bit (= V (2N-1) + LSB) voltage, and make it connected to high-speed comparison 1 = Order and the negative ramp voltage generator (50) of the input (431) reduces the voltage from the maximum value with a fixed negative slope to When it is equal to three reference voltages (23), the number of W signals (8 0) is counted. #, 义

Step 5 · 2 Connect the positive terminal input (4 3 2) of the high-speed comparator to the reference voltage two (2 2) 'that is the output voltage when the ideal DAC input is 0 minus one least significant bit (= V (0)- LSB) voltage, wait until the fixed negative slope generated by the negative ramp voltage generator (50) drops to equal to the reference voltage two (2 2), stop counting the number of clock signals (80), and also stop the negative ramp voltage generator ( 5 〇) output; Step 5 · 3 Calculate the number of clock signals (8 0) in step 5 · 1, 5 and 2,

D: \ nthu \ patent \ atsO1 \ ats01. Ptd Page 23 531972 V. Description of the invention (20) Number of total clock signals (9 9) Number of all round-in codes plus one word: The number (99) divided by the time (a minimum interval of AH to arrive at the ideal interval of the input code to calculate the number of clock signals each at // 4), but also the W round code is relatively ideal. The interval is relatively ideal. The number of clock signals is ± 0.5. The lowest digit (= Λ number of input code numbers); 'Valid digits for the 70-day clock signal: ^: 5 丄 Repeat the high-speed comparator. The positive input (432) is connected to the parameter: υ ', that is, the output of the highest value of the DAC under test, plus, ^, we take the low effective bit (= V (2n — 1) + LSB) voltage, Comparator negative terminal input (43 " negative ramp voltage producer) ^ 妾 = the maximum value is reduced by a fixed negative rate $ # 姿 土 () and the voltage is connected from the _ input (432) to the output of the DAC under test (500), and counting; counting the number of pulses to 5 (80), at this time, the control circuit (7 tries to sample (60) is the highest input code of the DAC; the test step 5. 5 when the negative ramp voltage is generated Voltage generated by the device (5 〇) When it drops to the output (500) of the DAC under test, the control circuit (70) controls the test pattern (^) to decrement the least significant bit of the input code, and enters the DAc (1 〇) under test, and records the same Clock signal (80) count; Step 5 · 6 Repeat steps 5 · 5 until the total number of clock signals (9 9) has passed, and compare whether the clock signal (80) count recorded by each input code is In the relatively ideal interval time range; if it is, the non-linear error D: \ nthu \ patent \ ats01 \ ats01. Ptd page 24 531972

Claims (1)

531972 /, application scope of patents " " one 1 -------- '可 二 ί = Voltage generator is controlled by the negative slope voltage generated by the control circuit; 5 Tiger control; 2 difference amplifier group is controlled by The positive and negative phase return signals generated by the circuit, delay:…, No., and, and the three phases of error amplification controlled by the reverse phase and delayed return to zero signal control are composed of the first difference amplifier, the second error amplifier, and the third error amplifier; The relevant connections include an error amplifier output connected to the negative input of the comparator, an error amplifier input connected to the ground, a positive input of the error amplifier connected to the reference voltage four, and a positive input of the comparator. And the second positive input of the comparator, the second output of the error amplifier, the second negative input of the error amplifier, the second positive input of the error amplifier; the third output of the error amplifier connected to the second input of the comparator, and the third negative terminal of the error amplifier connected to the ground The input and the three positive terminals of the error amplifier connected to the reference voltage 1. The switch group consists of the self-test switch 1, the offset switch, the dac switch 1, the DAC switch 1, and the gain. Off, test self-switch 2. It consists of just low switch, high test switch, and DAC switch, and it is controlled by the switch group control signal generated by the control circuit. T test self-switch-reference voltage-and error Amplifier two gΑ 端 terminal turn in; offset switch is connected to reference voltage two and error amplifier two negative terminal. The DAC switch two is connected to the test start switch, so that the output of the DAC under test can pass through the input of the two negative terminals of the error amplifier. Error amplifier two negative round people: 口 J 存 531972 The scope of the patent application & value can be compared with the output voltage of the DAC under test next time; the DAC switch under test is also connected to the 1 test start switch, so that the output of the DAC under test can be passed to the second input of the error amplifier; Voltage three and error amplifier two are upright, and input; test self-switch two is connected with reference voltage four and error amplifier two is upright and input; low-test switch is connected with reference voltage two and high-speed comparator positive input 'test too high switch Connect the reference voltage three and the positive input of the high-speed comparator; 'The DAC switch is connected to the test start switch so that the output of the DAC under test can be passed to the positive input of the high-speed comparator; & the circuit input clock signal, test permission signal, And test result 2 comparator 1 output, comparator 2 output, and high-speed comparator output · There are switch group control signals, positive and negative return to zero signals, delayed return to zero transmission, just, and reversed and then delayed return Zero signal, etc .; σ should be 2 :::? Build a self-testing digital-to-analog converter device master. ^ ^ To provide a negative ramp voltage or other known expected voltage: to be tested; the output of the bit-to-analog converter is better than the design, designing the digital-to-analog converter: =? :(, , Offset error, maintenance error, differential non-linear error, product: Shan Zhi; the main feature is to use the switch to switch the built-in built-in self-test number of bamboo wire, ^,,. ,, ^ digits to the ratio The converter device is connected to use the switching of the gate, and is replaced by the required test to determine the 1 shift error, Xiao Yi error, and differential material to test the required four parameters, respectively; the built-in built-in non-self-spring of the present invention The other feature of our device is that it uses the white-knowledge technology of the conventional V-to-analog converter to treat the output voltage of the DAC under test as D: \ nthu \ patent \ ats01 \ ats01. Ptd 531972 Negative input for comparison with the output voltage of the error amplifier DAC before comparison with the patent application range to be tested next. • The embedded built-in self-test device of the digital-to-analog converter as described in item 1 of the scope of the patent application, wherein the switch group is controlled to be connected to a differential non-linear error test device by the control signal of the switch group generated by the control circuit. f voltage one is connected to the three positive inputs of the error amplifier; the previous output of the DAC under test is the two negative inputs of the decision amplifier; now the test output "^ is the two positive inputs of the error amplifier; four reference voltages are connected to the positive input of the error amplifier叩 3 · The embedded built-in self-test device of the digital-to-analog converter as described in item 1 of the scope of patent application, wherein the switch group is controlled by the switch group control signal generated by the control circuit to be connected as an offset error test device: That is, the reference voltage = connected to the three positive terminals of the error amplifier; the reference voltage two is the error amplifier 2-the negative terminal input; the output of the DAC input under test 0 is the error amplifier cry-positive input; the reference voltage four is connected to the error amplifier-positive terminal Enter. — Just lose 4 · As stated in Item 1 of the patent scope, the digital-to-analog converter is built-in self-testing δ-type k-position, where the switch group is controlled by the control circuit and the switch group control ## control is connected to increase the disease. Differential test device: the reference voltage is connected to the three positive inputs of the error amplifier; the highest / value wheel output of the DAC to be tested is the second negative terminal of the error amplifier; the reference voltage three is the second of the error gate large value amplifier. Positive and negative output input; four reference voltages are connected to one positive input of the error amplifier. 531972 VI. Range of patent application Step 5 · 1 Connect the positive terminal input of the high-speed comparator to the reference voltage III, that is, the output of the highest value of the ideal DAC input plus the lowest effective bit voltage 'sub-connector for high-speed comparison When the negative ramp voltage generator of the negative input of the comparator drops the voltage from the maximum value with a fixed negative slope to equal to the reference voltage of three, it starts to count the number of clock signals; Step 5 · 2 Connect the positive terminal input of the high-speed comparator to the reference voltage Second, that is, the output voltage when the ideal DAC input is 0 minus a least significant bit voltage. Second, until the fixed negative slope generated by the negative ramp voltage generator drops to equal to the reference voltage t 一 止 τ, the number of clock signals is calculated. The output of the negative ramp voltage generator is also stopped; step f · 3 calculates the number of clock signals passed in steps 5 · 1, 5.2 to obtain the total number of clock signals, and divides the total number of clock signals by ( The number of all input codes is added), and the ideal interval time (a least significant bit) of a round-in code is-the number of daily guards ^, and the relative interval of each input code is calculated. "&Quot; 巳 目 (= relatively ideal number of clock signals for each input code ± 0 · 5 least significant bit time clock signals); Factory steps wide 4 # Repeatedly connect the positive input of the high-speed comparator to Reference voltage 2 yuan: Γ The output of the highest value of the input under test plus-a maximum = makes the negative ramp connected to the negative terminal input of the high-speed comparator. Generate and change the voltage from the maximum value to the fixed voltage for three hours. Positive end input connection = down to equal to the reference and start counting the number of clock signals, at this time 4; at the output of the DAC under test, the sample is the highest input code of the DAC; the test chart generated by the children step 5. 5 When the negative ramp voltage The generator scare voltage drops to equal to wait 531972 6. When applying for patent range to measure the DAC output, the control circuit controls the test pattern to decrement the input code of one least significant bit, enter it into the DAC under test, and record the clock signal counts when equal; Step 5. 6 Repeat Step 5 5 until the total number of clock signals has passed, and compare whether the clock signal count recorded by each input code is within a relatively ideal interval time range; if yes, pass the integrated nonlinear error test; if not, fail; The main technical content of the embedded built-in self-test digital-to-analog converter device testing method of the present invention is to provide a test method that compares the negative slope voltage or other known expected voltage with the output of the digital-to-analog converter to be tested; It is characterized in that when measuring the non-linear error of the product, it starts from the highest bit to the lowest bit, generates a desired value with a negative ramp voltage, and compares it with the output value of the digital-to-analog converter to be measured to obtain the digital-to-analog converter parameter value. . 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