TW531870B - Method for mounting a chip for improving bonding and positioning - Google Patents

Method for mounting a chip for improving bonding and positioning Download PDF

Info

Publication number
TW531870B
TW531870B TW091109186A TW91109186A TW531870B TW 531870 B TW531870 B TW 531870B TW 091109186 A TW091109186 A TW 091109186A TW 91109186 A TW91109186 A TW 91109186A TW 531870 B TW531870 B TW 531870B
Authority
TW
Taiwan
Prior art keywords
chip
mounting
positioning
improving bonding
prepreg
Prior art date
Application number
TW091109186A
Other languages
Chinese (zh)
Inventor
Geng-Shin Shen
Jesse Huang
Original Assignee
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to TW091109186A priority Critical patent/TW531870B/en
Application granted granted Critical
Publication of TW531870B publication Critical patent/TW531870B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)

Abstract

A method for mounting a chip for improving bonding and positioning is disclosed. By means of a prepreg formed on active surface of chip, the prepreg combines the chip and the substrate during chip mounting to provide a good support and bump positioning. After thermal compression, non-reflow bumps electrically connect the chip and the substrate accurately.

Description

531870 ’ 發明專利證書號第177516號（申請號091109186) 申請專利範圍替換本（無割線版本，98年4月） 造，其中該些焊墊之間隔係小於40 第14頁 $531870 ’Invention Patent Certificate No. 177516 (Application No. 091109186) Application for a replacement patent scope (non-secant version, April 1998), in which the interval between these pads is less than 40 Page 14 $

TW091109186A 2002-04-26 2002-04-26 Method for mounting a chip for improving bonding and positioning TW531870B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW091109186A TW531870B (en) 2002-04-26 2002-04-26 Method for mounting a chip for improving bonding and positioning

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW091109186A TW531870B (en) 2002-04-26 2002-04-26 Method for mounting a chip for improving bonding and positioning

Publications (1)

Publication Number Publication Date
TW531870B true TW531870B (en) 2003-05-11

Family

ID=28788654

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091109186A TW531870B (en) 2002-04-26 2002-04-26 Method for mounting a chip for improving bonding and positioning

Country Status (1)

Country Link
TW (1) TW531870B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8187965B2 (en) 2003-07-23 2012-05-29 Megica Corporation Wirebond pad for semiconductor chip or wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8187965B2 (en) 2003-07-23 2012-05-29 Megica Corporation Wirebond pad for semiconductor chip or wafer

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees