TW531844B - Method to prevent the ion byproduct leakage in spacer - Google Patents

Abstract

The present invention is a method to prevent the ion byproduct leakage in spacer, especially relating to a spacer formed by an offset liner, a liner after surface treatment and rapid thermal chemical vapor deposition or atomic layer deposition to prevent the ion byproduct in spacer from leaking into the other regions. The present invention is a spacer with good quality, which is formed by an offset liner, a liner after surface treatment and rapid thermal chemical vapor deposition or atomic layer deposition, so as to prevent the ion byproduct in spacer from moving into the other regions through diffusion or drifting in the high-temperature environment and affecting the voltage stability of semiconductor devices after turning on power and further affecting the quality of semiconductor devices.

Description

531844 V. Description of the invention (1) 5-1 Field of the invention: The present invention is a method for preventing leakage of by-product ions in the partition wall, and particularly relates to a method of using a compensation cushion layer, a surface treatment layer and A method of rapidly heating a barrier wall formed by a chemical vapor deposition method or an atomic layer deposition method to prevent by-product ions in the barrier wall from leaking to other regions. By using the method of the present invention, the by-product ions in the gap wall can be fixed in the region of the gap wall, the voltage stability of the semiconductor element after being energized can be improved, and the quality of the semiconductor element can be improved. 5-2 Background of the Invention: Generally, when manufacturing a spacer of a polycrystalline silicon gate, most of the spacer material used is an insulating material to reduce the current leakage defect of the polycrystalline silicon gate. A pad layer is usually formed on the outside of the polysilicon gate (Polygate) to increase the degree of bonding between the spacer and the polysilicon gate, and to prevent defects such as leakage current and stress from affecting the quality of the semiconductor device. . Most of the insulating materials used in traditional spacers are oxides, but with the shrinking of the process line width, silicon nitride is currently used as the material of the <1 spacer. However, the degree of combination of silicon nitride and polycrystalline silicon is not high. Therefore, if a cushion layer is not formed outside the polycrystalline silicon gate, the polycrystalline silicon gate and the spacer will easily cause gaps, which will affect the quality of the semiconductor device.

531844 V. Description of the invention (2) The function of the cushion layer The defect of the force between the electrode and the gap wall, so a good degree of bonding, the polycrystalline silicon and the polycrystalline silicon gate used in the cushion layer are thermally oxidized. First enter the gas in the reaction chamber of the furnace tube to make the surface of the oxygen ion infiltration react. Use the process of etching the furnace tube to remove the chemical vapor deposition during the formation of gap heating chemical vapor deposition. pascal), and the thermal chemical vapor deposition ° C, the pressure is about 2 to 4 minutes, which is the interface between the gate and the gap to increase the quality of the gate bonding, so that the gate does not generate leakage current or should The material of the cushion layer and the material of the gate and the spacer must be good enough to exert its proper performance.. Most of the materials used are stone dioxide, because it has a good degree of combination with the silicon nitride of the spacer. The traditional methods of forming a silicon dioxide layer as a cushion layer are to first send a wafer that has formed a polycrystalline silicon gate on a substrate. When the temperature of the reaction chamber reaches about 700 ° C, oxygen is passed through and the polycrystalline silicon is passed. On the surface of the gate electrode, a silicon dioxide film is formed as a cushion layer on the polycrystalline silicon gate electrode. Next, a nitride layer is formed on the outer side of the silicon layer, and a gap wall can be obtained after a part of the silicon nitride layer. ， 的 制 System In general, the furnace process or rapid product method is usually used to convert silane (si 1 ane; S i Η 4) or digas silane. Lane; S i H 2C 1 2) and ammonia (ammonia; NH3) to (si 1 ic η nitride) as the partition wall. In the furnace tube is about 680 to 780 ° C, and the pressure is about 20 to 60Pa. The process time required is about 2 to 6 hours. In the rapid addition process, the temperature used is approximately 6500 to 7200 2 0 to 6 0 torr, and the required process time is. In the process of reaction, something like 531844 is often produced. 5. Description of the invention (3)

Hydrogen (hydrogen;; 2) and hydrogen chloride (hydrochloric; HC1) and other by-products (b y-p r 〇 d u c t). In a high-temperature environment, these by-product particles will become ions with great kinetic energy and move to other areas through diffusion or migration. When these ions move to the area below the gate, it is easy to react with the impurity particles below the gate and remain under the gate. When the semiconductor element is energized, a short channel effect is easily generated under the gate, which affects the voltage stability of the semiconductor element, and then affects the performance and quality of the semiconductor element. Among the by-products, the effects of hydrogen ions are most severe. Therefore, the method of the present invention must be used to minimize the chance of generating by-product ions during the formation of the gap wall, and reduce the temperature of the process of the gap wall, so that the ions of the by-product ions remain in the gap wall and will not move Other regions affect the stability of the semiconductor device voltage. Although the temperature required for the process has been reduced in the process of the spacer, in the subsequent process of the semiconductor device, a high temperature environment will still be required to meet the requirements of the process. Traditionally, the silicon dioxide cushion layer formed by the thermal oxidation method can successfully combine the polycrystalline silicon gate and the spacer, so that the polycrystalline silicon gate does not cause defects such as leakage current and stress. However, it cannot block the ions of the by-product ions in the gap wall, and moves to the bottom of the gate through the pad through diffusion and drift modes in a high temperature environment, which affects the stability of the voltage of the semiconductor device. 5-3 Purpose and summary of the invention: 531844 V. Description of the invention (4) In view of the above background of the invention, the traditional method cannot reduce the number of by-product ions in the partition wall, and cannot prevent by-product ions in the partition wall Ions move to other areas and affect the voltage stability of the semiconductor element after it is energized. The main purpose of the present invention is to use a compensation pad, a surface treated pad, and rapid heating chemical vapor deposition or atomic layer deposition. The barrier wall formed by the method to prevent by-product ions in the barrier wall from leaking to other areas. The second object of the present invention is to reduce the thermal budget of the spacer process by using a spacer formed by a compensation spacer, a spacer after surface treatment, and rapid heating chemical vapor deposition or atomic layer deposition. (Thermal budget) 〇 A third object of the present invention is to improve the semiconductor by using a compensation cushion layer, a cushion layer after surface treatment, and a spacer formed by a rapid heating chemical vapor deposition method or an atomic layer deposition method. The voltage stability of the component after being energized. A fourth object of the present invention is to improve the quality of a semiconductor device by using a spacer formed by a surface treatment and a spacer formed by a rapid heating chemical vapor deposition method or an atomic layer deposition method. Across the surface, another object of the present invention is to utilize a compensation cushion

Page 7 531844 V. Description of the invention (5) After treatment, the barrier layer formed by the rapid heating chemical vapor deposition method or atomic layer deposition method can reduce the cost of production and operation. According to the above-mentioned object, the present invention provides a method for preventing ions in the partition wall from leaking, using a compensation cushion layer, a compensation cushion layer with a higher surface hardness, a second cushion layer, and a rapid heating chemical gas. The spacer formed by the phase deposition method or the atomic layer deposition method can reduce the thermal budget of the spacer process and prevent the ions in the spacer from leaking to other regions. The invention can also improve the stability of the voltage of the semiconductor device after being energized and can improve the quality of the semiconductor device. The invention can further improve the product yield (y i e 1 d), so as to reduce the cost of production operation and improve the operation efficiency of the manufacturing process.

Page 8 531844 V. Description of the invention (6) Referring to the first figure, a gate oxide layer (gate ο X ide 1 ayer) 2 2 is formed on the substrate 10 of the wafer, and a stone layer 2 is formed. 4 On the gate oxide layer 22, the silicon layer 10 may be a polycrystalline silicon layer. Referring to the second figure, after the gate position is defined, a mask layer 30 is formed on the silicon layer 24 at the gate position. The excess gate oxide layer 22 and the silicon layer 24 are removed through an etching process, and the photomask layer 30 is removed by cleaning with a chemical solvent to form a gate electrode 20 on the substrate 10. Referring to the third figure, this is a schematic diagram of the gate 20. The gate 20 includes at least a silicon layer 24 and a gate oxide layer 22. The gate oxide layer is a pad oxide layer formed by a 2 2 -thermal oxidation method, and is formed on the substrate 10. The polycrystalline silicon layer 24 is formed on the gate oxide layer 2 2. Referring to the fourth figure, a pad layer 4 0 is formed on the gate electrode 20 and the substrate 10. There are many methods for forming the cushion layer. In this embodiment, several methods are proposed to form the cushion layer to meet the requirements of the manufacturing process. The first method is to use a rapid heating chemical vapor deposition method to form a silicon oxynitride layer on the gate 20 and the substrate 10 as a cushion layer. The temperature used in this method is approximately 600 to 750 ° C, the pressure used is approximately 200 to 760, and the time required for the process is approximately 1 to 4 minutes. First, the wafer to be processed is sent into the reaction chamber. When the temperature in the reaction chamber reaches the set temperature, Shi Xiyao, water gas and ammonia gas are passed in to form a nitric oxide on the substrate and the gate.

531844 V. Description of the invention (7) A silicon (si 1 icon oxynitride) layer is used as a cushion layer. The silicon oxynitride layer formed by the rapid heating chemical vapor deposition method is a material that is biased toward oxides, which prevents the nitrides from contacting the silicides and causing excessive stress, which affects the quality of the semiconductor device. The surface hardness of this nitride stone layer is relatively thick, so that by-product ion ions in the barrier wall generated in subsequent processes can be blocked out of the cushion layer, which cannot be diffused or drifted through the cushion layer. Move to the bottom of the gate and affect the voltage stability of the semiconductor device. The second method is to first form a first cushion layer on the gate electrode and the substrate. The material of the first cushion layer is an oxide, usually tetraethylorthosilicate (TE0S) or south temperature oxide. (High thermal oxide; HT0) as the material of the first cushion layer. Referring to the fifth figure ', the first cushion layer is partially removed after a step of etch back. The first cushion layer remaining on the gate electrode 20 and the substrate 10 becomes an offset liner 45. The function of the compensation pad 45 is to prevent the saturation current of the gate 20 from falling too fast. Therefore, the compensation pad 45 is used to reduce the speed of the saturation current of the gate 20 to decrease. After the compensation pad layer 45 is formed on the gate electrode 20 and the substrate 10, a plasma process is performed on the surface of the compensation pad layer 45, such as remote plasma nitridation; RPN) or decouple plasma nitridation (DPN) to improve the surface hardness of the compensation pad 45 and complete the process of the compensation pad 45.

531844 V. Description of the invention (8) The principle of the so-called absorption plasma nitridation method and remote plasma nitridation method is to first send the item to be processed into an electric field environment, and then introduce nitrogen (nitrogen; N 2) Or a mixture of nitrogen and helium (he 1 i um; He). The electric field is used to change the gas into an ion state, and the acceleration of the electric field causes the ions to rapidly impact the surface of the article. The surface hardness of the surface of the article after the impact of ions becomes higher than the surface hardness of the article without the plasma nitriding treatment or the remote plasma nitriding treatment. When the remote plasma nitridation method is implemented, the process temperature is about 500 to 7500 ° C, the pressure used is about 1 to 3 Taoer, and the time required for the process is about 30 L · to 120 seconds. When the absorption plasma nitriding method is implemented, the process temperature is about 50 to 200 ° C, the pressure used is about 0.5 to 20 Tao, and the time required for the process is about 30. To 120 seconds. Depending on the process requirements, different methods of nitriding plasma treatment are used. After the process of absorbing plasma nitriding or remote plasma nitriding, stress concentration usually occurs on the surface of the compensation pad 45, so a reoxidation treatment can be performed at this time. In order to eliminate the phenomenon of stress concentration occurring in the compensation pad 45, and to avoid the phenomenon of stress concentration affecting the quality of the semiconductor element. However, with the needs of the process, this re-oxidation process can be arranged to be processed in subsequent processes, and it is not limited to re-oxidation immediately after the process of absorption plasma nitridation or remote plasma nitridation. Process.

Page 11 531844 V. Description of the invention (9) After the compensation pad layer 45 is formed, a lightly doped drain (LDD) process is next performed. The purpose of this process is to reduce defects caused by hot carrier effects. Usually, the lightly doped drain process is followed by a re-oxidation process to repair the damaged surface during the lightly doped drain process. However, with the needs of the process, the oxidation process does not need to be limited to light. Processing is done immediately after the doped drain process. Referring to the sixth figure, after the lightly doped drain electrode process, a second pad layer 50 is formed on the compensation pad layer 45, and the function of the second pad layer 50 is that of a general pad layer. Must have a function to serve as the interface between the gate 20 and the gap wall to increase the bonding quality between the gate 20 and the gap wall formed in subsequent processes, so that the gate 20 will not generate leakage current or stress Defects. As the material of the second cushion layer 50, tetraoxyethyl silicon or a high-temperature oxide is usually used. After the second cushion layer 50 is formed, the surface of the second cushion layer 50 needs to be further subjected to plasma nitridation or absorption plasma nitridation to increase the surface hardness of the second cushion layer 50, and Complete the second pad 50 process. The surface of the second pad layer 50, which has undergone long-range plasma nitriding or absorption plasma nitriding, has a higher hardness. In the subsequent manufacturing process of the gap wall, regardless of the number of by-product ions in the gap wall, the gate and the region at the bottom of the gate will be protected by the second cushion layer with higher hardness, so that the By-product ions move to the bottom of the gate through the second pad through a diffusion or drift movement mode, thereby affecting the voltage stability of the semiconductor device

Page 12 531844 V. Description of the invention (ίο) The invention can also improve the properties of the gap wall, reduce the production of by-product ions in the gap wall, and reduce the process temperature of the gap wall process to reduce the The opportunity for product ions to move to the gate or to the area below the gate. The method used in this embodiment is an atomic layer deposition method (a t om i c '1 a y e r d e p o s i t i ο η; A L D). In the traditional deposition process, the reaction gas is passed into the reaction chamber together to start the deposition at a desired position. However, many by-product ions are generated during the gas deposition process. This by-product ion is easy It is coated in the deposited layer and cannot escape. In particular, when using a rapid heating deposition process, the process time is relatively short, so the number of by-product ions in the barrier wall will increase greatly, resulting in the high-temperature environment, these by-product ions will easily diffuse through Or it can be moved to other regions in a drift manner, which affects the quality of the semiconductor device. The method used in this embodiment is an atomic layer deposition method. The principle of the so-called atomic layer deposition method is to first pass the first gas into the reaction chamber, and after it reacts with the material at the desired deposition position, use an inert gas to remove the reaction byproduct ions generated by the reaction. Pump extracts this byproduct ion from the reaction chamber. Next, a second gas is passed into the reaction chamber to cause it to react with the first gas ion at the location of the plutonium to generate the desired product. An inert gas is used to remove the reaction by-product ions generated by the reaction, and the by-product ions are extracted from the reaction chamber by a group of w pumps.

Page 13 531844 V. Description of the invention (11) Referring to the seventh figure, after the production of the second cushion layer 50 is completed, the production of the spacer layer 60 is then performed. Because the adopted method is atomic layer deposition, after the process of the spacer layer 60 is completed, the number of by-product ions in the spacer layer 60 will be far less than that produced by the traditional rapid heating chemical vapor deposition method. The resulting gap. The process temperature of the atomic layer deposition method is about 300 to 650 ° C, which is lower than the process temperature of the rapid heating chemical vapor deposition process. Therefore, the byproduct ions in the gap wall layer 60 can be avoided in a high temperature environment. Under the effect of diffusion or drift. Referring to the eighth figure, after the spacer wall layer 60 is formed, a part of the spacer wall layer 60 is removed through an etch-back step to form a spacer wall shape on the second cushion layer 50. Then, the compensation pad 45 and the second pad 50 are partially removed in a lithography and etching process so that the top of the gate 20 is exposed to the gate 20. When the process line width is gradually shrinking, the material of the spacer is usually made of nitride such as silicon nitride. Next, you can define the positions of lightly doped anode 7 5 and source / deposited 80 and implant the required ions to complete a low-temperature and high-quality metal-oxygen semi-transistor (meta 1 oxide semiconductor transistor). When the barrier wall is made by the atomic layer deposition method, because the content of by-product ions in the barrier wall is small and the thermal budget of the barrier wall process is low, it is not necessary to use the cushion layer of the present invention to prevent by-products in the barrier wall. Ions move through the interlayer to the gate or the area below the gate. However, the speed of the atomic layer deposition method is relatively slow, which does not meet the requirements of the process. Therefore this

Page 14 531844 V. Description of the invention (12) The invention can also adopt a composite spacer wall, a compensation cushion layer and a second cushion layer to improve the efficiency of the process operation. When the atomic layer deposition method is used to form a second spacer layer on the gate and the substrate, and then a second spacer wall layer is formed on the rapid spacer layer, usually the same material is used to remove the part. The second gap wall layer can complete the process of the gap wall. In the same way, there are fewer 50 product ions on the second cushion layer, and the by-product ions move in different layers and the second cushion layer according to the process requirements. It is also possible to compensate for the formation of a thick heating chemical vapor layer and the first gap between the cushion layer and the first layer. Finally go through one to form a gap as shown in the ninth figure. The first gap wall layer formed has a certain ability to block to the gate 20 and the gate 20, and the ordinary resistance can be used to obtain a higher resistance stability, a two-layer layer, and a thinner deposition method. It is necessary to use the original 65. After the semiconducting layer of the second interlayer is taken from the semiconducting layer, make the first one to be in the shape of the lithography step in the first and second gaps. 0 field, so it replaces the pad body element. According to the embodiments described above, the present invention provides a method for preventing ion leakage in the partition wall, which utilizes a compensation plutonium layer, a surface treated cushion layer, and a rapid heating chemical vapor deposition method or an atomic layer. The spacer formed by the deposition method reduces the thermal budget of the spacer process and prevents the ions in the spacer from leaking to other areas. The invention can also improve the stability of the voltage of the semiconductor element after being energized and can improve the quality of the semiconductor element. The invention can further improve the yield of the product, reduce the cost of production and operation, and improve the operating efficiency of the manufacturing process. It not only has practical effects, but also has never been done before.

Page 15 531844 V. Description of the invention (13) The design of the invention has the enhancement of efficacy and progress, so it has met the requirements of the new model of the patent law and applied for it in accordance with the law. To this end, the examiners are honoured to examine it in detail, and pray for the granting of patents at an early date. The above description is only a preferred embodiment of the present invention. This embodiment is only used for illustration, not for limiting the scope of patent application of the present invention. It can still be implemented without departing from the essence of the present invention. Such changes should still fall within the scope of the present invention. Therefore, the scope of the present invention is defined by the following patent application scope. 531844 The diagram is briefly explained. The first diagram is a schematic diagram of forming a gate oxide layer and a silicon layer on a substrate. The second diagram is a schematic diagram of a mask layer formed on the silicon layer after the first gate position. The figure is a schematic diagram of forming a gate electrode on a substrate; the fourth picture is a schematic diagram of forming a pad layer on the gate electrode and a part of the substrate; the fifth picture is a schematic diagram of forming a compensation pad layer on the gate electrode; the sixth picture is on the A schematic diagram of forming a second cushion layer on the compensation cushion layer; a seventh diagram is a schematic diagram of forming a spacer wall layer on the second cushion layer; a eighth diagram is a schematic diagram of forming a spacer wall on the second cushion layer; and a ninth diagram In order to form a composite partition wall on the second cushion layer, the representative symbols of the main parts of the schematic diagram are: 10 substrate 2 gate

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Claims (1)

531844 6. Scope of patent application 1. A method for preventing leakage of a by-product ion in a gap wall, the method at least comprises: forming a gate electrode on a substrate 'the gate electrode includes at least a gate oxide layer; Forming a compensation cushion layer on the gate electrode and applying a first plasma treatment to the compensation cushion layer; forming a cushion layer on the compensation cushion layer and the substrate and applying a second electric paddle to the cushion layer Processing; forming a first gap wall layer on the cushion layer, the first gap wall layer is formed by an atomic layer deposition method; forming a second gap wall layer on the first gap wall layer, the second gap The wall layer is formed by a rapid heating chemical vapor deposition method; and a portion of the first gap wall layer, a portion of the second gap wall layer, a portion of the cushion layer and a portion of the compensation cushion layer are formed to form the The gap wall is on top of one of the exposed gates. 2. The method according to item 1 of the patent application range, wherein the compensation pad is a south temperature oxide. 3. For the method according to item 1 of the patent application scope, wherein the compensation pad is a tetraoxoethoxylate. 4. The method according to item 1 of the patent application, wherein the first plasma process is a remote plasma nitriding process. Page 19 531844 6. Scope of patent application 5. For the method of the first scope of patent application, the above-mentioned second plasma process is an absorption plasma nitriding process. 6. The method according to item 1 of the patent application, wherein the first spacer layer is a silicon nitride. 7. The method according to item 1 of the patent application, wherein the second spacer layer is a silicon nitride. «8. A method for preventing leakage of a by-product ion in a gap wall, the method includes at least: forming a gate electrode on a substrate 'the gate electrode includes at least a gate oxide layer; forming a compensation pad layer A first plasma treatment is applied to the gate electrode and the compensation cushion layer is formed; a cushion layer is formed on the compensation cushion layer and the substrate and a second plasma treatment is applied to the cushion layer; a gap is formed A wall layer on the cushion layer, the gap wall layer is formed by a rapid heating chemical vapor deposition method; and a part of the gap wall layer, a part of the cushion layer and a part of the compensation cushion layer are formed to form the gap Wall and expose the top of one of the gates. 9. For the method of applying for item 8 of the patent scope, wherein the above-mentioned compensation cushion is _ Page 20 531844 6. Scope of patent application A high temperature oxide. 10. The method according to item 8 of the scope of patent application, wherein the above-mentioned compensation cushion is a tetraoxoethoxylate. -1 1. The method according to item 8 of the scope of patent application, wherein the second plasma process is a remote plasma nitriding process. 12. The method according to item 8 of the scope of patent application, wherein the first plasma process is an absorption plasma nitriding process. ¥ 1 3. The method according to item 8 of the scope of patent application, wherein the aforementioned spacer layer is a nitride. 1 4. A method for preventing leakage of a by-product ion in a gap wall, the method includes at least: forming a gate electrode on a substrate, the gate electrode including at least a gate oxide layer; forming a cushion layer on the substrate A gate electrode and the substrate; forming a gap wall layer on the cushion layer, the gap wall layer being formed by an atomic layer deposition method; and removing part of the gap wall layer and part of the cushion layer to form the Gap-wall and expose the gate on top of one of the gates. Page 21 531844 VI. Application scope of patent 15. If the method of scope of patent application No. 14 is applied, the above-mentioned cushion layer may be treated with a plasma; 16. If the method of scope of patent application No. 14 is applied, The plasma process described above is a long-range plasma nitridation process. 17. The method according to item 14 of the scope of patent application, wherein the above plasma process is an absorption plasma nitriding process. 18. The method according to item 14 of the scope of patent application, wherein the above-mentioned spacer layer is a nitride nitride. 19. The method according to item 14 of the scope of patent application, wherein the above-mentioned cushion layer is a south temperature oxide. Φ I WM page 22