TW530389B - Memory array structure and programming method of mask ROM - Google Patents

Abstract

A mask ROM memory array structure comprises plural first conductive layers with the first direction, a dielectric layer covering the first conductive layer, plural second conductive layers with the second direction on the dielectric layer and a contact plug for selectively connecting the first conductive layer to the second conductive layer according to a coding data. A bit-line selection circuit couples the first conductive layer to provide a detection signal to the first conductive layer. A word-line selection circuit couples the second conductive layer to selectively ground the second conductive layer. A detection circuit is used to detect the above mentioned detection signal level and read the data.

Description

530389

Memory array structure of curtain-type read-only memory About a mask structure and programming method that is programmed by the setting of the connection between metal layers. The present invention relates to a masking and stylization method, especially a memory array structure with contact plugs or perforations (contact or read-only memory), and the traditional read-only memory () is usually Part of the semi-finished product is made and stored in the warehouse. When mass production is needed, it is programmed according to customer needs (Prog ram mi ng) to shorten the time required for the mask ROM from order to shipment. Time (turn_arundund). At present, the traditional semi-finished method of stylized read-only memory and its characteristics and limitations are as follows: (1) Diffusion programming, which is an early step in the manufacturing process. The stylization step is performed before the fabrication of the metal-oxide-semiconductor (MOS) is determined, so it takes a long turn-around-1ime 〇 (2) implantation stylization (impiantati〇ri pr〇gramming), It is performed in the middle of the manufacturing process. The stylization step is performed after Mos is made and executed before the contact or inter layer dielectric material (Inter Layer Dieiectrics) is formed. The implantation stylization system inserts ions into through Region (Channel Region) to adjust the starting voltage vt (Threshold

Voltage). The time required for the order-to-shipment of this mask-type rom is slightly shorter, which is more accepted by the industry. However, this process requires an additional photomask step to implant Vt, which requires a more complicated process and cost. (3) contact / via programming (conn / VIA Programming), forming contact / via holes (cont / via holes) on the MOS electrodes, and then reusing

530389 V. Description of the invention (2) The contact window / via window plug (Contact / via plug) is connected to the electrode of MOS 'to determine the switch of this transistor. This step is performed later in the process, so it has the shortest turn-around-time ^ °. However, due to the space occupied by the MOS itself plus the dielectric layer to form the contact / via hole, The remaining space leads to a larger area required for the memory cell (Ce 1 1) 'increasing unnecessary production costs. When producing the wafer structure of the mask-only read-only memory (ROM), the shortest time must be considered Inside, the crystal is created according to the code (pr0gram code): Second, the area of the memory cell must be minimized as much as possible to meet the need for improvement. According to the analysis of the above-mentioned traditional technology, it is obvious that the traditional technology is described: ϊ t. In order to solve the above problem, the main purpose of the present invention is to provide a small size and volume from order to order in addition to the cost and complexity of the memory array structure and programming method of ί Γ memory. The time required to shorten the wide-screen read-only memory is to obtain the above-mentioned a = itUrn_ar〇und — time). The memory array structure of the body includes a kind of mask-only read-only memory layer; Layer of dielectric layer The first plurality of conductive layers and the second plurality of conductive layers are placed in the first direction; the first direction is disposed in the dielectric 'and placed in the ^ dielectric thunder »data and selectively electrically connected to the first thunder layer for plugging according to a code The bit line selection circuit is coupled to the contact measurement signal of ^ and the second conductive layer to the first conductive layer. The character line selection pendulum: the conductive layer is used to provide a detection layer to selectively make the second conductive layer The circuit is coupled to the second conductive ground. The detection circuit is $ 5,0503-6499TWF (N); TSMC2001-0287; robert.ptd 530389

It is used to read the data of the above-mentioned signals. . In addition, the present invention provides a method for programming a memory array of a mask-type read-only memory, which is suitable for a word line selection circuit and a word line selection circuit, and includes the following steps. First, a plurality of first conductive layers arranged in a first direction are formed on a substrate and coupled to the bit line selection circuit. Next: a dielectric layer is formed to cover the first conductive layer. Next, a plurality of second conductive layers arranged in the second f direction are formed on the dielectric layer, and are coupled to the word line to select electricity 2 ° Finally, a plurality of contact plugs are formed in the dielectric layer according to a coded data.

The plug 'selectively electrically connects the first conductive layer and the second conductive layer. Example: ^ Refer to FIG. 1. FIG. 1 is a schematic top view illustrating a memory array of a read-only memory (ROM) according to an embodiment of the present invention. The read-only memory memory array according to the embodiment of the present invention includes a plurality of first conductive layers (MA0 ~ MAX) arranged in a first direction a, and a plurality of second conductive layers (MB) arranged in a second direction b. (0 ~ MBγ). A plurality of memory cells are formed at the intersections of each of the first conductive layers (MA0 ~ MAX) and the second conductive layer (MB0 ~ MBΥ). Here, the first direction a and the second direction b need not be parallel. In this embodiment, the first direction & and the second direction b are orthogonal vectors to each other. FIG. 2A is a side cross-sectional view showing a memory cell C00 of a read-only memory (ROM) according to an embodiment of the present invention, and FIG. 2B is a view of a read-only memory according to an embodiment of the present invention ( ROM) side sectional view of memory cell C12. As shown in FIG. 2A, a first conductive layer MA0 is first formed on the substrate 20, and then a dielectric layer 22 is formed to cover the substrate 20 and the first conductive layer.

530389 V. Description of the invention (4) MA0 ‘finally’ forms a second conductive layer MB0 on the surface of the dielectric layer μ. This is the first structure of the memory cell according to the embodiment of the present invention. Another memory cell structure is shown in FIG. 2B. First, a first conductive layer MA1 is formed on the substrate 20, then a dielectric layer 22 is formed to cover the substrate 20 and the first conductive layer MA1, and then on the dielectric layer 22. A second conductive layer MB2 is formed on the surface. Finally, a contact plug 24 is formed in the dielectric layer 2 to electrically connect the first conductive layer MA1 and the second conductive layer 2. According to the present invention, the setting position of the contact plug 24 is determined according to the encoded data of the read-only memory, and the effect of the contact plug 24 on the operation of the read-only memory circuit will be described later. In the present invention, the memory cell having the contact plug 24 is referred to as an On Cell, as shown in FIG. 2B and FIG. 1 by reference numeral ci2; and the remaining memory cells that do not form the contact plug 24 are It is a closed cell. Referring to FIG. 1, the word line selection circuit is coupled to the second conductive layer (MB0 ~ MBY), and has a plurality of mS transistors (sw0 ~ SWY). The drain of each M0s transistor is The source is electrically connected to the corresponding second conductive layer, the source is electrically connected to the ground point, and the gate of each MOS transistor is electrically connected to the line (WL0 ~ WLY). When the word line scanning signal is at a high level, the corresponding MOS transistor is turned on and the second conductive layer coupled to it is grounded. The bit line selection circuit 14 is coupled to the first conductive layer (θΜΑ〇 ～ ΜΑ ° χ) and has a plurality of M0S transistors (SL0 ~ SLX). The source of each m0s transistor is electrically connected to the corresponding A conductive & "α ^ electrical layer, and the pole system are electrically connected to the primary measurement amplifier 16 and the gate of each MOS transistor is electrically connected to the bit, (BL0 ~ BLX). When the bit line When the scanning signal is at a high level, the library M0S transistor is turned on, and the first conductive layer coupled to the transistor is

5. Description of the invention (5) The device 16 is electrically connected. According to the present invention, the memory array structure according to the present invention has an I / O port 18 for output, which is used to output the data stored in the memory. The following describes the implementation of reading according to the present invention. Bay: Operation process. π The memory array described in her example is shown in Figure 1. Taking the reading of the memory cell C00 as an example, when the line WLO is selected, the voltage J field k on the word line WL0 takes a child to make the attendant conductive. Plane MB0 is grounded. Moreover, as mentioned above, since C00 is a closed memory cell (c 1 ose Ce ii), so it is connected to 222, so the second f electrical layer MB0 is not placed in contact with the contact plug and is the first-conductive fine electrical connection. ; Where the line selection circuit 14 of the circuit 14 a, a, + In this case, the current measured by the bit line selection circuit 14 ^ 楗 will not flow through the second conductive layer mb〇. To the ground point, that is, the bit line selection circuit: the current will not be lost ', so the sense amplifier (Sense Afflplifier) ^ can not detect the leakage current and output a logic signal "". In another example, taking the term memory cell C1 2 as an example, when a word line WL2 is selected, the voltage on the sub-line WL2 still turns on the switching element m2, so that the second conductive layer M B 2 is grounded. As a result, as described above, since the memory cell C1 2 is an on-cell, the second conductive layer Mβ2 and the first coupled to the bit line selection circuit 14 are the same as described above. -The conductive layer MA1 is electrically connected. In this case, the detection current provided by the bit line selection circuit 14 will flow to the ground point through the current path provided by the first conductive layer M1, the contact plug 24, and the second conductive layer-2. The detection current provided by the element line selection circuit 丨 4 is lost through the above path and becomes a leakage current. Therefore, the sense amplifier (Sense

530389 V. Description of Invention (6)

Amp 11 f 1 er) 16 detects the leakage current I and outputs a logic signal of “1”. Same: In the application of "month", it cannot be shared between different 1/0 ports. The second path of each port, that is, the first conductive layer of each ι / 〇 soil. The conductive layer is independent. The early conductive layer is electrically connected to the corresponding NMOS switching element. The first conductive layer of the different right 1/0 port outputs the leakage current to the I ^^ element at the same time. The port 1/0 port will read the output signal of the unstable leakage current. The conductive layer design can avoid the above situation. It happened. The memory array provided by the masking surface of the social private second ft invention consists of multiple metal layers. Not only does not require additional light, it can effectively shorten the processing time at the end of the process. Therefore,: 乂 ^ production cost, and ^ ^ ^ ^ ,, rom ^ ^ Electrical layer :: 之: 发: ΐ !: 体: 结 结 法 is limited by MOS memory structure; ^ body structure, Therefore, the screen of no-knowledge technique is called the secret cell :::? : = = Compared with the conventional memory cell size, only the space required to form the side of the mask by two conductive layered wide-body array structures is more decisive: ′ greatly reduced production costs. ^ Lower the screen-type memory. Although the present invention is disclosed in the preferred embodiment, the scope of the present invention is not limited to the spirit and scope of anyone skilled in the art. It can be done without departing from the present invention. First, decoration, so the present invention 0503-6499TWF (N); TSMC2001-0287; robert.ptd page 9

530389 V. Description of invention (7) The scope of protection shall be determined by the scope of the attached patent application

1B Page 10 0503-6499TWF (N); TSMC2001-0287; robert.ptd 530389 The diagram is briefly explained in order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible. A preferred embodiment is given below, and With reference to the accompanying drawings, the detailed description is as follows: FIG. 1 is a schematic top view illustrating a memory array of a read-only memory according to an embodiment of the present invention. FIG. 2A is a side cross-sectional view showing a memory cell C00 of the read-only memory according to the embodiment of the present invention. FIG. 2B is a side sectional view showing a memory cell C12 of the read-only memory according to the embodiment of the present invention. Explanation of symbols: 10 ~ word line selection circuit 14-i bit line selection circuit 16 ~ detection amplifier; 18-'I / O port; 2 0 ~ substrate; 2 2 ~ dielectric layer; 24, 1 contact plug Plug; a ~ first direction; b ~ second direction; C00 > C12--memory cell; BL0 ~ BLX ~ bit line, MA0 ~ MAX ~ first conductive layer MB0 ~ MBY ~ second conductive layer SW0 ~ SWY ~ Switching element;

0503-6499TWF (N); TSMC2001 -0287; robe r t.p t d p.11 530389 Schematic description WL0 ~ WLY ~ Character line _

HiHI Page 12 0503-6499TWF (N); TSMC2001-0287; robert.ptd

Claims (1)

530389 VI. Scope of patent application 1 · A curtain-type read-only " plural number-conducting dwelling, memory array structure, including:-a dielectric layer, arranged in the i-direction; a plurality of second conductive dwelling conductive layers Configured on the dielectric layer: a second-direction pre-element selection circuit that is not parallel to the first direction, and selectively select the first-second conductive layer for grounding one of the first conductive layers; θ is used for selection, +, and 070 line selection circuits, which are coupled to the above-mentioned first lead μ 仏 the above-conductor-conductor-primary-test signal; M $ electrical layer 'is used to raise the contact plug of the village, and is arranged in the above-mentioned medium In the electrical layer, it is used for step-by-step: to selectively and electrically connect the first conductive layer and the first material. -Detect electricity @ to detect the level of the above-mentioned debt measurement signal and read the data 2. As the mask described in item 丨 of the scope of patent application; recall = structure 'where the above word line selection circuit includes ^ 第A plurality of switching elements of a conductive layer are turned on so that the second switching layer is grounded. "Scanning Miao Miao 3. The mask-type read-only memory array structure described in item 2 of the scope of patent application, wherein said switching element is a metal-oxide half (f ^ f body. Transistor 4. The mask-type read-only memory memory array structure described in the above item, wherein the above-mentioned memory array corresponds to a port of grain. M output p.13 0503-6499TWF (N); TSMC2001-0287; robert.ptd 530389 6 5. Patent application scope 5 · The memory array structure of the veil-type read-only memory described in item 1 of the patent application scope further includes a plurality of metal layer groups, and the first conductive layer and the second conductive layer are located on the metal The top layer of the layer group. 6. The memory array structure of the mask-type read-only memory as described in item 1 of the scope of the patent application, wherein the second direction and the first direction are orthogonal vectors. 7.-Kind of mask The memory array programming method of the read-only memory is applicable to a word line selection circuit and a word line selection circuit, and includes the following steps: providing a substrate; forming a plurality of first conductive layers arranged in a first direction on the substrate And coupled to the bit line selection circuit; forming a dielectric layer to cover the first conductive layer; forming a plurality of second conductive layers arranged on the dielectric layer in a second direction that is not parallel to the first direction, and Coupled to the word line selection circuit; and forming a contact plug in the dielectric layer according to a coded data to selectively electrically connect the first conductive layer and the second conductive layer. 0503-6499TWF (N); TSMC2001-0287; robert.ptd Page 14