TW530388B - Flash memory cell with a P-channel - Google Patents

Abstract

A P-channel flash memory cell includes an N-type doped substrate, a floating gate formed above the N-type doped substrate and isolated from the N-type doped substrate by a tunneling oxide layer, a control gate stacked above the floating gate and isolated from the floating gate by an oxide-nitride-oxide (ONO) dielectric layer, a P+ source, a P+ drain, and an N-type doped extension region adjacent to the P+ drain formed beneath the floating gate within a P-channel region of the N-type doped substrate.

Description

530388 V. Description of the invention (1) Field of the invention The present invention provides a p-channel (p-cha η ne 1) flash memory and its manufacturing method, especially a high-efficiency band-to-band penetration (Band-to-band tunneling, BTBT) p-channel flash memory for programming operation and manufacturing method thereof. Background In recent years, as the demand for portable electronic products has increased, flash memory technology and market applications have also matured and expanded. These portable electronic products include digital camera negatives, cell phones, video game apparatus, personal digital assistant (PAI) memory, telephone answering devices, programmable j c and so on. Since most portable electronic products are powered by batteries, how to reduce the energy dissipation and electrical performance of flash memory has become the focus of flash memory development. Basically, it is distinguished according to the doping properties of the substrate and source / drain (S / D). Flash memory can be classified into P-channel and N-type. Channel (N — ^^^ 丨) two

$ 5 pages 530388 5. The characteristics of the invention description (2) s), so it is suitable for the field of portable electronic products that require low energy consumption. The writing method of the P-channel flash memory can be divided into a channel hot hole induced hot electron injection mechanism and a band-to-band tunneling (BTBT) injection mechanism. And Fowler-Nordheim tunneling (FN tunneling) injection mechanisms. 199 5 years, Japan's Mitsubishi 1 \ 0111181 ^ (1〇 and others proposed '| 1 ^ 〇 乂 61 Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron (BBHE) for Flash Memory wi th A P-Channe 1 In the Ce 1 1n paper, the gate induced drain leakage (GIDL) is accelerated by a lateral electric field to generate thermionic electrons which are first applied to the write operation of the P-channel flash memory. See Figure 1 (a ) And FIG. 1 (b), FIG. 1 (a) shows a schematic cross-sectional view of a typical P-channel flash memory cell 10 in a programming mode (programming mode), and FIG. 1 (b) shows FIG. 1 (A) Energy band diagram along the AA 'tangent line. As shown in FIG. 1 (a), the P-channel flash memory cell 1 includes an N-type doped substrate 12 and an N-type substrate. Doped control gate 14, an N-type doped floating gate 16, a P-doped source 17, a P doped anode 18, a tunneling oxide 1 ayer 2 1 between Between floating gate 16 and base 12 and a 0 N 0 reference

530388 V. Description of the invention (3) The electric layer 2 2 is between the control gate 14 and the floating gate 16. Generally in the band-to-band electron pass-through writing mode, the gate is a positive voltage of 10 volts (V ο 11), the drain is a negative voltage of -6 volts, and the base is ground (gr und). The poles remain floating (f 1 0ating). Band-to-band tunneling occurs at 18 poles, generating electron hole pairs, in which electrons are repelled to the channel of the floating gate by the lateral electric field at the drain, and some electrons get high energy to overcome The energy barrier of the oxide layer 21 is tunneled, and the floating gate electrode 16 is injected to complete the writing operation. It should be noted that the writing efficiency of the BTBT mechanism is related to the valance band (Ev) -conduction band (Ec) energy gap at the overlap region of the drain-floating gate. The smaller the energy gap, the BTBT occurs. The easier it is, the higher the write efficiency. Among them, the band-to-band electron crossing mechanism, as shown in Fig. 1 (b), because a positive bias voltage is applied to the control gate, an electric field perpendicular to the direction of the Si-Si 02 interface is generated, which makes the drain and floating gate The inter-overlapping region produces energy band bending, so that the conduction potential of the drain electrode of the overlapping region approaches the valence band potential, and electrons in the valence band pass through to the conduction band, and an electron-hole pair is generated. The electrons are repelled to the channel area by the applied negative pole bias, and some electrons get high energy and are injected into the floating gate to complete the writing operation. It can be seen that the write efficiency of the flash memory of the P-channel band-to-band write mode is determined by the probability of the band-to-band electron crossing. In other words, as long as the probability of band-to-band electron crossing is increased, the write efficiency of the P-channel flash memory can be improved.

Page 7 530388 V. Description of Invention (4) Rate. Therefore, an object of the present invention is to provide a p-channel flash memory device with high write efficiency. This invention is a kind? The channel (^ 1] ^ 111 ^ 1) flash memory unit (^ 133] 1 memory cel 1) 'includes: an N-type doped substrate; a floating gate; the 0N0 dielectric layer is isolated from the floating gate; And a P-doped drain (P + drain); extension region) is formed directly on the N-type doped substrate and a p-channel is formed by a tunneling oxide layer immediately below the p-pole. Isolated from the N-type doped substrate. A control gate is stacked on the floating gate and is one-dimensional; a P-doped source (P + source) n); — N-type doped extension region (n doped The P-doped electrode is formed in the P-channel region of the floating gate. The region is defined as a drain.

The P-doped drain and the floating gate overlap region M-gate overlap region (drain —10—gate N-type doped extension region is used to strengthen the drain-gate lateral electric field (1 a ten prq 〖F; p] η, you & one ... 530388

V. Description of the invention (5) Refer to FIG. 2 for reference. FIG. 2 is a schematic cross-sectional view of a P-channel flash memory cell 402 of the present invention. As shown in FIG. 2, the p-channel flash memory of the present invention includes an N-type doped substrate 42, an N-type doped control gate S ′, a type-doped floating gate 4 6, and a tunneling oxide layer 5 1 between floating gate 46 and substrate 42, a 0N0 dielectric layer 52 between control gate 44 and floating gate 46, a p-doped source 4 7 and a p-doped drain 48, and an N-type doped extension region 49 is formed next to the P-doped drain electrode 48 and is formed in the p-channel region 55 of the N-type doped substrate 42 below the floating gate 46. The overlapped region of ρ-doped drain 浮动 and floating idler 46 is also called dra.in-to-gate overlap region 61, and its overlap length is about 0.05 to 0.1 micrometers. )about. In a preferred embodiment of the present invention, the N-type doped substrate 4 2 is an N-type well (N-we 1 1), which is formed in a lattice arrangement direction with a doping concentration of < 1 0 0 > The surface of a P-type single crystal silicon substrate with a thickness of about 3E15-5E15cm-3. However, the present invention is not limited to this, and other substrates, such as a commercial fossil silicon-on-insulator (SOI) substrate formed by a general SI MOX method, are also applicable to the present invention. The thickness of the tunneling oxide layer 51 is about 90 to 130 angstroms (an g strom). This N-type well system is implanted with an implantation dose of about 1E12 ~ 1E13cm-deficiency phosphate. The P-doped source 47 and the P-doped drain 48 are implanted into BF 2 with an implantation dose of about 1E1 5 cm 2. The N-type doped extension region 49 is formed by squamous pocket ion implantation (ρ oc k e t i m ρ 1 a n t), and the implantation dose is about 1E13 to 1E14cm_2.

Page 9 530388 5. Description of the invention (6) In other embodiments of the present invention, the N-type doped extension region 49 can also be formed by using arsenic pocket ion implantation or other N-type ion implantation methods. The implantation energy and implantation amount can be obtained by those skilled in the art after reference and modification of the content and purpose of the present invention to obtain an optimal operating range. The technical feature of the P-channel flash memory cell 40 of the present invention is that an N-type doped extension region 49 is added to the P-channel region 55. The N-type doped extension region 4 9 is formed next to the P-doped drain electrode 4 8 and is formed around the drain-to-gate overlap region 6 1 and under the floating gate P channel region 5 5 toward the P-doped source electrode 4 7 extend. In a write mode, the control gate 44 is connected to a positive voltage of 10 volts, and the sink drain is a negative voltage of -6 volts, while the substrate is grounded, and the source remains floating. The electrons generated by B T B T flow out from the poles 4 8 and move toward the channel region under the floating gate. Part of the electrons obtain high energy and can overcome the energy barrier of tunneling the oxide layer 51 and are injected into the floating gate 46. As mentioned earlier, the writing efficiency or electron penetration probability of the BTBT mechanism is related to the valence band (Eν) -conduction band (Ec) energy gap at the overlap region of the drain-floating gate. The greater the chance of occurrence. The N-type doped extension region 49 of the P-channel flash memory cell 40 of the present invention can significantly increase the writing efficiency of the P-channel flash memory cell 40 via the BTBT mechanism. This may be because the N-type doped extension region 4 9 strengthens the lateral electric field (1 a t e r a 1 f i e 1 d) near the overlapped region of the drain-to-gate overlap 6 1, so that the non-pole-to-gate

Page 10 530388 V. Description of the invention (7) Electron acceleration of the valence band of the pole overlap region 61 1 can be written in:

The number of BTBWs generated by gaining energy into the conduction band increases ’and then increases through the tunneling oxide layer 5 2: :: The efficiency is improved. Yu Yugu made the writing more explicit, because the N-type doped extension region toward the electric field accelerates the valence charge of the non-pole-to-pole overlap region 6 i / toward the Si-SiO interface of the enhanced side, which makes the electrons I II crosses to the conduction band, forming a BTBT phenomenon. In other words: the negative voltage of the gate is easily applied to the "parasitic hybrid electrode 48", which is generally between m: special between the P-doped drain electrode 48 and the N-type doped sideline electric field. Equivalently, the energy gap between the valence bond band potential energy near the Si-SM plane is reduced, thereby increasing the occurrence probability of the BTBm system. The shutter ί 3 is applied to the p-channel with a single transistor (1T): [: um can be used in the Shaanxi Shan 圮 思 early thinking with a double transistor (2τ). Please refer to FIG. 3. FIG. 3 shows a schematic diagram of the example J: 2 DQ memory unit 70. As shown in Fig. 3, 2τ: Yuan 70 includes a PM 0 # moving gate transistor 7a and a selective pen crystal 3 select transistor 70b formed in an n-type well. In addition, a first The p-diffusion region 77 is used as the source of the pM0s floating gate Merley crystal 70a, a second p is scattered, and the a-electrode transistor 703: and 月 t is used as PM0S. Floating gate: the pole u of the electric sun body 70a and used as the pM0s selection pole, the third P diffusion region 87 is used as the source of the pM electric sun body 70b. 530388

The pole 'is electrically connected to a one-bit line (b i t 1 i n e). The floating gate transistor 70a further includes a floating gate 76 isolated from the N-well 72 by the / tunneling oxide layer 81, and a control gate 74 isolated from the floating gate 76 by the 〆0N0 dielectric / dielectric layer 82. A P-channel region 85 is defined as a region between the surface of the N-well 72 below the floating gate 76 between the first p diffusion region and the first p diffusion region 78. A v-type doped extension region 79 is formed adjacent to the second P diffusion region 78 in the P-channel region 85 of the N-well 72 under the floating gate 76. In this embodiment, the PMOS selection transistor 70b is used to control the current flowing into the PMOS floating gate transistor 70a. PMOS selection transistor 70b includes a gate 84, which can be N-type doped or p-type doped. The thickness of the tunneling oxide layer 8A is about 80 to 130 angstroms. The N-type well 72 was implanted with a dose of about 1E12 ~ 1E13cnr ^ phosphate. The first p-diffusion region 77, the second p-diffusion region 78, and the third p-diffusion region 87 are all implanted with π. The implantation dose is about ^ E ^ Scnr2. The N-type doped extension region 79 is formed by ion implantation with a phosphorus pocket, and the implantation dose is about 1E13 ~ 1E14cm_2. The N-type doped extension region M can significantly increase the writing efficiency of the P-channel flash memory cell 70 through the BTTB mechanism. Extreme snow ΐ 广 Wide flash memory unit, * * Ming Department ☆ PM0S floating gate Y ^ ^ ^ ^ plus-N-type doped extension region 79. The N-type doped extension region 79 is formed immediately after the second p diffusion region 78 and is formed in the P-transport region 85 of the floating gate 7. In write mode, applied to the second p diffusion region

530388 V. Description of the invention (9) The negative voltage of (8), the lateral electric field generated at the interface between the second P diffusion region (78) and the N-type doped extension region (79), equivalently reduces S i -S i 0 The energy gap between the conduction band energy near the interface and the valence bond band energy increases the probability of occurrence of the BTBT mechanism. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent. m

Page 13 530388 Simple illustration of the diagram Simple illustration of the diagram Figure 1 (a) shows a schematic cross-sectional view of a typical P-channel flash memory unit. Fig. 1 (b) shows the band diagram along AA 'tangent in Fig. 1 (a). FIG. 2 is a schematic cross-sectional view of a P-channel flash memory unit according to the present invention. FIG. 3 is a schematic diagram of a 2T flash memory unit according to another embodiment of the present invention. Explanation of symbols in the figure 10 P-channel flash memory cell 12 N-type doped substrate 14 control gate 16 floating gate 17 P-doped source 18 P-doped drain 21 tunnel oxide layer 22 ONO dielectric layer 40 P-channel flash memory cell 42 N-type doped substrate 44 N-type doped control gate 46 N-type doped floating gate 47 P-doped source 48 P-doped drain 49 N-type doped extension region 51 tunneling Oxide layer 52 0 N 0 Dielectric layer 55 P channel region 61 Drain-to-gate overlap region 70 2T flash memory cell 70a PMOS floating gate transistor 70b PMOS select transistor

Page 14 530388 Brief description of the diagram 72 N-well 74 Control gate 76 Floating gate 77 First P diffusion region 78 Second P diffusion region 79 N-type doped extension region 84 Select gate 85 P channel region 87 Third P diffusion zone

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Claims (1)

530388 _Case No. 90114369_ 年月 日 __ VI. Scope of patent application 1 1. For the PM0S dual transistor (2T) flash memory cell in the scope of patent application item 7, the N-type doped extension region uses a Phosphorus pocket ion implantation was formed. 12. For example, the PM0S dual transistor (2T) flash memory unit in the scope of the patent application, wherein the implantation dose of the phosphorus pocket ion implantation is about 1E13 ~ 1E14cra_2. 13. For example, the PMOS dual-transistor (2T) flash memory cell in the scope of the patent application, wherein the PMOS selection transistor system is used to control the current flowing into the floating gate transistor. Page 19