TW530350B - Better copper CMP process utilizing dummy plugs in damascene process - Google Patents

Abstract

A method of fabricating a semiconductor wafer having at least one integrated circuit, the method comprising the following steps. A semiconductor wafer structure having at least an upper and a lower dielectric layer is provided. The semiconductor wafer structure having a bonding pad area and an interconnect area. At least one active interconnect having a first width is formed in the interconnect area, through the dielectric layers. A plurality of adjacent dummy plugs each having a second width is formed in the bonding pad area, through a portion of the dielectric layers. The semiconductor wafer structure is patterned and etched to form trenches through the upper dielectric layer. The trenches surround each of the at least one active interconnect and the dummy plugs whereby the upper dielectric level between the adjacent dummy plugs is removed. A metallization layer is deposited over the lower dielectric layer, filling the trenches at least to the upper surface of the remaining upper dielectric layer. The metallization layer is planarized to remove the excess of the metallization layer forming a continuous bonding pad within the bonding pad area and including the plurality of adjacent dummy plugs, thus forming at least one damascene structure including the at least one respective active interconnect.

Description

53〇35〇 ^ ------------- Year, month, day, day and year_ 5. Description of the invention (1)-Background of the invention (1) Field of invention The invention relates to the manufacture of products Circuitry method, and more particularly, a method for plowing integrated circuits with embedded test plugs. (2) Description of the know-how. Steel-inlaid and double-inlaid structures have begun to be used for inner conductors. Inlay-type and mechanical-chemical polishing (CMP) are used to flatten the top surface of copper inner conductors. For a Cmp question. U.S. Patent No. 5,885,856 (Gilbert et al.) Describes a method of forming an integrated circuit with a dummy mesas, adding a design pattern of the product rate f to balance the grinding across the surface of a semiconductor substrate ^ The location of the parent test platform is selected because it will not intersect a well: the boundary or active area, and it will not be lower than the conductive layer or polycrystalline silicon or the inner wire junction. National Patent No. 5, 639, 687 (We ling, etc.) describes a method of leveling the flatness pattern density of different layers of a half-wafer to improve the two-mechanical polishing process of the wafer. Dummy raised lines must be inserted. The gap between the traces is actively conducted on the wafer. U.S. Patent No. 5,544,994 (Gilton) describes a method for forming a bonding pad with flat metal connections to a semiconductor wafer, which can be customized to match different bonding pads and pin fingers. US Patent No. 5, 888, 889 (Fr is ina, etc.) describes a method for making borrowed gifts and gifts to be used in Hang Xi, m μ ι_ _

530350

A dual-mosaic structure is described, and there is no step of forming a two-layer metal inner conductor junction between the two layers without the conversion of U.S. Patent No. 5,801,094 (Yew et al.). U.S. Patent No. 5,266,446 (Chang et al.) Describes a method for fabricating flat multilayer thin film structures on dielectric and substrate substrates by coating the first and second layers of dielectric polymeric metal on the surface of the dielectric substrate. The second upper layer, the metal system is photosensitive, and is exposed and developed to form a shape on it. This feature is related to the characteristics of the first lower layer of the polymeric metal. Deposition covering on the second layer 'and coating the first and second layers. Features: Thicker conductive metal layer is deposited on the crystalline layer, filling the first and first temples = at least to the second layer. Layer, and then a thicker layer. SUMMARY OF THE INVENTION The main objective of the present invention is to provide a metal forming plug for forming a metal test plug and an active inner wire in the early etching step of semiconducting ancient = reverse. This process belongs to this process. The layered copperized invention belongs to the semi-invention, which is another test plug of the invasion machine, and the other of the conductor substrate is reduced to the minimum inlay type. The purpose is to provide a bonding pad area. A single etching step of forming the inner wire region of the inner wire region in the inner wire region is performed. The purpose is to provide a test plug in the copper chemical mechanical research process, which is to grind a large area of 0. The purpose is to provide a test plug that is used in a large area such as a bonding pad area.

Page 9 530350 said Amendment 5. Description of the invention (3) The copper depressions are minimized. Other purposes will be revealed below. The above and other objects of the present invention can be achieved by the following methods, i.e., providing a semiconductor wafer. The structure has at least one upper dielectric layer = a dielectric layer: the semiconductor wafer structure has a bonding pad region $ & & amp λ 鐾: At least one active inner conductor system having a first width is formed in the inner conductor region, and a plurality of adjacent test plug systems each having a second wide lug through the dielectric plate are formed at In the bonding pad area ,: through: a portion of the dielectric layer, the semiconductor wafer structure is patterned and etched to form a ^ groove ^ through the upper dielectric layer, and the groove surrounds each active inner conductor and test plug base ' By removing the upper dielectric layer between adjacent test plugs, the metallization layer is deposited to cover the lower dielectric layer, and the trench is filled to at least the upper surface of the remaining upper dielectric layer, and the metallization layer is planarized. A continuous bonding pad is formed in the bonding pad region by removing the excess metallization layer, and is included in a plurality of adjacent test plugs in the bonding pad region. Therefore, at least one mosaic structure is formed. Contains at least one Individual active inner wires 0 Brief description of drawing number 10 Semiconductor structure 12 Active element 14 Etching barrier layer 16 Inner dielectric layer 18 Etching barrier layer 20 Inner dielectric layer Page 10 530350 Case No. 91100288 Explanation (4) 22 insect-cut barriers 24 semiconductor wafer junctions 30 inner conductor area 32A active inner conductor 32B active inner conductor 33A width 33B width 34A via hole opening 34B via hole opening 36A metal plug 36B metal plug 37A groove 37A, Groove 37B Groove 37B, Groove 39A Double mosaic structure 40 Pad area 42A Test plug opening 42B Test plug opening 43A Width 43B Width 46A Test plug 46B Test plug 47A Trench 47A, Tungsten test plug

Page 11 530350 No. 91100¾¾ V. Description of the invention (5) 4: 7 B groove 4 7 B tungsten test plug 4 9 A flat joint 4 9 B flat joint pad 6 〇A metallization layer 6 0B metallization layer 6 2 A passivation protective layer 62B passivation protective layer 7 9 A second barrier layer 7 9 B second barrier layer 1 00 bottom 2 0 0 pattern repair is better and can be interposed and better Detailed description of the embodiment As shown in FIG. 1, the two embodiments of the present invention are the same, starting from a semiconductor structure 10 having at least one exposed active element 12, and may also include a semiconductor wafer or substrate, the active and Passive components are formed in crystals, conductive layers, and dielectric layers (such as polycrystalline interlayer oxide (丨 p〇), metal interlayer dielectric (IMD), etc.) to form and cover the surface of the wafer, or a semiconductive structure 10 It may be a semiconductor substrate with an active region 12, such as a wafer, and the electrical layer 16 may represent an IMD layer and / or an ILD (Internal Dielectric Layer) layer. The term "semiconductor structure 1 '" includes a semiconductor substrate The components in the wafer and the layers on the wafer. The active element 12 may represent a conductive line / in the dielectric layer, and the active it # 12 is a doped region in a substrate of the first generation.

Amendment No. 91100288 V. Description of the Invention (6) Unless otherwise specified in detail,-it is achieved by known conventional methods. Page… structures, such as layers, can form a semiconductor structure etching stop layer (the bottom is covered by the semiconductor structure 10 and the active device 丨 2 d stop layer) 1 4 series formation covering 1 6 series formation covering the lower etching stop layer 丨 lower Dielectric layer (I LD) part etch stop layer) 18 is formed to cover the lower 3 ′ eight lower layer etch stop layer (intermediate dielectric layer (ILD) 20 series is formed to cover the second electric layer 16 and the upper part is insulated from the inside) (The top is engraved to block:;, the block layer 18 is etched, and the upper layer mimo is engraved. This constitutes a semiconductor covering the upper interposer.

SiO2), Si3N4 (nitride stone), or Si0 (2f (silicon carbide, carbon-containing electrical material, organic low-dielectric constant material 2): milk most stone material), such as dielectric formation ' The bottom etch stop layer 14 may be: most, the nitride etch stop layer 18 may be from about. To = 2, 15, 2 may be from about 1 500 to 5 Å thick. And the top etch stop layer ILD layers 16, 20 may be formed of $ ^. Or a low dielectric constant of Cora 1 ^ S 1 1 k,: F 1 are, black diamond, formed, ILD layers 16, 2 are prepared / formed, and most Fortunately, the semiconductor wafer junction by silicon oxide (. 〇2)-1: 1 can be right to 15, _ Angstrom thick. The bonding pad area 40 can be Ren Fu Shi = including the inner conductor area 30 and the bonding pad area 40, Any row with less than one test embolism, or a large area for short, can have a domain. For any area, the bonding pad area includes a typical large area active element 12, such as _ 屈, # a is shown in Figure 2A to The line 'is in the inner wire area 30. It is formed by the two embodiments of the semiconducting graph of FIG. 6A and the graphs of 2β to 6β, which are circular structures 24. In these two embodiments, page 13, 530350-case No. 91100288_ year and month revision ___ 5. In the description of the invention (7), at least one via hole opening 3 4 A, 3 4 B is formed in the inner wire area 3 〇, and has a test plug opening in a single etching step 42A and 42B are within the bonding pad area 40. The difference in structure between the two embodiments is that the width 33A of the guide hole opening 34A of the active inner conductor 32A in the first embodiment (FIGS. 2A to 6A) is smaller than The width 43A of the test plug opening 42A of the test plug 46A, and in the second embodiment (Figures 2B to 6B), the width of the guide hole opening 3 4 B of the active inner conductor 32B is greater than the test plug 4 6 Test plug opening 4 of B. Width 43B of B. In the first embodiment, as shown in FIG. 2A, the semiconductor wafer structure 24 is patterned and etched in a single etching step to the inner wiring area. In the middle 30, at least one guide = opening 34A is formed to expose the active element 12, and at the same time, a test plug opening 42A is formed in the bonding pad area 40 with spaced intervals. The edge of the process is larger than the marked one. The ruler-etching process was chosen, compared to wide openings. Quick opening, reactive ion etching (RIE) of silicon dioxide can have the characteristics as shown in Figure 7, and depending on the etching process chemistry, that is, the etch rate (E / R) on the vertical axis vs. the horizontal axis The characteristic size, for a special feature, can produce a bell-shaped curve with the largest engraving rate: a special width of the trench to be etched, by changing the etch; chemical! The quality of the first embodiment can be changed Changing the bell curve A to the second left curve may change the bell curve on line B) by changing the remaining process chemistry ^ Invert the clock.

The bell-shaped curve B ’of the embodiment is that the narrower groove size has a maximum of $ 14 pages 530350

V. Description of the invention (8) The single-step etching process of the first embodiment etches the narrower via hole opening 34A 'of the active inner conductor 3 2A, which is much faster than the wide test plug opening 42A, because the reverse R 1E ( (Reactive ion etching) delay effect, that is, the wider, the opening area is engraved more slowly, because the concentration of etching species is reduced due to by-products. The via opening 34A extends through the etch stop layers 14, 18, 22, and the ild layers 16, 20 to expose the active element 12. The width 33A (or f) of the via opening 34 A is preferably less than 4000 angstroms. The end of the hole opening 34A is limited by the performance of the process. The via hole opening 3 4 A provides an electrically coupled combined component of the integrated integrated circuit on the semiconductor wafer 10, that is, the active component 12. The test plug opening 4 2 A can be etched through the upper remaining resist layer 2 2, the upper inner dielectric layer 20, the lower etch stop layer 18, and partially into the inner dielectric layer 16 (to a most Depth from 1 00 to 80 0 0 angstroms), the test plug opening 4 2 A is etched, so that the subsequent formation of test plugs and bonding pads will not interact with any integrated circuits on the semiconductor wafer. The elements are electrically connected together. The test plug opening 42A is preferably deep between 2000 and 16,000 Angstroms, and the width 43A (> 2f) of the test plug opening 42A is preferably less than about 80 000 Angstroms and 4 3 A wide It is limited by the performance of the process. Because the width of the pilot hole opening 34A is equal to "ρ", the width of the wider test plug opening 42A is greater than twice the width of the pilot hole opening 34A "f", that is, the width of the test plug opening 4 2 A is approximately > 2 f. Alternatively, the width 33A of the guide hole opening 34A is smaller than the width 43A of the test plug opening 42A by about 50% or more.

530350

V. Description of the invention (9) The opening 3 4 A is formed and arranged in the test plug opening 4 2 A. The barrier layer < consists of T a N or T a 'and may include a lower barrier. Layer portion and / or upper metal crystal layer portion. As shown in Figure 3A, a metal layer (not shown) is deposited on the structure, filling the via opening 3 4 A and the test plug opening 4 2 A at least with the upper etch stop layer 2 2 — The metal layer is then planarized, preferably by chemical mechanical polishing, to form a metal plug 3 6 a in the inner lead region 30, and a test plug 46A, a metal layer and a metal plug 36A and a test in the bonding pad region 40. The plug 46A may be composed of copper (Cu), or aluminum (A1) and preferably tungsten (w). As shown in FIG. 4A, the structure is patterned, and the upper etch stopper layer 22 and the upper inner dielectric layer 20 are etched to the lower etch stopper layer 8 to form a trench 37A (for example, a 'line trench') And adjacent to the tungsten metal plug 36A, and forming a trench 4 7 A ′ and adjacent to the tungsten test plug 4 6 A, the lower remaining resist layer 18 forms the bottom of the trenches 37A, 47A. Note that although the trench 37A Any different widths between the trenches 47A (two sets of 37A and 47A) are only etched to the lower remaining resist layer 18. All the upper #etch stop layers 22 and the upper inner dielectric layer 20 between the adjacent tungsten test plugs 46a formed in the trench 47A are removed. A selective second barrier layer 7 9 A may be formed and arranged in the trench 3 7 a and formed and arranged in the trench 47A. The barrier layer 79A may include a lower barrier layer portion and an upper portion. Metal crystal layer part. As shown in Figure 5A, the metallization layer is deposited on the structure to fill the trench 37A adjacent to the tungsten metal plug 36A and the trench 47A adjacent to the tungsten test plug 46a, at least as high as the upper etch stop layer 22, The metallization layer 60A may be prepared by Yan (W), Shao (A1), an aluminum alloy, or copper (c).

530350 _ Case number 91100288 V. Description of invention (10) (Cu)

As shown in FIG. 6A, the copper layer 60A is flattened. To remove excess copper metal and form: a flat double damascene structure 939α in the inner conductor area 30, consisting of a tungsten metal plug 36A and a copper metal filled trench sample 37A '; and a continuous flat bonding pad 49A for bonding The pad area 40 is composed of a tungsten test plug 47A ′ and a copper metal filled trench 47A. A flat passive protection layer 62A is deposited on the structure and patterned to expose a continuous flat bonding layer 4gA in the bonding area 40. For example, the passive protection layer 62A may be made of silicon nitride, SiC, SiO2 or S0G. As shown in FIG. 2B of the second embodiment, the semiconductor wafer structure 24 is patterned and etched in a single etching step to form at least one via hole opening 34B ′ in the inner conductor region 30. The active element 12 is exposed, and at the same time, a test plug opening 4 2 B is formed in the joint area 40 with a spaced phase. An etching process is selected, which is a narrower opening that is faster than a wide opening. During the etching process, more by-products will be generated in the wider opening (via opening 3 4 B), which affects the type of etching. And thus reduce the money engraving rate in a wide opening (via hole opening 3 4 B) versus a narrow opening (in test plug opening 4 2 B), for example, the chemistry of etching may be included. The single-step etching process of the second embodiment etches the wide via opening 3 4 B of the active element 3 2 B faster than the narrow plug opening 4 2 B because of the RIE delay or micro-filling effect as described above.

Via opening 34B extends through the etch stop layer 丨 4, 18, 22, and ILD

Page 17 530350 V. Description of the invention (11) The layers 16 and 20 expose the active element 12. The width 33B of the via hole opening 34B is preferably less than 80 0 0 angstroms. The end of the via hole opening 34B is determined by the performance of the process. As a limitation, the via hole opening 34B provides an electric handle and a combined component, which is an active component 12, that is integrated with the integrated circuit on the semiconductor wafer. The test plug opening 42B can be etched through the upper etch stop layer 22, the upper inner dielectric layer 20, the lower etch stop layer 丨 8, and partially into the lower ILD layer 16 (to one preferably from 1,000 to 8 The depth of the test plug opening 42B is etched so that the subsequent formation of test plugs and bonding pads will not be electrically connected to any joint components of any joint integrated circuit on the semiconductor wafer. The test embolic opening 42B is preferably deep between 300 and 16,000 angstroms,

The width 4 3 B of the test plug opening 4 2 B is preferably less than about 400 angstroms. The end of the width 4 3 B is limited by the performance of the process. The width 43B of the test plug opening 42B is about 80% or less than the width 33B of the guide hole opening 34B. A selective first barrier layer (not shown) may be formed and arranged in the via hole opening 34B, and formed and arranged in the test plug opening 42B. The barrier layer may be composed of TaN or Ta, and may include a lower portion A barrier layer portion and an upper metal crystal layer portion. As shown in FIG. 3B, a metal layer (not shown) is deposited on the structure and fills the via hole opening 34B and the test plug opening 42B at least with the etching stopper layer 2 2-and then the metal layer is planarized. It is preferable to form a metal plug 36B in the inner wire area 30 and a test plug 46B in the bonding pad area 40 by chemical mechanical polishing. The metal layer and the metal plug 36B and the test plug S46B can be copper (Cu), Or aluminum (A1) and preferably tungsten (W).

Page 530 350

As shown in FIG. 4B, the structure is patterned, and 22 and the upper ILD layer 20 are etched to the lower etch stop layer to protect the groove 37B (such as a 'line groove') adjacent to the crane metal plug 36B. ), And the groove 47B adjacent to the test plug 46B is formed, and the bottom of the etch stop layer 18 is shaped at the bottom of the 37B, 47B. Note that although the grooves 37β and the groove " 47B) is only etched to the etch stop layer 18. All the upper #etch stop layers 22 and the upper ILD layer 20 between adjacent crane test plugs 46β formed in the trench 4 "are removed. A selective second barrier layer 79B may be formed and arranged in the trench 37b, and formed and arranged in the trench 47B. The barrier layer 79B may include a lower barrier layer portion and an upper metal crystal layer portion Serving.

As shown in FIG. 5B, the metallization layer 60B is deposited to cover the structure, and the trench 37B adjacent to the tungsten metal plug 36B and the trench 47B adjacent to the tungsten test plug 46B are at least as high as the upper etch stop layer 22, The metallization layer 60B may be composed of tungsten (w), aluminum (A1), an aluminum alloy, or copper (Cu), and preferably steel (Cu). As shown in FIG. 6B, the copper layer 60B is flattened. It is better to use * CMp, = to remove excess copper metal and form: a flat double damascene structure 39b in the inner conductor region 30, which is plugged by tungsten metal. 36β and copper metal filled trench 37B '; and continuous flat bonding pad 49b in bonding pad area 40, consisting of crane test plug 47B' and copper metal filled trench 47B. A flat passive protective layer 6 2 B is deposited on the structure and patterned to expose a continuous flat bonding pad mb within the bonding pad area 40,

530350 Amendment No. 91100288 V. Description of the invention (13) 0. Selection structure of the second embodiment. Figure 8 illustrates the selection structure of the second embodiment. On the feature size), the small test plug opening 42B will be patterned even smaller than the design size, 'due to the type of optics. Subsequently, when the via hole opening 34β has been etched, the middle etch stop layer 18 describes the test plug opening 42β 'The test plug opening 42B is narrow. -I 'And that is, the test plug opening 42β is only covered by the layer 18 ′, that is, 100 ′. The structure of FIG. 8 will replace the structure of FIG. 2β. Second, as described above, the difference is as shown in FIG. 8 The test plug shown in the figure is opened to a depth of 1 ^ 42A. The opening of Ju Wangji The following are some of the advantages of the present invention. 1 The method of this month proposes better control of the depression and money invasion performance in the CMP process. Said I 彳 彳 and pride 2 Another main advantage is that the joint 测试 is formed according to the present invention due to the testing of the metal anchors 46a and 46B. And attached to the bottom dielectric layer. According to the 按 pattern of 乂 佳 黏 46A A :, and test the metal plug (circle open from Figure 9A to Figure 9C in J (or large area 4 °)), trapezoidal; such as described in Section The present invention has been well known, but it is specifically stated that the person who has studied this technique / tested eight cars and said it is a good example, and said that the change in the application of this technique can be changed without departing from In the form and details, the brigade and the couple are -------- the spirit and scope of this Maoyue · page 20 530350 ------ 9110 (¾_ ± _R_ Nichrome · τ : __ Brief illustration of the features and advantages of the method of manufacturing a semiconductor structure having at least one integrated circuit according to the present invention will be more clearly understood from the following description in conjunction with the drawings, in which the same reference numerals represent similar or equivalent elements , Area and part, and among them: 〃 Brother 2B to 6B is the first picture, 2A to 6A. _ Called Dobexianbei cross section of the two embodiments of the present invention w Figure 7 In order to plot the etching rate (E / R) versus the formation of trenches in silicon oxide layers with different etching chemistries. The inch chart is shown in Figure 8 which is the Two embodiments ^ Figures 9A to 9C are diagrams of the present invention ^. Pad, or a test plug in a large area is a plan view illustrating the joint.

Page 21

Claims (1)

530350 — ^ VI. Application for patent scope 1 · A semi-conductor provided in the method of inlaying 裎-a semi-lower part to form at least an electrical layer, adjacent to the electrical layer, patterning and depositing the upper wire and depositing a gold at least to Pingyuanhua ~ Continuous proximity measurement includes the 2 · If you apply for an active internal conductive connection in the integrated circuit 91100288 repair-embedded process, the manufacturing wafer, the conductor wafer dielectric layer; the wire area, one active the active Internal test and test plug each half of the test engraved with the semi-dielectric layer; the test plug part of the dielectric layer belongs to the remaining upper metallization layer bonded to the test plug; at least one range of the first wire will be crystal together, and any connection A better copper CMP method using test plugs in Year A is to manufacture a circuit with at least one integrated circuit. The method includes steps: a structure is a system with at least one upper dielectric layer and the semiconductor wafer structure has- The inner conductor region has a first width and passes through the dielectric wire, and a plurality of the conductors are formed in the bonding pad and penetrate a part of the dielectric wire. The plug has a second width; a conductive wafer structure to form a trench and pass through the trench to surround each of the at least one active part, thereby removing the lower dielectric layer covering between the adjacent test plugs Filling the upper surface of the trench dielectric layer; and removing the excess metal layer to form the bonding pad area, including the plurality and forming at least one mosaic structure, each of which includes Active inner conductor. The method according to item 1, wherein the at least one integrated component of the integrated integrated circuit is on the circle and the test plug does not electrically connect any integrated components on the wafer. Mouth 530350 Case No. 9110028S Amendment VI. Patent application scope 3 · The method described in the patent application scope No. τ ^ Gudi 1 method, wherein the first real poem of each active inner conductor ^ ^ See also the degree system Less than the second rabbit degree of each of the test emboli. 4 • The method as described in the first patent application, item 1 ^ ^, coin 丄, wherein the first wide 庳 γ t visibility of each of the active inner leads is greater than the second degree of each of the test plugs. 5 • According to the scope of application for patent # L consists of-metal, i: the method described, wherein the dielectric layer is glass), and the low dielectric constant ^ metal system is selected from oxidized stone, FSG (Dunbo diamond , Or c〇ral. = Group of materials, such as Silk, Flare, black covering the continuous bonding potential ^ includes a formation-passive protection layer composed of at least 'metal, the metal; =: f passive protection layer can be -Group. _ Is selected from silicon nitride, Sic, and Si〇 2 · as in the scope of the patent application] line and the test plug is the method described by ", wherein the active internal conduction tungsten, copper, and Shao's group of T metals, this metal is selected from its own, the metal is selected from steel and 4 metallization layers are composed of a group of metals. 7 · For example, the scope of patent application 1 =, tungsten, aluminum, and aluminum alloy The line and the test plug are composed of the method described by Min, in which the active internal guide is composed of ~~, and the metallization layer is made of copper 8 as described in the scope of patent application; the item is made of a metal Composition, the method described in the above 'wherein the dielectric layer is glass), and the low dielectric constant I material is selected Since silicon oxide, FSG (fluorine-based glass sample plug from the group of a known metal; inner lead and the measured active ,,, into the metal-based selected from tungsten, copper, Page 23 530 350 ^ No. 91 6. The group of patent application scope and inscription; and the gold 9 genus is selected from steel and crane:; =;: metal, the gold forms-pure protection layer to; cover = = =; and includes; The passive protective layer can be formed from a group of gasified rocks, Sic, and silicon on the pad of a metal. The metal is selected from :: Please refer to item i of the patent scope. 0 is composed of siliconized silicon. ; The blunt away companion tank exhibition I, wherein the dielectric layer is the active inner lead and the test pin i is formed. 2 composed of fossil evening; layer is composed of copper. ,, and, and the metallization, such as the method described in item i of the patent application, the at least one active inner conductor and the upper part and the upper part are provided with a step of forming a barrier layer; and The :: layer: intermediate dielectric thunder = 2: there is formed between the test plug and the upper dielectric layer and the lower dielectric layer of the portion. 1. The method as described in item i of the patent application, further comprising the step of forming a barrier layer on at least one active inner conductor and the upper and lower dielectric layers; and actively performing the single etching step ^ The lead and the test plug are formed between the test plug and the upper dielectric layer and the lower dielectric layer before the step of forming the test plug. The barrier layer includes a barrier layer portion and covers the barrier layer. The layer part of the barrier layer; The method according to item 1 of the patent application scope, wherein the metal layer planarization step is processed by chemical mechanical polishing. ’• — ^, Tunmu * 25 /! ≫ a yflil Λ ^ type for manufacturing half-conductor wafers with at least one integrated circuit ^ 0350 ^ 0350 ΛΐΙ 911QQ288 year j plus positive θ VI. Application ^^ $ Method 'The method includes the following steps: structure, which has-semiconductor structure residual insulation layer insulation: upper surface,-covered by semiconductor junction resistance 划 Γ Dielectric layer, the dielectric layer covering the lower dielectric layer reproduces the upper part% 禺 θ on the etch stop layer, the upper etching resist layer covering the upper dielectric layer, the layer, the semiconductor structure Has a bonding pad region and an inner: region in which at least one active inner conductor is formed in the inner two f regions and passes through the upper remaining resist layer, the upper dielectric layer, and the resistance: Γ: = Γ: Dielectric layer and semiconductor structure remaining number: kg; U2 'line has a first width, and a plurality of adjacent test plugs are formed in the technician to block the deer, enter the pad and etch through the upper part , Θ. " Electrical layer, and lower etch stop layer, and at least a part of the dielectric layer, each test plug has-the second wide path of the combined components are electrically connected together, and the test]; =: i round i Any integrated component of any integrated integrated circuit "i Pattern and etch the semiconductor structure to form a trench-like etch stop layer and the upper dielectric layer to the: through or above, the trench surrounding each at least A main = j etch stop layer plug to remove the line between the adjacent test plugs and the test plug insulation layer and the upper dielectric layer; Page 25, 530350, Case No. 91100288 Amended on June 6, patent application scope Deposit a metallized layer to cover the etched upper etch stop layer and the upper dielectric layer, fill the trench at least to the upper etch stop layer A surface; planarizing the metallization layer to remove the excess metallization layer to form a continuous bonding pad in the bonding pad area, and including a plurality of adjacent test plugs; and forming at least one dual damascene structure, the system It includes at least one respective active inner conductor; forming a flat passive protection layer to cover the semiconductor structure; and patterning the passive protection layer to expose the bonding pad area. 14 The method as described in item 13 of the scope of patent application, wherein the first width of each of the active inner leads is smaller than the second width of each of the test plugs. 15. The method as described in item 13 of the scope of patent application, wherein the first width of each of the active inner leads is greater than the second width of each of the test plugs. 16. The method as described in item 13 of the scope of the patent application, wherein the etching stop layer is composed of a metal selected from the group of silicon nitride, Si C, and Si 02; The electrical layer is composed of a metal selected from the group of silicon oxide, FSG (fluorine glass), and a low dielectric constant material, such as Silk, Flare, black diamond, or Coral: the passive protective layer It may be composed of a metal selected from the group of silicon nitride, SiC, and SiO 2. 17. The method according to item 13 of the scope of patent application, wherein the active inner lead and the test plug are composed of a metal, and the metal system Page 26 53〇35〇 ^^ Case No. 91100288 The scope of the patent application is to revise j selected from the group of tungsten, copper, and aluminum; and the metallization layer is composed of a gold ^ 'the metal system is selected from m Lu, and Jie Jin's group. 8 The method described in item 13 of the patent scope, wherein the 2: wire and the test plug are composed of cranes, and the metallization layer is composed of steel. The method described in the item of “He” you 19 is Γ " ... The money is carved s. Γ Ba Ji system * metal is composed of 'the metal system selected from the group of silicon nitride, Xi: V following 2 group; the dielectric The layer system is composed of -metal, and the number = is a group selected from the group consisting of self-oxidizing stone, FSG (fluorine glass), and low-level materials. And a low-dielectric constant group; the active inner conductor and the test plug are composed of a -metal layer and a metal, and the metal system is selected from the group of copper, gold, and aluminum alloys. The method described in item 2 of the scope of the patent application is the method of engraving the barrier layer composed of nitride nitride; the dielectric layer is composed of oxidation / protective layer is composed of said fossil evening = Lead and: the test plug is composed of crane; and the copper. Sentence 1 • training the method described in item 13 above, the step of forming a -barrier layer between the at least one active inner conductor and the upper part of the souther; and 530350 _ Case No. 91100288_ YYYY__ VI. Scope of patent application Before the lead and test plug formation step, it is formed between the test plug and the upper dielectric layer and the lower dielectric layer of the part. 2 2 · The method as described in item 13 of the scope of patent application, further comprising the step of forming a barrier layer between the at least one active inner conductor and the upper and lower dielectric layers; and Before the step of forming the active inner lead and the test plug in the etching step, it is formed between the test plug and the upper dielectric layer and the lower dielectric layer of the portion; wherein the barrier layer includes a barrier layer portion, and A portion of the crystal layer covering the portion of the barrier layer. 2 3. The method as described in item 13 of the scope of patent application, wherein the gold and metal layer planarization step is processed by chemical mechanical polishing. 2 4 · A better copper CMP process method using test plugs in a damascene process. The manufacturing method is to manufacture a semiconductor wafer with at least one integrated circuit. The method includes the steps of: providing a semiconductor structure having An upper surface of the semiconductor structure etching stopper layer, a lower dielectric layer covering the semiconductor structure etching stopper layer, a lower etching stopper layer covering the lower dielectric layer, and a lower etching layer An upper dielectric layer on the barrier layer and an upper I-etched barrier layer covering the upper dielectric layer; the semiconductor structure has a bonding pad region and an inner conductor region; the etch barrier layer is made of silicon nitride The composition and the dielectric layer are composed of silicon dioxide; in a single etching step, at least one active tungsten inner wire is formed in the inner wire region, and passes through the upper etch stop layer and the upper dielectric Page 530 350 i number 9nnn9 slave six, the scope of patent application _ layer, lower etching stopper layer, lower dielectric layer, uncut stopper ja, for your company, + apricot <, Japan and Japan semiconductor ,,, 0 structure-pad: empty ? Several adjacent test plugs are plugged in the interface pad, and pass through the upper etch stop layer, and must be: part of the touch stop layer, and at least partly to the next two; two ^ an active inner wire on the wafer- The connected joint elements are electrically connected together, and the test test = any joint element of any integrated integrated circuit; an electrical diagram to form a trench through the upper rural barrier layer and the upper dielectric layer to The trench surrounds each of the at least one active inner, ^ ,,,,,,, and ', thereby removing the upper between the adjacent test plugs: = the plug layer and the upper dielectric layer;] u 上 # # Engraving resistance: 7 copper metallization layer covers the upper dielectric layer of the rhyme and fills the upper dielectric layer of the trench; / millimeter etching resistance leveling: denting the copper metallization layer, In order to remove the excessive copper metallization layer, a continuous bonding pad is formed in the bonding pad area and includes “^ adjacent test plugs; and at least one double inlaid junction is formed, including at least one Separate active inner wires; forming a flat silicon nitride passivation protective layer • on the semiconductor structure ', and patterning the nitrogen fossil Tokyo passive protective layer to expose the bonding pad area. * The application method of claim 24 patents range, wherein each Page 29 530350 VI. Scope of patent application The first width of the active inner wire year, month, month, and correction, 2 6 7 2 8 2 9 degrees, is less than the second width of each of the test plugs. • The method according to item 24 of the scope of patent application, wherein the first width of each of the active inner leads is greater than the second width of each of the test plugs. The method according to item 24 of the scope of patent application, further comprising the step of 'forming a barrier layer between the at least one active inner conductor and the upper and lower dielectric layers; and Step 2 Before forming the inner lead and the test plug in the step 2, a method described in item 24 of the patent scope of the stomach is formed between the test plug and the upper dielectric layer and the lower dielectric layer of the part. 'Still included ^ to S = active inner conductors and the upper and lower dielectric layers moving inner conductors; and steps; and ί the single etch step main plug and the top 1: before the formation step' is formed in the Test the barrier layer ::: and between the lower dielectric layer of the part;. The barrier-barrier layer part of the second layer part: the barrier layer part, and-covering the cmpKJ: type ::: use A method for testing a plug for a better copper body circuit is to manufacture a circuit with at least one product: a circle guide, a circle system, a method including a step, a lower dielectric layer, and a substrate. The upper dielectric layer and the earth's dielectric layer and the undercut barrier layer cover; the + conductor structure is etched Engraving resistance 2: Covered on-semiconductor structure ~ on the ply layer; the semiconductor wafer structure has 30 pages 530350 _ case number 91100288 _ month and month amendment _ 6, the scope of the patent application has a bonding pad area and an inner wire Area; forming at least one active inner conductor having a first width in the inner conductor area, passing through the dielectric layer and the #etched insulation layer, and forming a plurality of adjacent test plugs in the bonding pad to pass through A part of the dielectric layer and the uppermost etch stop layer immediately stop at the etch stopper layer below the uppermost etch stopper layer, and each test plug has a second width; the first A width greater than the second width of the adjacent test plug; patterning and etching the semiconductor wafer structure to form a trench through the upper etch stop layer and the upper dielectric layer to the lower etch stop layer; the A trench surrounds each of the at least one active inner conductor and the test plug, thereby removing the upper etch stop layer and the upper dielectric layer between adjacent test plugs; depositing a metallization layer on the The button-etched upper I-etching barrier layer and the upper dielectric layer, filling the trench at least to the upper surface of the upper etch-blocking layer; and planarizing the metallization layer to remove excess metallization layer, Forming a continuous bonding pad in the bonding pad area and including a plurality of adjacent test plugs; and forming at least one double inlay structure including at least one respective active inner lead.