TW530311B - Address decoder circuit and flash memory - Google Patents

Abstract

A clock control circuit receives an external clock signal and generates an internal clock signal. Through use of internal programming and an external trigger signal, the clock control circuit blocks out one or more of the clock cycles of the external clock signal to generate the internal clock signal. The clock control circuit can be used in any semiconductor device, and especially in synchronous flash memory devices with a burst operation. In the synchronous flash memory devices, one or more of the internal clock cycles are blocked out to account for increased delays during certain data sensing operations such as word line switching during data reading. In the synchronous flash memory devices, the sensed data is stored in input/output buffers and transferred out synchronously to the external clock signal. A decoder circuit has two separate portions, a low voltage portion and a high voltage portion. Through the use of the high voltage portion, the decoder circuit is capable of supplying high program voltage. Through the use of low voltage portion and isolated from the high voltage portion, quick read operation is performed.

Description

53〇3i! A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (1) Reference to the definition of the patent application · This patent application is a temporary US patent filed on July 29, 1999 The application, entitled "Clock Control Circuits and Decoder Circuits and High-Voltage Comparators", filed an application, which is incorporated herein by reference. BACKGROUND OF THE INVENTION The present invention relates generally to semiconductor devices, and more particularly to a clock control circuit for controlling an internal clock signal of the semiconductor device, and particularly a non-volatile semiconductor memory device such as a flash memory device. Generally speaking, a flash memory device includes a bit sequencer, a column and row decoder, a sense amplifier, a write-out amplifier, and an array of memory cells. An example of a flash memory device is described in U.S. Patent No. 5,490,107, the contents of which are incorporated herein by reference. The memory cell array includes a plurality of memory cells arranged in rows and columns. Each memory cell has the ability to hold a single piece of information, and a row of memory cells collectively combines a bit line in the memory cell array. The row decoding state Ik co-location sequencer selects a bit line. Similarly, the memory cells arranged in a row of the memory card 7L array are collectively combined to a word line. This row is decoded to select a word line with the address sequencer. The column and row decoders together with the address sequencer select a different memory unit or group of memory units. ----------- Installation (Please read the precautions on the back before filling out this page) Memory memory and memory cells in the memory cell array of flash memory devices are usually grouped Becoming a sub-array is called a memory cell segment. Each memory segment is coupled to a sense amplifier and a write-out amplifier. This write out zoom

Single line late

------------ !! (Please read the note on the back # · Fill this page first} 1111 · 11111111 A7 V. Description of the invention (2 The voltage is stored in the country and stored in advance. The selected memory unit is called a day or write operation. Similarly, a set of predetermined voltages are applied to the selected memory unit to let the information be identified and sensed by the sense amplifier. The action is called a read operation. The speed of fetching and writing # is often increased in order to obtain high-performance, fast, memory devices. One way to increase read operations is to synchronize and synchronize. This read operation is performed to an external clock, and the speed of the read operation is improved. However, under certain conditions, a special read operation may take longer to implement than other fetch operations, and therefore a synchronous The situation may occur.-For example, when a word line transition occurs, that is, when the last memory cell is read along a previous word line within a memory, the first-memory cell is read along a word. A delay is usually experienced. This delay is usually more external One clock cycle of the clock is long, and therefore the read operation of the external clock is synchronized by the burst. As a result, an error occurs. Thus, incorrect data is read from the selected memory unit. The present invention is also roughly It relates to a semiconductor device, and more particularly to a decoder circuit for a semiconductor device, especially an invariant semiconductor memory device such as a flash memory device. In a write-out or programming operation The relatively high program voltage Vpp needs to be supplied to the memory unit by this decoder circuit. Because Zpp circuit must process Vpp, high-waste crystals must be used in this decoding ^. However, the high wish transistor has a Thick oxide layer, and therefore slower operation than money crystal. This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) # 5. Description of the invention (3) Therefore, in order to increase programming and reading It may be advantageous to use a low-voltage transistor for the speed of the operation. Since the high-voltage transistor system is necessary to process Vpp in the decoding circuit, it may be advantageous to lower the voltage. The high-voltage part of the decoding circuit is partially separated. If most of the logic conversion is handled by the low-voltage part of the decoding circuit, this flash memory device will facilitate: increased capacity for fast reading and programming operations. SUMMARY OF THE INVENTION The present invention provides a clock control circuit that receives an external clock signal and generates an internal clock signal, uses a synchronized flash memory device of one of the clock control circuits, and generates the internal clock from an external clock signal. The method of number t. The resulting internal clock and signal money-a selected number of external clock cycle warp segments. The start of this external clock cycle segment is triggered by a

Signal triggered. X + a transcriber combination is used in this control clock circuit to receive external clock and trigger signals. In this recorder combination, the recorders are coupled in series. The -millimeter in the series receives the trigger signal as an input, is picked up by the -material clock, and is provided to the second muffler. In this case, the transcriber also delays this input by an external clock cycle and provides it to the third transcribeer and so on. Therefore, the output-delay trigger signal of each transcriber. The delay trigger signal output by any duplicator is deviated in time by one or more external clock cycles from the delay trigger signal from all other duplicators. The delay trigger signal generated by Shi Li and the clock segmentation signal to generate a 4½ trigger signal. This clock trigger signal is accompanied by this external clock signal. The paper size is translated to Chinese National Standard (CNS) A4 specifications. 530 311 A7

Description of the Invention (5) Thinking in connection with the drawings, it will be easier to understand that when the present invention becomes better understood, the same reference numerals throughout the drawings indicate the same parts. Brief description of the drawings Figure 1 is a top block diagram of a flash memory device of the present invention; Figure 2 is a top block diagram of a specific example of a clock control circuit; Figure 3 is a clock of Figure 2 A block diagram of a specific example of a combination of the transferer of the control circuit; FIG. 4 is a schematic diagram of one of the transferers in the transferer combination in FIG. 3; and FIG. 5 is one of the trigger signal generating circuits of FIG. 2 Schematic diagram of a specific example; FIG. 6 is a schematic diagram of a specific example of the clock buffer of FIG. 2; FIG. 7 is a certain time chart illustrating the relationship between different signals using the clock control circuit of FIG. 2; Figure 9 is a schematic diagram of a specific example of the data timing circuit in Figure 1; Figure 9 (a) is a schematic diagram of a specific example of a set of extended sensing buffer circuits; Figure 9 (b) is a repeated setting of the extended sense Schematic diagram of a specific example of a test buffer circuit; Figure 10 is a certain time chart illustrating the interaction between different signals using the data timing circuit of Figure 8; Figure 11 is a block diagram of a single-bit decoder circuit Which is used as a column decoder circuit and Both line decoder circuits; 530311 A7 V. Description of the invention (Figure 12A-Gate voltage selection circuit of traditional address decoder circuit; (Please read the precautions on the back before filling this page) Figure 12B is a A voltage supplier circuit of a conventional address decoder circuit; Figure 13 is a gate voltage supplier circuit of the present invention; Figure 14 is a traditional address sequencer; Figure 15a is for even bits A specific example of the improved address signal generator of the present invention of the address signal; FIG. 15b is a specific example of the improved address signal generator of the present invention for the odd address signal; FIG. 15c FIG. # No. 16 delay line is used for the generation of address signals by the address signal generator of the present invention; FIG. 16a is a specific example of the address signal generator of the present invention for odd address signals; FIG. 16b is A specific example of the address signal generator of the present invention for even-numbered address signals; Figure 16c is a signal delay line for the use of the address signal generator of the address signal generator of the present invention; the wisdom of the Ministry of Economic Affairs Property bureau employee Figure 17 printed by Fei Cooperative is a block diagram of a specific example of the address sequencer of the present invention; Figure 18 is a block diagram of a specific example of a data sensing plan; and Figure 19 is one of the high-voltage comparators Schematic diagram of a specific example. I. General ^ In Figure 1, a specific example of a synchronous flash memory is shown. This synchronous flash memory has a clock control circuit 2, which is a clock control circuit 2 9 paper size Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 530311 A7 V. Description of the invention (7) Receive the external σM surface k # u3, and combine this external clock signal with a trigger signal 5 to generate an internal clock Signal 7. The one-bit address sequencer 4 receives the internal clock signal 7 and sequentially generates an address signal internal sundial line 7 by addressing in sequence. This address signal is provided to the row and column buffers. 8 This address is "selectively changed and supplied to the row and column decoding circuit. 26 This row and column decoder circuit generates the row and column decoding signal to select memory. The special memory cell in the body cell array 51 is used for reading and regular operation. The mother-memory cell has a structure similar to a peroxygen semi-electric crystal, and because of this, a memory cell has a source region And the drain region are on a base. There is a float and a control between the base and the memory unit. The information is in the memory unit, that is, in this floating gate, by applying a set of pre-amplified voltages to Memory cell. Similarly, a set of predetermined voltages are applied to the Lu Jiyi body cell to read information contained in the memory cell. The memory cell array 51 contains a plurality of memory cells 36, 38, 40, 42, 44, 46, 48, and 50. For simplicity, only a subset of memory cells in the memory cell array 51 are shown. This memory cell 36, 38, 44, and 46 are classified as first Memory unit segment and memory unit, 42 48 and 50 series Classed into the second memory cell segment. Each memory cell segment is combined into a corresponding write amplifier and sense amplifier pair by a corresponding control transistor. In particular, the drain system of the control transistor Combining to a write-out amplifier and a sense amplifier. For example, the first row of control transistors 28 of the first memory cell segment is coupled to the write-out amplifier 16 and the sense amplifier 18. CNS) A4 size coffee x 297 public love) ------- ----------- 1 Pack (Please read the precautions on the back before filling this page) IIII Order 111! 11 Ministry of Economy Printed by the Intellectual Property Bureau's Consumer Cooperatives 530311 A7 ------ B7 V. Description of the Invention (8) Similarly, the drain of the memory cell is connected to the control transistor. For example, the memory cells 36 and 44 The drain is coupled to the source of the first row of control transistors 28. The gate of this control transistor is coupled to the lamp corner code circuit 24 via a decoded signal line. For example, the first and third rows of control transistors 28 And the gate of 30 are combined from the decoder circuit 24 of this row to the decode signal line 29 of the first row. A write-out amplifier and a sense amplifier pair are also combined into an equivalent input / output buffer. In Figure 1, the write-out amplifier 16 and the sense amplifier 18 are combined into an input / output buffer 12, and the write The output amplifier 20 and the sense amplifier 22 are combined to the input / output buffer 14. This input / output buffer is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 2 and 14 are also combined to the external clock signal 3 and data input. I / O bus 1. Before the day-to-day operation, the program data comes to a data wheel I / O bus, which is stored in the corresponding I / O buffer and synchronized to the external clock signal 3. This day-to-day operation is then performed on the internal clock signal 7 generated by the unknown control circuit 2 in the same manner. In -read operation #, the detected or sensed data is stored in a corresponding input / output buffer, synchronously to the internal clock signal 7, and then transferred out to the data wheeler / output bus. To external clock signal 3. The output transfer from and to the input / output buffer has the ability to execute at the same time. These simultaneous transfers provide maximum operating speed for both reading and scheduling. However, each read and scheduled operation depends on the internal clock signal 7 generated by the clock control circuit 2. Π: Clock control circuit The paper size applies the Chinese national standard teNS) A_4 specification (210 x 297 public love) ^^ υ3ΐι V. Description of the invention (9) As stated in the text of the first figure, the predetermined voltage level must be applied Perform the read operation on the appropriate memory cell. These read voltages are applied to the word and element lines. These words and fields are inherently delayed by the built-in resistance and capacitance of the specified line. Read in _ In the fetch operation, when there is a memory cell transformed from the last-group on one word line to a memory cell of the next group on the lower-word line, that is,-boundary crossing or word line conversion, these delay times increase. Since the operation of reading the electrical house level must be removed from one word line and applied to another-word line, the explicit fetch operation for _ word line conversion usually takes as long as from one memory cell to another in the same word line. S Ji Yi's early reading of the body's' reading option. Shi A > Λ, 取, 贝 1, and 舌 1, the data sensing may take a longer time than one clock cycle of the external clock signal 3. To be data Sensing provides extra time—internal The clock signal 7 is generated by Timing's clock control circuit 2. This internal clock signal 7 synchronizes the external clock signal 'but contains one or more clock cycle segments. According to this internal clock signal 7 is in place Address device, transfer to warp knitting section to the I / O bus is only necessary delay in order to provide more time for material sensing. Must read the supply equipment package -------- Order- -------- (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

# This clock control circuit 2 includes-a recorder combination 100, a clock hit signal generator 23 and-a clock buffer 25. Based on this external clock signal 3 and the input of trigger W5, the clock control circuit 2 generates the internal clock as number 7. This transcriber combination just makes the material clock signal 3 to supply the delayed touch; the number goes to the clock trigger signal generator 23. The external clock signal Ling from the clock, sends: the clock trigger signal generated by Lu No. generator 23 "input, this day ± 1 mile buffer to generate this internal clock signal 7. Τ

This paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 public love) 12 Five Description of the invention (10) 2 Description of the combination of the recorder 丨. . One specific example. This trigger signal 5 is generated by the address sequencer shown in Figure 1. The address sequencer 4 generates a trigger signal 5 at each address increment. This trigger signal% is combined with the input of an inverter PD2. The output of the inverter 102 is coupled to the first shift: one of the cry 104 is lost. The output of the first-mover recorder ， and the first-delay trigger signal are input from one of the first and second porter 106. The output ‘second delay trigger signal Li’ of the second transcriber 结合 is coupled to the input of the third transcriber 108. The third transcriber 108 produces a third delay trigger signal B2 as an output 4-the transcribers 104, 106 and 108 are coupled to the external clock signal 3. Although Figure 3 only shows three transcribers in the transcript combination, the number of transcripts used by Ren is flexible, and the number of 7-segments from the internal clock signal is given regardless of the external clock cycle. It depends. In Fig. 4, one specific example of the writers 104, 106, and 108 in the writer combination of Fig. 3 is shown. The external clock signal 3 is coupled to an input of an inverter 110. The output of the inverter 110 is coupled to the gate of a transistor 112. The drain of the transistor 112 is coupled to the input of the transcript 104, and the source of the transistor 112 is coupled to the input of the inverter 114 and the output of the anti-phase 116. The inverters 114 and 116 include a first tap. This first buckle stores the input of the recorder synchronously to the falling edge of the external clock signal 3. The output of the inverting state 114 and the input of the inverter 116 are coupled to the drain of an electrical transistor 118. The gate of the transistor 118 is coupled to the external clock signal 3. The source of the body 118 is coupled to an input of an inverter 120 and an output of an inverter 122. The inverters 120 and 122 include a second connection. This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 13 530311

The second buckle stores the contents of the first buckle to the rising edge of the external clock signal 3 synchronously. An output of the inverter 120 and an input of the inverter 122 are combined to provide the output of the shifter, and a time delay trigger signal. The clock trigger signal generating circuit 130 receives the delay trigger signal Lo ′ LjuL2 generated by the self-transferr combination 100. The clock trigger signal generating circuit 130 in FIG. 5 includes first, second, and third double-input OR gates 132, 134, and 136 in parallel. The first delay trigger signal lg is coupled to the first dual-input invertor gate 132. This second delay trigger signal is coupled to the first input of the first dual-input anti-OR gate 134, and the third delay trigger signal L2 is coupled to the first input of the third dual-input anti-OR gate 136. The second inputs of the two-input inverter gates 132, 134, and 136 are coupled to the clock segment signals Bl, B2, and B3, respectively. Although the clock segment signals B1, B2, and B3 are typically set before the manufacture of the synchronous flash memory device, this clock segment signal is capable of being set in the operation of the synchronous flash memory device. The clock segment signals B1, B2, and B3 determine the number of segments of the external clock cycle divided by the internal clock signal 7. For example, if the first clock segment signal B1 is set to the low level and the second and third clock segment signals ... and the phantom is set to the high level, an external clock cycle is segmented from the internal clock signal 7. If the first and second brothers are aware of the first time segment, Lu 5 Tigers B1 and B 2 are set to the low level and the second time segment ## B 3 is not set to the two position, the two external clock cycles are from Segmented by internal clock signal 7. Although Fig. 5 shows that three dual-input inverting OR gates are used in the clock trigger signal generating circuit 130, the number of dual-input inverting OR gates used depends on the size of this paper. The Chinese National Standard (CNS) A4 specification (210 X 297) applies. (Mm) (Please read the notes on the back before filling out this page) • n an --II order ----- I-!-Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 14 530311 A7 B7 V. Description of the invention ( 12, The period depends on the number of segments programmed by the internal clock signal 7. The clock trigger signal generating circuit 13 also includes a three-round inversion OR gate 3 8 A dual input inversion OR gate output is combined to the three input inversion OR The input of the OR gate 13 8 and the output of the OR gate 13 8 are the outputs of the clock trigger signal generating circuit and are combined with one of the inputs of a clock buffer 14 in FIG. 2. Each of these double inputs is OR The gates 132, 134, and 136 turn out when both the equivalent clock segment signal and the equivalent delay trigger signal go to a low level. The two inputs are inverted OR gates! This output of 8 is a clock trigger signal. When used to segment one or more externals When the signal is combined with the external clock signal 3 in its clock buffer 140. I Φ In Figure 6, the clock buffer 14 in Figure 2 is shown. At this time, the buffer is input, and the clock in Figure 5 The output of the trigger signal generating circuit is coupled to the input of an inverter 142. The output of the inverter 142 is coupled to the drain of the theta body 143. The source of the transistor 143 is coupled to the inverter 146 Input and output of one of the inverters 148. The inverters 146 and 148 include a buckle. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This external clock signal 3 is coupled to the input of the inverter 144 and a dual input inverter. The first input of the gate 150. The output of the inverter 144 is coupled to the gate of the transistor 143. The output of the inverter 146 and the input of the inverter 148 are coupled to the second input of the dual-input anti-gate 150 The output of the dual-input inverting gate 15 is coupled to one of the inputs of the inverter 152. The input of the inverting source 142 is' This clock trigger signal, how many external clock cycles are programmed when the internal clock signal 7 is generated The output of the inverted state 142 is the internal clock signal. No. 7, one or more external clocks. The paper size of this paper applies to the Chinese National Standard (CNS) A4 specification (210 X 297 public love). 530311 B7 Five Wisdom Wealth Staff Consumption and Invention Statement (13) Period has been edited. No .: It is a certain time chart, which summarizes the second to sixth pictures of =: timing diagram of clock signal 82,-trigger signal is fixed within 2: delay trigger signal 86,-second delay _ 4 ^ 4 5Tiger The timing pattern 90 is shown. Japanese, ::: Those who can see the timing pattern, when this trigger signal 5 goes to a high level T-delay trigger signal L. As the external clock ^ goes to a low level °, when the first delay trigger signal h is low, 1 delay triggers ㈣L4 external clock signal 3 rising edge and goes low. Although both delays are red. The He and Li systems use the 分段 clock segmented signal to make the two adjacent clock systems ’:: Γ: number 7 segment. Therefore, as in —, here :: OR is synchronized to the external clock signal. However, this internal time ′ f t is two lost clock cycles. By removing the clock cycle, the extra ¥ time is provided for reading # or data sensing operation #. n (a) ················································ The internal clock signal 7 provides extra time. The use of the data timing control circuit has been widely recorded since then. Figure 8 illustrates a data timing control circuit b, yield = data sensing signal 63. This data timing control circuit 15 combines the main data circuit 71 and an analogy- Time_Digital (ATD) circuit 9. This ATD Turtle Road 9 is supplied with an a for Lu, at least displaying the "sequencer" of the address signal of the sequencer. The address sequencer generates a pulse, A. Signal, # recall it to the paper size Gu㈣ (eNS) A4

I 530311 V. Description of the invention (14) Each bit address is incremented. This thin circuit 9 has a P-channel transistor 91 and a -N-channel transistor 95. The electrode connected to the p-channel transistor 91 is a reference voltage and the source connected to the P-channel transistor is a resistor. %. Connected to the other end of the resistor 93 is the terminal of the 9-channel transistor 9m, one end of a capacitor 97, and the first input to the "double-input negative OR gate 99". This A. # 号 系 Gate is supplied to the p-type transistor 9ι # σN-type transistor%. These two transistors-function as an inverter to reverse the eight. signal. For example, if the A0 signal is high, the p-type transistor 91 is turned off and the v-type transistor is connected, so a line to the ground line is generated. Therefore, the negative input of OR 99 is connected to the transistor 99, which is pushed to the ground line, that is, the low level. Conversely, if the Α signal is low, the p-type transistor 91 is connected and the transistor just turns off ', thus generating a line from Vcc. Therefore, the first input of the f-OR gate 9 9 connected to the N-type transistor 9 9 is gradually pushed to vce, that is, a high level. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The second input to the anti-OR gate 99 is combined with this A0 signal. At each transition of the signal from low to high, the output of the anti-OR gate 99, this atd signal, is the first input of the anti-OR gate 99 is pushed to the ground line to a low level. On the transition of the AG signal from high to low, the first input of the anti-OR gate 99 is gradually pushed high. In this gradual transition of the first input of the reverse OR gate% from low to high, both inputs to the reverse OR gate 99 are low. Therefore, the output of the inverse OR gate 99 goes from high to low, and therefore a rising edge is generated for this ATD signal. The ATD signal remains high until the first input of the inverse OR gate 99 makes this transition and becomes high. Once the 17th paper size of the anti-OR gate 99 is suitable for financial reasons, 530311, invention description (when the input becomes high, the ATD signal goes low and therefore the falling edge of the ATD signal is generated. Resistance ϋ93 and capacitor 97 Decision—time constant, which determines the time period or pulse width of the ATD signal generated. This atd signal provides input to the data timing control circuit 15. The other input to the #timing control circuit 15 is an extended data The sensing (exsns) signal 70. The EXSNS signal 70 is generated by the extended data circuit 71. The logic state of the exsns k number 70 depends on the input to the extended data circuit 7 丨 and the data sensing is set after an extension The RESETEX signal 73 and the repeatedly set data sensing buffer state are described in Figure 9b to generate this REgETEX No. 75. This set of data sensing buffers and this reset data sensing buffer are exactly the same, except that The input to each buffer is different. This set of two sensing buffers is used as input to supply the internal clock signal and trigger (TRG) signal. Then set the data sensing buffer, another The internal clock signal and the A0 signal are used as inputs. In Figure 9a, the internal clock signal (INtcLK) is connected to the first input of the inverter gate 901 and one of the inverter 903 inputs. This inverter The inverter gw is connected to the gate of the transistor switch 905. When the inTCLK signal goes low, the transistor switch 905 is connected. When the transistor switch 905 is connected, the output of the inverter 907 is connected So far, the drain of transistor switch 905 is transmitted to inverters 909 and 911 through the source of transistor switch 905. The input to inverter 907 is connected to the trigger signal. This inverter 9 〇9 and 911 invert the signal of the source of the self-transistor switch 905 and supply this signal to the first input of the inverse gate 9 01. The inverters 9 0 and 911 also act as a buckle to maintain this. The logic state is at the second input of the anti-gate 901, which is a US paper standard applicable to China National Standard (CNS) A4 (210 X 297 mm)

Please read the note on the back 1 (% '5 Packs · Page II Order # Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 18 530311 A7 B7 V. Description of the invention (16) (Please read the notes on the back before filling in this (Page) This trigger signal. The output of the inverting gate 901 is coupled to one of the inputs of an inverter 913. The output of the inverter 913 is the SETEX signal 73. Therefore, the INTCLK signal is low and the output of the inverting gate 901 is low. The output is high, and the SETEX signal 73 is low. When the INTCLK signal goes high, the transistor switch 905 is turned off, and the first input of the anti-gate 901 is also high. Therefore, when the INTCLK signal goes high At the time, the signal at the second input of the anti-gate 901 is basically a trigger signal that is “timed” to set the logic state of the SETEX signal 73. Therefore, if the INTCLK signal goes to a high level, the trigger signal is When the level is low, the SETEX signal is also low. However, if the trigger signal is high before the INTCLK signal is high, the SETEX signal is high. Therefore, the SETEX signal rises on the INTCLK The edge goes high, and when the trigger signal is high, and the SETEX signal goes low at the falling edge of INTCLK, and when the trigger signal goes low. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs as mentioned above Moreover, the re-set data sensing buffer in FIG. 9b is similar to the set data sensing buffer in FIG. 9a described above, except for the input to the buffer. Therefore, the RESETEX signal 75 is generated in the same way as the SETEX signal. However, this AG signal affects the logic state of the RESETEX signal 75. Therefore, when the INTCLK signal goes high, the AG signal is timed to set the logic state of the RESETEX signal 75. If the AQ signal is low before the INTCLK signal goes to a high level, the RESETEX signal is also a low level. However, if the A0 signal is high before the INTCLK signal goes to a high level, the 19 paper standards apply to Chinese national standards (CNS) A4 specifications (210 X 297 mm) 530311 A7 B7 Five inventions printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives () RESETEX letter Going high. So 'this RESETEX signal goes south at the rising edge of INTCLK, and when the Aq signal is high, and the RESETEX signal goes below the falling edge of INTCLK. And when this A0 signal goes low. In FIG. 8, the RESETEX signal 75 and the SETEX signal 73 are supplied as inputs to the extended data circuit 71. The SETE: X ^ f number 73 is coupled to one of the gate of the first transistor 77 and an input of the inverter 83. The output of the inverter 83 is coupled to the gate of the second transistor 81. When the SETEX signal goes to a high level, the first transistor 77 is connected and the second transistor is turned off due to the interference of the inverter 83. The source of the first transistor 77 is connected to the ground and the non-electrode of the first transistor 77 is connected to the reverse electrodes 85 and 87. This EXSNS signal 70 is the output of the inverter 87. This inverse effect 87 acts as a buckle and maintains the logic state at the first transistor 77A <. Therefore, when the first transistor is connected, one of the lines to the ground is turned on and the EXSNS signal 70 goes to a high level. a Conversely, when the SETEX signal goes low, the first transistor is turned off and the second transistor 81 is connected. The RESETEX signal 73 is coupled to the gate of a third transistor 79. The third transistor 79 has a lacquer system coupled to the ground line, and a drain system coupled to the second transistor si'ijc '. The anode of the second transistor is coupled to the inverters 85 and 87, and η5 is also used as a second source to supply the EXSNS signal 70. With the SETEX hybrid system low, if this RESETEX signal 73 goes to a high level, then one of the multi-push ground lines is developed. Therefore, this EXSNS signal 70 'goes to the ground line and goes low. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 20 530311 A7 --------- B7________ V. Description of the invention (18) This EXSNS signal 70 is supplied to the data timing control circuit 15, and is combined with the ATD signal from the ATD circuit 9 to generate a data sensing signal 63. In Fig. 8, the transistor in the data timing control circuit 15 operates similarly to the transistor of the ATD circuit 9 described earlier. Therefore, the transistors 101a and 101b and the transistors 105a * 105b receive the ATD signal and act inversely 1 §. The resistors 103a and 107a along with the capacitors 103, 107b, and 107c also operate similarly to the resistor 93 and capacitor 97 of the ATD circuit 9, i.e., an RC delay or time constant is generated. However, with the addition of capacitor 10, the delay experienced at the input of reverse OR gate 109b is longer than the delay experienced at the input of reverse OR gate 10%. However, these delays become noticeable only when the EχsNs signal 70 goes high. When EXSNS½ 70 is at the high level, if other inputs other than the OR gate 10 are at the low level, the output of the OR gate 10b will go high. If the input of the negative OR gate 109b is low, the input of this negative OR gate 109a is also at a low level due to the similarity in the components and the interconnection of the components coupled to the negative OR gate 109a. With this, the input of the NOR gate 109a is low, and the output of the NOR gate 10% goes high. The output is inverse OR gates 109a, b, which is also the input of the reverse OR gates lu. The trend is still current, and this SNS signal 63 also goes to a high level. Similarly, when the EXSNS signal 70 goes low, the output outside the OR gate goes low. The input to the NOR gate 109a is also low, and therefore the output of the NOR gate 109a goes to a high level. With the output of the negative OR gate 109a, b, it is also the input of the negative OR gate 111. When it is low, the SNS signal 63 also goes to a low level.

In Figure 10, EXSNS signal, TRG signal, A〇 signal, ATD This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 public love) ----------- install (please Read the Zhuyin on the back? Matters before filling out this page)! | Order! — # Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 21 530311

The timing chart printed by the Ministry of Economic Affairs and the Intellectual Property Office's Consumer Cooperatives as a 仏, SNS signal, and internal and external clock signals illustrates the interaction of these signals and the operation of the data timing control circuit15. Because this internal clock signal provides input to the address sequencer, this signal depends on the state of the INTCLK signal. Therefore, the Aq signal switch, that is, changes state, on the rising edge of each INTCLK signal. The ATD signal from the ATD circuit 9 depends on the state of the A () signal, which is generated at the falling edge of the signal. This ATD signal indicates the transition status from one site to another. The SNS signal 63 functions to control the sense amplifier. Therefore, in periods TS1 and TS2, the sense amplifier is triggered to read a memory cell on the rising edge of the SNS signal. As explained with reference to Fig. 8, the durations of the periods T31 and T% are controlled by the resistor 107a and the capacitors 107b, c. Therefore, if longer time is needed for data sensing, additional capacitance is added to extend the duration of the periods TS1 and TS2. The sense amplifier is triggered to stop reading the memory cell at the falling edge of the SNS signal. We assume a standard read operation, and this sense is amplified to allow two external clock cycles to read the memory cell. In Figure 10, when the TRG signal is high on the rising edge of the external clock signal, the next external clock cycle is skipped. As explained earlier with reference to Figure 7, when the TRG signal is high, a boundary crossing is encountered, and the sense amplifier requires additional time to read this data. Since the INTCLK signal is supplied to the address sequencer to control the increase of this address, the ag signal does not change until the rising edge of the INTClk signal. If the AQ signal does not change, then the ATD signal will not produce the paper size applicable to the Zhongguanjia Standard (CNS) A4 specification (210 X 297 public love ^^ 1— ^ -------- · I- ------ (Please read the notes on the back before filling this page) 22

53〇3U 5. The Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed an invention note (2G: if this ATD signal would not be generated and eight. When the signal does not change, this SNS signal stays high and the sense amplifier continues from now on The memory unit reads the data. Therefore, by delaying this internal clock signal to _ append to the outside: the clock cycle 'this sense of the county' is provided by the amount of ^ ^ implementation read. ', Melon: the decoder circuit as early as the first Formerly explained, the row and column decoder ^ 8 generates the row and column decoded signal based on the address signal generated by the address sequencer 4. A specific example of the decoder circuit of the present invention is described in Figure ^ The isolated high and low voltage sections are used as a row or column of decoder circuits 24 and 26 as illustrated in Figure 丨. This address signal, ... An i is provided as a self-buffer 8 or row The input to buffer 6 is shown in Figure 丨 In Figure 11, a bit selector circuit 162 provides these signals to each of the gate voltage supplier circuits 240a, 240b, 240c, and 240d as required before Invert zero or more bits Signal Aq ... Ani. When this address signal A0 ... Aη · 1 can indicate the selection of a special gate voltage supplier circuit, zero or more address signals A0 ... Aη_! Are inverted to apply logic "High level, at all signal inputs for this special gate voltage provider circuit. For example, when all address signals AG ... are logic low, if gate voltage supplier circuit 240a is to be selected, all signals 164, 166, 168, and 170 have been provided to the gate voltage supplier circuit 24 (which are reversed at the address selector circuit 162, so that all signals 164, 166, 168, and 170 are applied to the gate voltage supplier The input of the circuit 240a is a logical rain when it is applied. ”As another example, if all address signals A0 ... Anq 23, this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 male) (B) 530311 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs — B7 V. Invention Description (21) When the logic is “high”, this gate voltage supplier circuit 2413 is to be selected. Letter of the gate voltage supplier circuit 240d Nos. 188, 190, 190, and 192 are reversed at the address selector circuit 62, so that all signals 188, 190, 190, and 192 are applied to the input of the gate voltage supplier circuit 240d. It is logic "high, 'when applied. Figures 12 A and 12 B are the traditions of using gate voltage selection circuit 200 and gate voltage supplier circuits 24 oa 240 d respectively as the address decoder circuit of the figure 丨 丨Figure 12a shows a gate voltage selection circuit 200, which outputs a voltage output Vppi2 0. The voltage level of the voltage output Vppi2 03 is any Vee or Vpp, and depends on a read signal R and set. The read signal R is generated by the system using the synchronous flash memory device and is provided to the synchronous flash memory device when the read operation is required. The master signal R is coupled to the gate of an empty mode N-channel transistor 2⑽. The drain of the empty-mode N-channel transistor 202 is coupled to, and the source of the empty-mode N-channel transistor 202 is coupled to a voltage output 2 3 Vpp. The read signal R is also coupled to the input of an inverter 2o. The output of the inverter 210 is coupled to the gate of a p-channel transistor 208. The source of the p-channel transistor 208 is coupled to a common electrode 209. The drain of p-channel transistor 204 is coupled to the gate of an enhanced-mode N-channel transistor 204. The drain of the enhanced-mode N-channel transistor 204 is coupled to ν. The drain of the PP P-channel transistor 208 is also coupled to the source and gate of an empty-mode N-channel transistor 206. The gate of the enhanced mode N-channel transistor 204 is coupled to the drain of the p-channel transistor 208. This enhanced-mode N-channel transistor 204 is a high-voltage transistor with a thick oxide layer and low conductivity. Since this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read first Note on the back, please fill out this page)-Install IIII ^^ 1111111 ·

24 V. Description of Invention (22)

Need to handle high gate program voltage V

PP This read signal R goes to two digits in one of the read options. When this read letter is R system, the N channel is switched? Ω ,, 店, # The electric body 202 is connected and the voltage at the source of the transistor 202 becomes close to V. iL _ ^ " Therefore, the voltage output Vppi203 becomes close to V. When the read signal R is high, the output of the inverter 210 becomes low. When the output of the inverting ㈣G goes low, the p-channel transistor is connected to provide a potential close to ground so as to enhance the closed-source of the ❹㈣transistor⑽6. This near-ground potential is also applied to the gate of the empty channel channel transistor class to turn it off, so it is prevented from transmitting. This device will not provide vpp to voltage output.

Vpp203. When the read signal R goes low during the operation of this program, the ^ mode n channel transistor 202 is turned off, so it is prevented from providing v "to the voltage output VPP1203. # When this read signal scale is low, the The output of the phaser 21 is going to a high level, so the p-channel transistor is turned off. The enhanced-mode n-channel transistor 204 is connected, and the program draws ink Vpp to provide the voltage output Vppi203. Both line decoder The circuit 24 and the column decoder circuit 26 include a plurality of gate voltage provider circuits 220 in FIG. 12B, each outputting one, because each gate voltage provider circuit provides the necessary voltage to a specific row control transistor or a memory. A specific column of cells. In the gate voltage provider circuit 220, the signal from the address selector circuit 162 is input into an inverse gate 222 as an input signal. The output of the inverse gate 222 is combined to an N channel. The drain of the transistor 224 and the gate of an N-channel transistor 230. The gate of the n-channel transistor 224 is coupled to ν ". N-frequency paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 25 530311 A7 ----- 2Z ____— V. Description of the invention (23) The source of the Tao transistor 224 is combined to a p The source of the channel transistor 226 and the gate of the p-channel transistor 228. The drains of the P-channel transistors 226 and 228 are coupled to the input terminals 225 and 227, respectively. This Vppi input is provided by a gate voltage selection circuit 22o. The gate of the P-channel transistor 226, the source of the p-channel transistor 228, and the drain of the N-frequency transistor 230 are coupled to an output voltage 231 of a gate voltage provider circuit 220. The source of the N-channel transistor 230 is coupled to a common electrode 229. When a special gate voltage supplier circuit 22 is not selected, at least one of the input signals LG ... Lw to the inverse gate 222 is logic "low." At this time, at least one of the inputs to the gate 222 is logic "". When low,, the output of the anti-gate 222 is logic “high.” When the output of the anti-gate 222 is logic “high,”, the N-channel transistor 230 is connected, pushing the output voltage 231 down to There are 229 ground lines near the ground. When the output of voltage 231 is pushed low, the p-channel transistor 226 is connected to provide a logic “high,” the voltage is at the gate of the p-channel transistor 228, so it is prevented from providing a high voltage to the output 231. Therefore, the gate voltage provider circuit 220 does not provide an output voltage for reading or programming operations when its system is not selected. When a special gate voltage provider circuit 220 is selected, all of this input The signal L0 ... is logic "high", and the output of the inverse gate 222 is logic "low". This low logic is applied to the gate of the transistor 23o to turn it off, so that the output 23 1 is not The logic "low" of the output of the reflexive and gate 222 is applied to the p-channel transistor 228 through the N-channel transistor 224. The N-channel transistor 228 is connected and pushed this output 231 up to V or this paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 male 1) ----------- install (please (Please read the notes on the back before filling this page) IIII ^ 11111111 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employees' Cooperatives 26 530311 A7 B7 V. Description of Invention (24)

Vcc depends on one of the voltage levels of Vppi227. Since the transistors 226, 228, and 230 must handle Vpp, they are high-voltage transistors with an ortho oxide layer and a relatively low conductivity. When Vee is typically lower, the conductivity of the p-channel transistor 228 becomes substantially lower, and this will result in a slow read operation. As a result, those who provide Vee to Vppi203 of this electric crystal 202 must be larger. In Fig. 13, the gate voltage supplier circuit 240 of the present invention is illustrated with a separate high voltage portion and a separate low voltage portion. The low voltage portion of the gate voltage provider circuit implements operations that require fast switching. In the gate voltage providing circuit 240, an inverting gate 242 receives an input signal of the same form as the inverting gate 222 of a conventional circuit when the gate voltage provider circuit is selected. An output 243 of the inverse gate 242 is coupled to a gate of the N-channel transistor 248, an input of the inverter 246, and a drain of an N-channel transistor 252. One output 247 of the inverter 246 is coupled to the drain of the N-channel transistor 250. The gate of the N-channel transistor 250 is coupled to the source of the N-channel transistor 248 and the source of the N-channel transistor 252. The source of the N-channel transistor 250 is coupled to the output voltage 260 of the gate voltage supplier circuit. An output of the inverter 244 is applied to the gate of the transistor 250. The transistors 248 and 250 are low-voltage N-channel transistors with a threshold voltage of 0V. The N-channel transistor 250 is used to isolate the high-voltage part from the low-voltage part. When a special gate voltage provider circuit is not selected, the output 243 of the inverse gate 242 is high, and therefore the output 247 of the inverter 246 is low. This N-channel transistor 248 is connected, and therefore, this N-channel transistor 250 is suitable for the paper size of China National Standard (CNS) A4 (210 x 297 mm) ----------- Shang ( (Please read the notes on the back before filling out this page)

ϋ i ^ i mmat ϋ · 口 'I mmat ϋ immmm It 1B1 I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 27 A7 V. Description of the invention (25: Connected to it) and Immediate Point 249 go high. Therefore, the self-inversion The low output of the converter 246 is output as the output of a special gate voltage supplier circuit. When the low output of the power supply circuit is applied to the gates of the transistors 254 and 256, it operates as an inverter. The p-channel transistor 254 is connected and applied

The gate of the VppiKp frequency chirped transistor 258 and the n-channel transistor are turned off. As a result, the p-channel transistor 258 is turned off, and the system is not provided at the output 260. When a special gate voltage provider circuit is selected, the output 243 of the inverse gate 242 is at a low level, and therefore, the output of the inverter 246 is high. When the read signal R is high, indicating the read operation, the output of the inverter 244 is low, so the N-channel transistor 252 is turned off. This output 260 is pushed up to Vppi. Because the channel capacitance of the N-channel transistor 250 and the node 249 of the gate of the N-channel transistor 250 are combined with a high level, the high conductivity of the N-channel transistor 250 is maintained. Since the inverter 246 is formed with a highly conductive electric crystal, the output 260 is strongly driven, and thus results in a fast operation for reading. In addition, the inverter 246 does not cause this Vppi voltage drop by generating a high output. Therefore, the empty-mode N-channel transistor 202 of the gate voltage selection circuit in Fig. 12a does not need to be compensated by any voltage drop on Vppi. When a special gate voltage provider circuit is selected, and when the read signal R is low, indicating a program operation, the output of the inverter 244 is high, so the N-channel transistor 252 is connected. The N-channel transistor 248 is gradually turned off when the node 249 is pushed low. As above, the reading operation is stinky. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm invention description (26). This output 260 is driven up to vppi. However, this N-channel transistor 248, By means of a shutdown function, a buffer isolates the low-voltage part of the gate voltage provider circuit with the high-voltage part of the self-brake voltage provider circuit. Therefore, the program voltage, that is, 'the high voltage when comparing a read voltage, is provided At output 26 ° without affecting the low-voltage part of the gate voltage provider circuit. IV: Address sequencer This address sequencer sequentially increases the address by one, in synchronization with the rising edge of the internal clock signal. It is the address The generation of signals and jump signals are used. These trigger # numbers are generated inside the address sequencer. Traditionally, jump signals are used to generate N address signals to complete multiple logic gates that are structured together. The use of this traditional logic gate group, as shown in Figure 11, is to impose a series delay for the address signals of each group through a reverse gate and N-1 inverters. Time. These delays The sum presents a significant delay, particularly in terms of increasing the operating clock frequency of the memory device. For example, if the delay of ^ is associated with each logic gate, the total delay is j = Nx ti. This will prevent The clock cycle becomes smaller than J. Therefore, the number of gates in the delay line of the logic gate is reduced, that is, the address signal generator. The address sequencer provides the capability of a memory device to operate to High-frequency clock. Figure 14 is a block diagram of a conventional sequencer 300. A trigger signal generator 301 generates the trigger signal 5, which is provided to the clock control circuit 2 to start the internal clock signal. The suppression of the internal clock cycle is as described with reference to Figures 2 to 7 ^ This is just an example of the trigger signal $ generated, and the generation of the trigger signal 5 is not limited ^ This 530311 Invention Description (27-special case. The clock trigger signal generator 3 () 1 is coupled to the address signal generated internally by the address sequencer 300. The address sequencer 30 includes an address signal generator 304, 308 and 312, it generates address signals of,,, and respectively. For the sake of clarity, the address signal generators for address signals A: ... A " are not shown in the u-th graph. Each address signal is generated The generator is coupled to the internal clock signal 7 and an inverted internal clock signal. The internal clock signal input 7 is inverted by an inverter 302 to generate the inverted internal clock signal. The address signal generators 304, 308, and 312 The system is also coupled to the dual inputs or the outputs of gates 303, 3007, and 311, respectively. The first input of the XOR gate 303 is coupled to the logic "Γ," and the second input of the x〇R gate 303. It is coupled to the output A0 of the address signal generator 304. The first input of the XOR gate 303 is also coupled to the first input of an inverting gate 305. The second input of XOR gate 303 is also coupled to the second input of anti-gate 305. The output of the inverting gate 305 is coupled to the input of an inverter 306. One of the inverters 306 outputs a jump signal (Tgl (0) is coupled to the first input of the x0R gate 307 and the first input of the inverse gate 309. One of the second address generator 308 outputs A0 Combined to the second input of the xor gate 307 and the second input of the inverse gate 309. The output of the inverse gate 309 is coupled to the input of an inverter 310. The output of the inverter 310 is a hop signal (D21 (1)). The first input of the foot gate 3 11 is coupled to a jump signal (Tgl (2)). The second input of the XOR gate 3 11 is coupled to the output Ag of the address signal generator 312. One of the address signal generators 304, 308, or 312, one of the dual-input XOR gates 303, 307, or 311, and one of the gates 305 or 309, and the reverse phase (210 x 297 mm) Please read Note 0 on the back first. ▲ Page IIIIIII Order printed clothes for the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 30 530311 V. Description of the invention (28) Device 3 0 6 or 3 10 of-group The state description in Figure 14 is expressed by the following 'equation ... 1)' A⑷ (T ^ Tg ^ jT]) ㊉ a⑻ (1M) > here a) Tgl⑻〇M) = Tg l (n ι) (τ-1) · An (1M) · and b) Tgl (-l) is called with this logical equation A · B = A + B and the traditional formula "Buer, algebra, the following" The ear, the equation is bursting. Is an even-numbered address, that is, the "Bull's equation system produced by" even number "below 2) A (n) (T)-Tgk-i / Tl) ㊉ A㊉ (T-1); and a) Tgl⑷ (T-1) == Tgl (ni) (T l) · a⑻ (τ ι). It is an odd address, that is, where η is a singular number, and the following Bourr equation is generated: ♦ ^ 3), Α (η) (Τ) = Τ§1 (η_υ (ΐΜ) ㊉ Α⑷ (1Μ); And a) Tgl⑷ (Tl) = Tgl (n)) (Tl) + A (n) (Tl). The "Bull" equations (2) and (3) are given by 5 The logic gates shown in Figure i 5 (aMc) are shown. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. This inverse OR delay is equal to the inverse AND delay. The minimum cycle time is then reduced by the address sequencer. Therefore, this delay is reduced. Example #, if -trans or one-transverse and on-delay is 1, the total delay is j = 20xTan. Traditionally, this delay was a combination of a gate and an inverter. Therefore, this total delay is longer. For example, the total number of days is about 20. Therefore, the improvement of ηχ in cycle time is obtained. If Tai is 0.5ns, then 10ns is reduced. Similarly, in another specific example of the address sequencer, the “Buer,” equation is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love). 31 Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Consumption Cooperative Printed 530311 A7 _________ Β7 ___ 5. Description of the invention (29) " " (1) and (1 a) are controlled by setting m — 1/2. Use m =: 1/2 and use the traditional “buer” Algebraic method, the following "Buer, the equations have been developed: 4) 'Aum / T ^ Tglpm—i / Tl) ㊉ A (2m) (Tl); and 5)' Tgl (2m-1) (Τ- l) Two Tgl (2m_2) (Tl) · A (2m_ " (Tl). By combining equation (5) and equation (4), the following "Buer, equation system: 6), A ^ OO ^ Tgl ^^ Tl) · A ^ JT-l) ㊉A (2m) (Tl). Therefore, using equation (1), the resulting '' buer, equation system: 7) '㊉ A ^ MT-l ) 8) J Tg1 (2m) (Tl) = Tgl (2m.l) (Tl). AUm) (Tl). A (2m.1) (Tl). A (2m) (Tl). This cloth ear etc. Equations (6), (7), and (8) are represented by logic gates illustrated in Figures 16 (a)-(c), with k = n / 2. As in I6 (a) _ (c ) As shown in the figure, the total number of reaction gates is n / 2, and Therefore, the cycle time limit of this address sequencer is reduced by half. Another specific example of the address sequencer is illustrated in Figure 17. The address sequencer in Figure 17 is similar to that illustrated in Figure Π Traditional address sequencer. However, in Figure 17, the clock input to some address sequencers is the address element. From the address buffer is the control transistor of the address of the last row, which indicates a word The transition (start / stop) of the line is used. The inversion of the last row of address elements is also used in the proper position of the clock input to the address sequencer. For example, the bits containing the address signals A0 to A21 Address, the second address buffer state is used. The address buffers for address elements A0 to A5 are used. The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 public love). I- ------ ^ --------- (Please read the notes on the back before filling out this page) 32 530311 A7 ____B7 V. Description of Invention (3 ()) -------- --- install (please read the precautions on the back before filling this page) ## on the front side of the unit. A 5 is assumed to be a word line conversion address. But 'though word line conversion Since the word line address conversion element and the allowable maximum delay time, but any signal can be used here. A5 is used as a clock signal, and this clock input is supplied to the remaining address buffers used to generate addresses A6 to A21. V: Data sensing # Referring back to Figure 1, the sense amplifiers 18 and 22 are connected to individual data lines. These data lines are meta-lines that are combined into individual memory segments. The initial voltage levels of these data lines are usually zero. However, since the capacitance is developed between adjacent data lines, a data line usually has a voltage level higher than the ground level. Therefore, when the predetermined read voltage is applied to the data line and the sense amplifiers 18 and 22 try to sense data from the memory cell, a delay time is experienced. Conventionally, this data line is separated, that is, a larger space is provided between the data lines to remove this delay time. However, by adding a large space between the data lines, the size of the memory module, the physical space occupied by the flash memory device is also increased. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. To remove this delay without increasing the memory phantom size, pull down the transistor system and enter this > material line. In Figure 18, this pull-down transistor 801 is coupled to the data line 803. The gate of the pull-down transistor 801 is coupled to the repeatedly set signal line 805. Before reading a memory cell, the reset signal line 805 is set to a high level for a short period of time. Therefore, pull this transistor down and ground the data line. Starting with all data lines initially at a ground voltage level, the capacitance coupling between the data lines is reduced, and the capacitance on individual data lines is also reduced. Therefore, the paper scale is subject to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 33 530311 A7 V. Description of the invention (Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

The delay is reduced without increasing the memory phantom size. VI: High Voltage Comparator As shown in Figure 1 as a benchmark, a program operation requires a set of predetermined circuits to be applied to the memory unit. The high-voltage comparator circuit 54 of FIG. 1 includes a set of transistors to determine the precise timing at which the predetermined voltage is sufficiently high enough to start regulating the memory cell. Fig. 19 illustrates a specific example of the high-voltage comparator circuit 54 of Fig. 1. The high-voltage comparator circuit in Figure 19 detects the moment when the voltage level, the predetermined program voltage, and the line AA correspond to the voltage level at line 3] 5. The voltage level at line v is assumed to be normally constant and high, and the voltage level at line v is assumed to increase. This line V 叩 is coupled to the gate of a V transistor 181. When the voltage level increases at the line V, the Vpp transistor 181 is connected, and the line BB, which is coupled to the drain of the Vpp transistor 181, is slowly pulled to. Therefore, as the voltage level at the line v increases, the voltage level at the line BB also gradually increases. This line BB is also coupled to the gate of a BB transistor ι83 and the gate of an aa transistor 185. Therefore, as the voltage level at the line BB gradually increases, the BB and AA transistors are gradually connected. The source connected to the AA transistor 185 is a line A A, which is also coupled to a reference transistor ^ 87. The line Vre〆 ^ is coupled to the gate of the reference transistor ι87. Because this reference transistor 1 87 is connected, and because the normal voltage level is applied to the line Vref ', the voltage level at line AA is close to the voltage Vee < When this AA transistor is gradually connected, the ground wire The line is from voltage V ref

PP

PP

PP when ------------ installed (Please read the precautions on the back before filling this page)

ϋ I ϋ 1. 1 · 1 ϋ II I secret 34 530311 A7

530311 A7 B7 V. Description of the Invention (33) The planning of the memory unit is the W of this post. The voltage level on line BB and line AA has already reached its specified operating voltage level immediately. Please VD: Conclusion Accordingly, the present invention provides a clock control circuit that has the ability to generate an internal clock signal by selectively segmenting one or more clock cycles of the external clock signal. At the same time, the present invention provides a decoder circuit with the ability to quickly generate a predetermined voltage for programming and reading operations. Although the application in a synchronous flash memory device based on the -trans configuration has been described, this clock control circuit has a wide range of uses in any semiconductor device that requires a similar internal clock signal. Likewise, this decoder circuit has a wide range of uses in any semiconductor device that requires a similarly increased transmission of a predetermined voltage. In particular, the clock control circuit and the decoder circuit are equally used in a synchronous flash memory device based on a reverse structure. ~ A In addition, although the present invention has been described with a specific specific example, many additional modifications and changes will still be apparent to those skilled in the art. Therefore, we should understand that the present invention can be tested in a manner different from that specifically described. Therefore, this specific example of the present invention should be regarded as illustrative in all points of view without any restriction, and the scope of the present invention should be determined by the added patent application items and their equivalents instead of the foregoing description. The paper size of the paper is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 530311 A7 B7 V. Description of the invention (34) Component label comparison table Printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 ··· Data input / Output bus 36, 38, 40, 42, 44, 46, 48 2 ... clock control circuit 50 ... memory unit 3 ... external clock signal 51 ... memory unit array 4 ... sequencer 54 ... High-voltage comparator circuit 5 ... trigger signal 63 ... data sensing signal 6 ... line buffer 70 ... data sensing signal 7 ... internal clock signal 70 " _EXSNS signal 8 ... column buffer 71 ... data Circuit 9 ... ATD circuit 73 ... data sensing signal 12, 14 ... output / input buffer 73 ... SETEX signal 15 ... data timing control circuit 75-.. RESETEX signal 16 ... write amplifier 77 ... One transistor 18 ... sense amplifier 79 ... third transistor 20 ... write amplifier 81 ... second transistor 22 ... sense amplifier 82 ... external clock signal timing Figure 23 ... clock trigger signal generator 83 ... Inverter 24 ... line decoder 84 Trigger signal timing diagram 25 ... Clock buffer 85, 87 ... Inverter 26 ... Column decoder 86, 88 ... Delay trigger signal 27 ... Clock trigger signal 90 ... Internal clock signal 28, 30 ... Line control circuit Crystal 91 ·· ρ-type transistor 29… line decode signal line 93 ··· resistor • 1. ^ 1 ϋ · I 11 B ^ iI an I i I i ^ in I • TI TI ϋ ϋ II '(Please (Please read the notes on the back before filling this page) This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 37 530311 Α7 Β7 35 5. Description of the invention (---------- -, ·, 1 pack (Please read the precautions on the back before filling this page) Order --------- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 95 ... N-type transistor 97 ... Capacitor 99 · ····· 100 ··· Micographer 101a, b ... Transistor 102 ·· Inverter 103a, 107a ··· Resistor 103b, 107b, 107c ··· Capacitor 104 ··· Recorder 105a, b ... Transistor 106 ... Second transferor 108 ... Third transferor 109b, a ... Inverter 110 ... Inverter 111 ... Invertor 112 ... Crystal 114, 116 ... Inverter 118 ... Transistor 120, 122 ... Inverter 130 ... Clock trigger signal generating circuit 132, 134, 136 ... Inverting OR gate 138 ... Three-input inverting OR gate 140 ... Clock buffer 142 ... Inverter 143 ... Transistor 144 ... Inverter 146, 148 ... Inverter 150 ... Dual input inverting gate 152 ... Inverter 162 ... Address selector circuit 163, 165 ·· ρ-type transistors 164, 166, 168, 170 ·· Signal 169, 167 ... Empty mode transistor 181 ·· Transistor 183 ·· 185 ... Transistor 187 ··· Transistor 185 190, 192 ... Signal 200 ... Gate voltage selection circuit 202 ... N-type transistor 203 ... Voltage output Vppi 204, 206 ... N-type transistor 208 ... P-type transistor 209 ... Common ground 210 ... Inverter 220 ... Gate voltage supplier circuit 222 ... Gate 224 ... N-type transistor 225, 227 ... Input connector 38 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ) 530311 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (36) 226, 228 ··· ρ-type transistor 302… Inverter 229 ·· · A total of ground wires 303, 307, and 31-XOR gate 230 ··· N-type transistor 304, 308, 314 ··· Address signal output 231 ··· Output voltage generator 240 ··· Gate voltage provider circuit 305 ... " Reverse gate 240a, b, c, d ... Gate voltage supply 306 ... Inverter circuit 309 ... Reverse gate 242 ... Reverse gate 310 ... Inverter 243 ... Output electronics 311 ... XOR gate 244 ... Inverter 312 ... Address signal generator 246 ... Inverter 801 ... Pull down transistor 247 ... Output voltage 803 ... Data line 248 ... · N-type transistor 805 ... Reset signal line 249 ·· Node 901 ··· Reverse gate 250 ... N-type transistor 903 ... Inverter 252 ... N-type transistor 905 ... Transistor switch 254, 256 ... Crystal ρ 907 ... Inverter 258 ... Transistor ρ 909, 911 ... Inverter 260 ... Output voltage 913 ... Inverter 300 ... Sequencer ---------- -^ 1 pack (please read the precautions on the back before filling this page) Order --------- The size of the paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) 39

Claims (1)

530311 A8 B8 C8 D8, patent application scope 1 · An address decoder circuit, including: · Idle voltage supplier circuit has a high voltage part and a low voltage part knife, the rain pressure part is generally isolated from the low voltage part, the gate voltage The supplier circuit receives several address signals and a gate voltage; and a voltage selection circuit, the gate voltage selection circuit provides the gate voltage to the gate voltage supplier circuit and uses it as the output of the gate voltage supplier circuit. 2. If the address decoder circuit of item 1 of the patent application scope, wherein the gate voltage supplier circuit provides the gate voltage as an output at the address signal, it means that the condition is used to generate the gate voltage output. 3. If the address decoder circuit of item 2 of the patent application range, wherein the high voltage part of the gate voltage supplier circuit includes several high voltage transistors to provide a guide for the gate voltage from the gate voltage selection circuit to the gate voltage supplier For circuit output. 4. If the address decoder circuit of item 2 of the patent application scope, wherein the low voltage part of the gate voltage supplier circuit includes several low voltage transistors, a conduit is provided for the gate voltage from the gate voltage selection circuit to the gate voltage supplier The output of the circuit is used to bypass the high voltage part of the gate voltage supplier circuit. 5. The address decoder circuit in item 4 of the patent application, where the low-voltage part of the gate voltage supplier circuit includes a second low-voltage transistor coupled to the turn-out and gate voltage supply of the gate voltage supplier circuit High-voltage part of the circuit; low-voltage (please read the note on the back to write this page), you can combine a first low-Qing transistor to a reference electricity and the paper size of the country (⑽) A4 specifications ( 210X297 mm) 40 530311 A8 B8 C8 ____D8 VI. Patent application Fanyuan transistor, & the first low voltage t crystal acts as a switch to connect to this second low voltage transistor; a reverse gate is connected to the address signal; A first inverter receives a read signal; a second inverter is coupled to the inverse gate and the first and second low-voltage transistors; and a third low-voltage transistor is coupled to the first and second An inverter, the inverse AND gate and the second low voltage transistor. 6. If the address decoder circuit of item 3 of the patent application scope, wherein the high voltage part of the gate voltage supplier circuit includes a common ground wire; a first south piezoelectric crystal coupled to the output of the gate voltage supplier circuit, The low voltage portion of the gate voltage supplier circuit and to the common ground; a second voltage transistor coupled to the output of the gate voltage selection circuit 'this first output to the piezoelectric crystal and the gate voltage supplier circuit; and a third voltage The transistor is coupled to the output of the gate voltage selection circuit 'the outputs of the first and second high voltage transistors and the gate voltage supplier circuit. 7 · — A kind of flash memory, including: several memory units; one row of decoder circuit receives the address signal and generates the 4th decoded number of the row decoding 'This row of decoder circuit contains a gate voltage supplier circuit with one The paper size of the high-pressure part and a low-pressure part applies the Chinese National Standard (CNS) A4; | Γΰϊ ^ < 297 mm) ~ (Please read the notes on the back 11 ^ Write this page, ^ Ti 530311 A8 B8 C8 D8 The scope of the patent application is that the voltage-suppressing part is generally isolated from the low-voltage part. The gate voltage supplier circuit receives several address signals and the gate voltage, and a gate voltage selection circuit. The gate voltage selection circuit provides the gate voltage to The gate voltage supplier circuit, 俾-is used as the output of this gate voltage supplier circuit; and a column of decoder circuits that receives the address signal and generates a column decoding signal. Each column of decoded signals is associated with one column of the memory cell, and A control gate coupled to the memory cells in the associated row. The flash memory of item 7 of the patent claim, in which the decoder circuit includes: a gate voltage supplier circuit having a high voltage part and a low voltage part. The south voltage part is substantially isolated from the low voltage part. The voltage supplier circuit receives a plurality of address signals and a gate voltage; and a gate voltage selection circuit, the gate voltage selection circuit provides a gate voltage to the gate voltage supplier circuit, and is used as an output of the gate voltage supplier circuit. 9. The flash memory of item 8 of the patent application scope, further comprising a plurality of write-out amplifiers coupled to each of the plurality of memory cell segments. 10. The flash memory according to item 8 of the patent application scope, further comprising a plurality of sensing amplifiers coupled to each of the plurality of memory cell segments. ; Destination 1 (Please read the notes on the back ^^ Write this page) Μ • Order — 42