TW530278B - Circuit capable of increasing the output voltage range and the controlling method thereof - Google Patents

Abstract

A circuit capable of increasing the output voltage range is disclosed, which comprises a first circuit device, a second circuit device and an output circuit. The power of the first circuit device is supplied by the first voltage source and the second voltage source, and the first circuit device receives an input signal. The output port of the first circuit device is in the first preset state or outputs the first output signal based on a selection signal. The first output signal is corresponding to the input signal, and is located in the first voltage range defined by the first voltage source and the second voltage source. The power of the second circuit device is supplied by the third voltage source and the fourth voltage device, and the second circuit device receives the input signal. The output port of the second circuit device is in the second preset state or outputs the second output signal based on a selection signal. The second output signal is corresponding to the input signal, and is located in the second voltage range defined by the third voltage source and the fourth voltage source. The output circuit is coupled to the first circuit device and the second circuit device. When the output port of the first circuit device is in the first preset state and the second circuit device outputs the second output signal, the output circuit will output the second output signal from an output terminal. When the first circuit device outputs the first output signal and the output port of the second circuit device is in the second preset state, the output circuit will output the first output signal from an output terminal.

Description

530278 V. Description of the invention (1) John Chu is related to the driving circuit technology, especially the circuit and the control method that can increase the output voltage. θ 口!? j, the text is limited to the voltage conversion characteristics of liquid crystals, in order to improve the contrast == good quality, the thin film transistor liquid crystal display (tftlcd) usually uses 8 ~ 12 'operating electric | g Today's half ^ processes are mostly 5v, 3.3v, or even lower, so the voltage range used by thin film transistor liquid crystal displays is "relatively high voltage". In the general CMOS process, the gate oxide layer may have a breakdown phenomenon within 7 ~ ”, so it cannot be used in a voltage environment of 8 ~ 12 ¥. Therefore, a high-voltage process is required to manufacture liquid crystal displays. However, in order to avoid the cost of developing a new process, US Patent Nos. 5, 5 78, 957 and 5, 510; 748, etc., disclose an "Integrated Circuit Having Different Power Supplies for

Increased Output Voltage Range while Retaining Small Device Geometries’1 is a 5V standard process used to implement the driving circuit required for liquid crystal displays. Please refer to Figure 1, which is a block diagram of the column driver circuit disclosed in US Patent Nos. 5,578,957 and 5,510,748. In FIG. 1, reference numeral 40 is a digital wheel-in signal including a plurality of bits, and is used to indicate a required brightness value of a pixel (pixe1) in the liquid crystal display. The digital input signal 40 may include four or more bits depending on the gradation (black and white display) or chromaticity (color display) required by the liquid crystal display. Reference numerals 48 and 52 belong to two circuit blocks. Among them, the circuit block 48 is powered by VDD2 (about + 12V) and VSS2 (about + 6V), including a shifter

Page 5 530278

V. Description of the invention (2) 46. A digital / analog converter (hereinafter referred to as a DAC circuit and a sample and hold circuit (hereinafter referred to as the S / Η circuit) 52 is provided by Vddi (about κν) and VSS1 (about 0V) Power supply, 50, a DAC circuit 68, and an s / ii circuit 70, etc. (abbreviated) 54, and 56. The circuit block contains a shifter. The level shifter 46 receives the digital signal 40, and raises the voltage range to + 6V ~ + 12V; in addition, '°

The shifter 50 receives the digital signal 40, and limits the voltage range of the signal to a voltage range between 0J and + 6V. Then, the digital signals adjusted by the shifters 46 and 50 are adjusted to the DAC circuits 54 and 68, respectively, and the analog signals 62 and 76 corresponding to t are converted. Among them, the analog signal 62 is a voltage range between W + 6V " ~ + 12V, and the analog signal 76 is a voltage range between 0v ~ + 6v. Next, the analog signals 62 and 76 are respectively added to the S / H circuits 56 and 70, and the S / Η circuits 56 and 70 are gated when a new input signal 40 appears in the shifters 46 and 50 ( strObed), which are used to sample and store the analog signals 62 and 76 respectively, and output the signals 63 and 78 to the buffer circuit 64 respectively. As shown in FIG. 1, a certain bit signal 26 is input to the shifters 128 and 132 individually for generating control signals enh and ENL. The shifter 128 is powered by VDD2 and VSS2, and the shifter 132 is powered by Vddi and ^. As described in U.S. Patent Nos. 5,578,957 and 5,510,748, when the bit signal 126 is at a high level, the control signal ENIL is switched to the VSS2 voltage via the shifter 1 2 8 and the control signal ENL is passed through the shifter 1 3 2 Switch to the VSS1 voltage; when the bit signal 1 2 6 is at the low level, the control signal £ n is switched to the VDD2 voltage, and the control signal ENL is switched to the vDD1 voltage.

Page 6 530278

The 64th circuit is based on the control signals ENH and ENL. The detailed circuit of the output buffer circuit 64 is as described in V. Invention Description (3) Therefore, the input buffer circuits k 6 3 and 7 8 are selected. Figure 2 shows. In general, the 'output buffer circuit 64 is like a multiplexer, and is used to select the analog signals 63 = 78 output by the S / H circuits 56 and 70. As shown in Figure 2, the analog signal 63 is at the source terminal of a PMOS transistor 136. The gate of the PMMOS transistor 136 is controlled by the signal ENH, and the drain terminal is connected to another pMOS transistor 14 The source of 〇 is connected to a circuit node A. The gate of the PMOS transistor 1 40 'is used to receive vss2, and the output terminal 6 6 is not coupled to the output terminal.

When the control signal ENH is at a low level (ie, VSS2), the PMOS transistor I 136 is turned on, so the signal 63 is coupled to the circuit node a. Since pM0§ ^ | crystal 140 is also turned on, the signal 63 is coupled from the circuit node a to the output terminal 66 again. Since the signal 63 is changed within the voltage range of VSS2 ~ VDI > 2, as long as the bit signal 1 26 is at a high level, the output signal of the output terminal 66 can be changed within the same voltage range. As shown in FIG. 2, the analog signal 78 and the drain terminal of the 1.0 transistor 142 are controlled. The gate of the NMOS transistor 1 42 is controlled by the signal ENL, and the source terminal is connected to another NMOS transistor. The drain of the crystal 46 is connected to a circuit node β. The NMOS transistor 1 46 has two gates to receive V, and the source is extremely lightly connected to the wheel | terminal 66. When the control signal ENL is at a high level (ie, VDD1), the NMOS transistor 1 4 2 is turned on, so the signal 7 8 I is connected to the circuit node B. Since the crystal 1 46 is also turned on with the q g thunder, the signal 78 is sent from the circuit node R ^ 530278 again.

: ~ Out 66. Since the signal 78 is performed within the voltage range of VSS1 to VDD1, as long as the bit signal 丨 26 is at a low level, the output number of the output terminal 6 6 can be changed within the same voltage range. According to this, when the potential of the output terminal 66 approaches the VSS1 potential due to the conduction of the NMOS transistor 146, the PM0S transistor 136 is turned off, while the pMOS transistor 140 can make the potential at node A not lower than ^, Ensure that the gate-source, or gate-drain voltage drop of pM0s transistor 36 does not exceed 6V, thus protecting the gate oxide layer of the transistor 1 36 from breakdown. Similarly, when the potential of the output terminal 66 approaches the potential due to the conduction of the PM0S transistor, the transistor 142 is turned off, and the transistor 146 of NM0 can make the potential at node 8 not higher than VDD1. Ensure that the gate-drain and gate-to-gate voltage drops of the NMOS transistor 142 do not exceed 6V, thereby protecting the gate oxide layer of the NMOS transistor 142 from collapse. Emulsification / However, the dry-out buffer circuit 64 of US Patent Nos. 5,578,95 7 and 5,5i0,748 need to be controlled according to the control signals ENH and ENL. = Switching control is performed at the analog output. The operating frequency 1 may be degraded again. In order to take into account the analog signal output bandwidth and high voltage operation, the crystal area product must not be too small, so the crystal area product will increase. Therefore, one object of the present invention is to provide a Increase output power

Bu 1 Wang j 7 / W circuit and its control method are based on the DAC circuit for switching control, which is a digital form of control. Therefore, there is no question of operating frequency degradation. The minimum process size is also used. Design '@Reduce the overall demand for crystal cubes. In order to achieve the above object, the present invention provides an increase in output by providing a Jki1

530278 V. Description of the invention (5) Electrical first circuit device in voltage range The circuit device presents a first output and a second voltage source via an output port receiving an input via a second electrical input signal, and a second preliminary Let the status be in the loser to complete. A second voltage, a first voltage according to the source of the device and a signal, and a first preset state or signal according to the selection of a voltage source and a first voltage defined by the output circuit of the driving circuit of the input invention. One power and four voltages are correspondingly determined—the second state, the second output signal, the second output signal, the power supply circuit, and the packet generator, the voltage source, the first, the first, and the first two electrical circuits are installed. When the first selection signal makes the The first state or input signal is within the range of the potential pressure. First to third. The wheel output circuit device Lu Sangji outputs the second input and the output terminal output; when the circuit output of the circuit device is output, the output signal is output from the stomach and the second signal is output from the first and second channels. This includes a first digital analogy and An output circuit. A signal from a two-to-two voltage source ratio converter; a first-stage voltage source and a second voltage-selective signal output a signal, and the source within the voltage range is provided to the two circuit-mounted output signal voltage source and When a signal is output from an output port coupled to the circuit, the first circuit presents the first output source to provide the first first input at the second. The second power supply is set to lose. The second and fourth circuits include ~ circuits. The skirt gives a signal to the power supply and the circuit device. A voltage source circuit device receives a wheel-out port and presents a wheel-out signal. The invention also provides a first number of wheel-out converters for electric wheel-out ports. The first, first, and second analog transfers are provided. The source, according to the present ~ ~ out of the signal, as defined in the Fan Garden ^-

The first circuit device on page 9 presents the first preset output circuit. When the first device outputs the first input two preset state, the electrical digital analog converter in the voltage range passes a first one selection signal to make the preset The state is either at the first voltage source. Second digital analog 530278 V. Description of the invention (6) The converter is provided with electricity through a third voltage source and a fourth voltage source, and according to the selection signal, the wheel of the second digital analog converter is presented ~ Set the state or output a second output signal; wherein the second input 2 and the second input 2 are located in one of the two defined by the third voltage source and the fourth voltage source: two and two. The output circuit is coupled to the first digital analog converter and the 鹆-slave solid-state converter. When the output port of the first digital analog converter presents the first negative state, the second digital analog converter When the second round output signal is output, the pre-condensing circuit outputs the second output signal from an output terminal; when the first digital S output device outputs the first output signal, and the second digital analog converter is itchy, change the first output signal. In the two preset states, the output circuit generates the first output signal. L said that the output wheel is therefore "the present invention is switched at the digital analog converter circuit: a controllable method" so there is no question of operating frequency degradation i :: Designed with the smallest process size, which reduces the overall crystal The obvious change of area i makes ΐ ;;; f and its ..., characteristics, and advantages can be explained in more detail as follows: a preferred embodiment is given, and in conjunction with the accompanying drawings, a simple illustration of the detailed illustration is made : No. 5, 5-8, 957 and 5, 51〇, shown in the series H of Mei Lei in Figure Γ. Figure 2 is a schematic diagram of the first block of the road; Figure 3 is the figure of the wheel A detailed circuit diagram of the buffer circuit 64 is shown; FIG. 乂 According to the block diagram of the first preferred embodiment of the present invention

530278 V. Description of the invention (7) --------- • Figure 4 shows a block diagram according to the second preferred embodiment of the present invention. Figures * ,,, and 3 are shown according to the third aspect of the present invention. A block schematic diagram of the preferred embodiment; and FIG. 1 is a detailed circuit I diagram showing the embroidery circuit of FIG. 3, 4, or 5. Symbol explanation: 3 ~ output buffer circuit; 1 ~ high voltage range circuit block; 12 ~ DAC circuit; 2 ~ low voltage range circuit block; 22 ~ DAC circuit; 31 ~ PM0S transistor; 1 ~ digital Input signal; 6 ~ encoder; 11 ~ shifter; ~ S / Η circuit; 21 ~ shifter; 23 ~ S / Η circuit; 32 ~ NM0S transistor. Embodiment: The display effect is displayed with a better wheel. Generally, a liquid crystal display is driven by using a column driving column drive or a dot inversion driving mode. Therefore, two sets of different voltage targets need to be used to drive the drive operation. Therefore, it is defined as high voltage range and low voltage range. In the embodiments disclosed below, a high voltage range of + 6V to + 12V and a low voltage range of 0V to + 6V are used. However, this is only for convenience of explanation, and is not intended to limit the present invention. For example, a high-voltage dream range of + 5V to + 10V, and a low-voltage range of 0V to + 5V can be similarly applied. Make a statement.

530278 V. Description of the invention (8) First embodiment Please refer to FIG. 3, which shows a preferred embodiment of the present invention and a block diagram. In the figure, reference numeral 1 is a digital input code containing a number of bits, which is used to indicate the brightness of a liquid crystal display. Two = pixels. According to the LCD display: two m one degree (black and white display) or chromaticity (color display), digit wheel °, the second order contains four or more digits. The reference numerals 10 and 20 are Gulei, respectively. _With circuit block and low voltage range circuit block. Its [electrical circumference ν_ (about + 12V) and vssz (about + 6V) provide power, including two bits; Jie Leyou -DAC circuit 12, and an S / H circuit 13 and so on. Circuit block two: Power is provided by 1, VDD1 (about + 6V) and VSS1 (about ov), and includes a shifter ^, a DAC circuit 22, and an S / H circuit 23. One example: "The shifter 11 receives the digital input code 1 and one selection for the poor, two digital input code 1 and the voltage range of the selection signal U / D to a voltage range between + 6V to + 12V, respectively, into signals" And "the output of the self-shifter η is additionally received by the shifter 21 with the digital input code 1 and the selection signal ^ / d, and the voltage range of the digital f input code 1 and the selection signal U / D is limited to a voltage between ^ ~ + 6V Range, into signals 2 4 and 2 5 output from the shifter 2 1.

After 'f', the digital code 14 and the selection signal 15 after passing through the shifter 11 to adjust the voltage range are output to the DAC circuit 12. If the selection signal u /]} is Micro Motion $, the DAC circuit 1 2 will convert the digital code 1 4 to the corresponding analog signal 1 6 and the analog signal 1 6 will be between + 6 V ~ + 1 Voltage range between 2 V. 1. If the selection signal U / D is at a low level, the output port of the dac circuit 1 2 is available. There are two statuses. One state is output disable (⑽disable).

Page 12 530278

^ The output is in a floating state and does not output any voltage value; the other state is to output a predetermined voltage of vSS2. Heart. The digital code 24 and the selection signal 25 'after the voltage range is adjusted by the shifter 21 are output to the DAC circuit 22. If the selection signal U / D is at a low level, the DAC circuit 22 will convert the digital code 24 into a corresponding analog signal 26, and the analog signal 26 will be in a voltage range between 0v ~ + 6V. If U / D = is selected as the high level, the output port of MC circuit 22 can have two states =, the state is output disable, the output port is in a state of ocean movement, and no voltage is rotated.榼; Another state is the predetermined voltage. DD1

The DAC circuits 12 and 22 are coupled to the S / Η circuits 13 and 23 via the analog signal 16 / Vss2 and the analog signal / DD1, respectively. When s / ί circuits 13 and 23 have a new input signal 1 appearing in the shifters 12 and 21, they will be gated 'to block the analog signal 16VVSS2 and the analog signal circuit DD: tm' respectively, and start with The connection lines 17 and 27 are output to the buffer circuit. Circuits 13 and 23 are only selective circuits, so s / i = circuit j t23 can be removed. It can also achieve the object of the present invention. Brothers consistently

Illustration. The block of the preferred embodiment shows the beauty part ^. A figure with the same label represents the same or relative | ^ ^ ^ ~ ^ ^ ^ 6 ^ ^ ^ ^ ^ ϋ Γ ΐ ^ 21. If the # codes are processed with the digital codes 7 and 8 and shifted by 1 ‘^ 5 # uU / D as the high level, the number output by the decoder 6

Page 13 530278 V. Description of the invention (ίο) = 7 Even if the original input digital code i ′ and Digital ma 8 is a digital code corresponding to ^. If the selection signal ㈣ is a low level, decoding = even the original input digital code], and digital code 7 is even a digital code. SS2 Then, the shifter 11 receives the digital code 7 and raises the digital to a voltage range between m and m, then outputs a signal 18. m

Two 18 2j if digital code 8, which limits the range of electric code of digital code 8 to ον ~ + 6V Lei Xiandou ^^ 2 output. However, after the shifter 11 adjusts the digital codes 18 and 28 after the target range, they are output to the DAc circuit 12 and 12 °, respectively. As mentioned above, when the selection signal U / D is at a high level, digital code 7 is the original Enter the digital code 1, * digital code 8 even if it corresponds to ΓΛΤ ^ 22 / " ^ 18 " 28 * The digital input code 1 and the digital code representing Vddi. According to this, the DAC circuit 12 converts the shifted digital input code i to a voltage range between m and + 12V) and outputs. Upper one: Selection ratio Γ is preliminarily ί = c Electricity: 22 Converts the digital code representing Vddi to voltage-like voltage output, or makes the output of DAe electric relay loatable) ° Furthermore, when the selection signal U / D is a low level, the digital code is even for VSS2, and the digital code 8 is the original input digital code-=: 2 two rra8 and 28, even if the V-digit code and t are over-steamed 21 Digital input code i processed. Accordingly, the DAC circuit 22 converts the shifted digital input code 1 into a corresponding analog signal 26 (between

Page 14 530278 V. Description of the invention (11)-m 1 〇V ~ = 6V voltage range) output. In addition, when the selection signal υ / ρ is at a low level | bit, the DAC circuit 1 2 converts the digital code representing VSS2 into an analog vss2 predetermined voltage output, or makes the output of the DAC circuit 1 2 appear to be floating. ° The parts of the S / 和 circuits 13 and 23 and the output buffer circuit 3 are the same as those in the embodiment shown in FIG. 3, and will not be described again. Fig. 5 is a block diagram showing a still another preferred embodiment of the present invention. Among them, those with the same symbol in Figure 3 represent the same or corresponding parts. In this embodiment, the selection signal U / D is directly applied to the DAC circuits 12 and 22. If the selection signal U / D is at a high level, the Behr DAC circuit 12 will convert the digital code 14 into the corresponding analog signal 16, and the output 9 of the DAC circuit 22 will output a predetermined voltage of VDD1 or it will float. status. If the selection signal \ / D is at a low level, the output port of the AC circuit 12 will output a predetermined voltage or it will be in a floating state, and the DAC circuit 22 will convert the digital code 24 into a corresponding analog signal 26. . As for the control method of the selection signal u / D, it can be toggled. ^ According to the above embodiments, the output buffer circuit 3 can be simplified, as will be described in detail below. Please refer to Figure 6 for details of DA (3, 4 or 5) of circuit DA (: Circuit 12 round buffer circuit 3, S / H circuit has been omitted in the figure. In Figure 6, Analog signal π /% and a circuit node c at the source / drain terminal of a pM0s transistor. The ~~ pole of this PM0s transistor is used for 530278. 5. Description of the invention (12) ----- receiving vSS2 voltage And another source / sink terminal is coupled to the output terminal 30. In addition, the analog signal 26 / VDD1 and a source terminal of one NMOS transistor 32 form a node D, and the gate of the NMOS transistor 32 It is used to receive 0 thanks, and the other source / sink terminal is coupled to the output terminal 30. When the selection signal U / D is at a high level, the DAC circuit 12 converts the digital | 14 (Figures 3 and 5) or 18 (Figure 4) is converted into the corresponding analog signal 丨 ^! Out: At this time, the analog signal 16 is higher than the Vsss voltage, so that the PM31 transistor 31 is turned on, and the analog signal 16 is coupled to the PM0S transistor 31 The output terminal 30. Therefore, the voltage at the output terminal 30 is higher than the Vddi voltage. If the DAC circuit 22 outputs a predetermined voltage of vDD1, the 1 of the transistor 32 (equal to the voltage and the voltage of vDD1 is reduced) is Zero, so the NMOS transistor 32 is turned off. If 一, the output port of the DAC circuit 22 is floating, the output port of the DAC circuit 22 will be | at most it will be charged to VDD1-Vtn (the threshold of the NMOS transistor 32 Voltage), and thus turn off the NMOS transistor 32. Therefore, even if the potential of the output terminal 30 approaches the VDD2 potential due to the conduction of the PMOS transistor 31, the node d will not be higher than 7 to ensure that the NM0s voltage The gate-drain or gate-source voltage drop of the crystal does not exceed 6V, thus protecting the gate oxide layer of the NMOS transistor 32 from breakdown and destruction. When the selection signal U / D is at a low level, The DAC circuit 22 will convert the digital code 24 (Figures 3 and 5) or 28 (Figure 4) into the corresponding analog signal 26. At this time, the analog signal 26 is lower than the vDD1 voltage, so NM0s The transistor 32 is turned on, and the analog signal 26 is coupled to the output terminal 30 through the NMOS transistor 32. Therefore, the voltage at the wheel output terminal 30 is lower than the VsS2 voltage. If the DAC circuit 12 outputs a predetermined voltage of VSS2, the PMOS transistor is used. 31 ^ (equal to Vss2 voltage 530278 V. Invention description (13) minus VSS2 voltage) is zero, so PM0S transistor The body 31 is in a closed state. If the output port of the DAC circuit 12 is in a floating state, the wheel output of the DAC circuit 12 is at most discharged to a voltage value of VSS2 + Vtp (the critical voltage of the PM0S transistor 31), and then closed. PM0S transistor 31. Accordingly, even if the potential of the output terminal 30 approaches the VSS1 potential due to the conduction of the NM0S transistor 32, the node C will not fall below VSS2 to ensure the gate-drain or gate-source of the PM0S transistor 31 The inter-voltage drop does not exceed 6V, thus protecting the gate oxide layer of the pMOS transistor 32 from breakdown and destruction. Furthermore, when the DAC circuits 12 and 22 output a predetermined voltage, they are not limited to and VDD1. The predetermined voltage output by the DAC circuit 12 may be in a range between (vss2 + 丨 VTp I) and VSS2, and VTP represents a threshold voltage of the PM0S transistor 31; and the predetermined voltage output by the DAC circuit 22 may be In the range between (VDD1-VTN) and VDD1, Vtn represents the threshold voltage of question 0s and transistor 32. In addition, 'the potential difference between analog signal 16 and VSS2 can be greater than the threshold voltage of an transistor' analogy The potential difference between the signal 26 and the threshold voltage of a transistor can also be greater than the threshold voltage of a transistor. In summary, the circuit that can increase the output voltage range according to the present invention is a switching control at the DAC circuit, which is a digital control method, so there is no The problem of operating frequency degradation can also be designed with the smallest process size, which reduces the overall crystal cube's need for area. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention: any familiarity Those skilled in the art can change and moisturize the stomach without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be

Page 17 530278 V. Description of the invention (14) Subject to the scope of the attached patent application.

Page 18 1

Claims (1)

530278 6. Scope of patent application 1. A first driving circuit includes: a circuit device provided to a power source through a first voltage source and a second voltage source, the first circuit device receiving an input signal and according to a circuit The output port of the device presents a first preset state output signal; the first output signal corresponds to a selection signal defined by the input and the first voltage source and the second voltage source to make the first or output a first An input signal is within the first voltage range; a second circuit device is provided to the power source; the first selection signal causes the second or output a second input to be within the range; the input signal is within the second voltage range; The output circuit is configured; when the second circuit device of the first circuit outputs two output signals from one input to one output signal and the first state, the output circuit 2. If the patent application signal is selected, the first preset signal indicates the first preset The state is set to receive the input signal through a third voltage source and a fourth voltage source and two circuit devices, and present a second preset state according to the output port of the circuit device. The second output signal corresponds to one defined by the third voltage source and the fourth voltage source, and the output port coupled to the first circuit device and the second circuit device presents the first preset. State, the second output signal, the output circuit outputs the first output terminal; when the first circuit device outputs the second circuit device, the output port presents the second preset state, and sends the first output signal from the Output terminal output. The driving circuit described in the first item of the scope, wherein, in the state of the series, the output port of the first circuit device is presented, and the second circuit device outputs the second output signal 3. As described in the second item of the patent application scope Drive circuit where the Page 19 530278 6. Scope of patent application I When the selection signal is in the second logic state, the first circuit device outputs the first output signal, and the output port of the second circuit device assumes the second preset state. 4. The driving circuit according to item 1 of the scope of patent application, wherein the potentials of the second voltage source and the third voltage source are approximately equal. 5. The driving circuit according to item 1 of the scope of patent application, wherein the first preset state is an electrically floating state. 6. The driving circuit according to item 1 of the scope of patent application, wherein the first preset state is outputting a first preset voltage. 7. The driving circuit according to item 6 of the scope of patent application, wherein a potential difference between the first preset voltage and the second voltage source is less than a threshold voltage of a field effect transistor; the first output signal and the first The potential I difference between the two voltage sources is greater than the threshold voltage. 8. The driving circuit as described in item 7 of the scope of patent application, wherein the potential between the first preset voltage and the second voltage source is approximately equal. 9. The driving circuit according to item 1 of the scope of patent application, wherein the second preset state is an electrically floating state. 10. The driving circuit according to item 1 of the scope of patent application, wherein the second preset state is outputting a second preset voltage. 11. The driving circuit according to item 10 of the scope of patent application, wherein a potential difference between the second preset voltage and the third voltage source is less than a threshold voltage of a field effect transistor; the second output signal and the first The potential difference between the three voltage sources is greater than the threshold voltage. 1 2. The driving circuit according to item 11 of the scope of patent application, wherein: 530278 6. Scope of patent application The potential between the first voltage and the third voltage source is approximately equal. 13. The driving circuit as described in item 1 of the scope of patent application, wherein the output circuit includes: a first field effect transistor connected to the first circuit with a source / drain, an output port, and a The gate is connected to the second voltage source, and the source / drain is coupled to the input terminal; and ^ the first field effect transistor is connected to the output port of the second circuit set by a source / tears, A gate is connected to the third voltage source, and another source / drain is coupled to the output terminal. The drive circuit as described in item 13 of the scope of patent application, wherein the% effect transistor is a PMOS transistor, and the second field effect transistor is a NMOS transistor.疋 • The driving circuit as described in item 1 of the scope of patent application, where Φ, including the input signal is a digital input code. ‘口 16 士 The driving circuit described in item 15 of the scope of patent application, where g is integral. The circuit device includes a shifter to electrically power the digital input code. 17 • For the drive circuit described in item 16 of the scope of patent application, φ ▲ is replaced by: = set includes-digital analog converter, the digital The turn-in stone converts i to the first output signal. ~ Xi // As described in the driving circuit described in item 17 of the scope of patent application, | a The digital analog converter is based on the selection signal, so that the number is' 530278 VI. The scope of patent application g19 · The scope of patent application The driving circuit of item 18, wherein the selection signal is coupled to the digital analog converter via the shifter. ^ 20 The driving circuit according to item 18 of the scope of patent application, wherein the selection signal is directly coupled to the digital analog converter. 2 1 · The driving circuit according to item 18 of the scope of patent application, wherein the selection k is coupled to the digital analog converter via a decoder. / 2 · The driving circuit as described in item 15 of the scope of patent application, wherein the " Xuan No. 1 Packet Circuit Device " includes a shifter to perform lightning adjustment on the digital input code. . u 々 2 3 · The driving circuit 5 according to item 22 of the patent application scope, wherein the first circuit device further includes a digital analog converter, and the code is converted into the second output signal. The X number is 24. The driving circuit as described in item 23 of the scope of patent application, where ^ number = analog converter is based on the selection signal, so that the output bee of this type: a first-default state or output one First = 25. The driving circuit described in item 24 of the scope of patent application, ^ Selecting k number is coupled to the digital analog converter via the shifter 26. The driving circuit described in item 24 of scope of patent application, ,sweet". The-& selection signal is directly coupled to the digital analog converter. ， 中 27. The driving electric μ selection signal as described in item 24 of the patent scope of Shenying is coupled to the digital class through a decoder, of which 28 · -type driving circuits include:. Changer. A first digital analog converter, which is supplied by a first voltage source. 6. The patented range voltage source provides electricity%. The change is based on the output of the wheel. The signal is selected to make the first-digital analogy two, / 、 中 ， 此 第 ~ 于 山上 预。 It is evil or outputs a first input signal-the first: within the first to the voltage range; the first voltage source and the second electric voltage source provide electricity: than a converter, via a third voltage source and a first According to the selection signal, the wheel of the four converters presents the first: digital analog number; among them, read the second preset state or output a second output signal as defined by the voltage source ~: wheel out signal Located between the third voltage source and the fourth output circuit within a voltage range; and a bit analog converter; a volume, connected to the% first digital converter and the second first preset state, two When the output port of the first digital analog converter presents the number, the power output = the second digital analog converter outputs the second output signal, the first digital analog 2 and the second output signal are output from an output terminal; when the analog When the converter outputs the first output signal, the second digit rotates the first output, and when the second preset state is displayed, the output circuit 29 outputs, for example, an output from the output terminal. The selection is the driving circuit described in # 28 of the patent scope, where, when the output is in a logical state, the second analog output of the digital analog converter is preset, and the second digital analog converter outputs 30. The driving circuit according to item 28 of the patent scope, wherein, when the letter 2 is in the second logic state, the C-bit converter output = one round-out signal, the second digital analog converter's round-out port, the first preset status. 530278 6. Scope of patent application 31. The driving circuit described in item 28 of the scope of patent application, wherein the potentials of the second voltage source and the third voltage source are approximately equal. 32. The driving circuit according to item 28 of the scope of patent application, wherein the first preset state is an electrically floating state. j 3 3. The driving circuit according to item 28 of the scope of patent application, wherein the first preset state is outputting a first preset voltage. 34. The driving circuit according to item 33 of the scope of patent application, wherein the potential difference between the first preset voltage and the second voltage source is less than a threshold voltage of a field effect transistor; the first output signal and The potential difference between the second voltage sources is greater than the threshold voltage. i 3 5. The driving circuit according to item 34 of the scope of patent application, wherein j, the potential between the first preset voltage and the second voltage source is approximately equal. j 36. The driving circuit according to item 28 of the scope of patent application, wherein g the second preset state is an electrically floating state. 37. The driving circuit according to item 28 of the scope of patent application, wherein the second preset state is outputting a second preset voltage. 38. The driving circuit according to item 37 of the scope of patent application, wherein a potential difference between the second preset voltage and the third voltage source is less than a threshold voltage of a field effect transistor; the second output signal and the The potential difference between the third voltage sources is greater than the threshold voltage. 39. The driving circuit according to item 37 of the scope of patent application, wherein the potential between the second preset voltage and the third voltage source is approximately equal. I 40. The driving circuit as described in item 28 of the scope of patent application, wherein j the output circuit includes: | 530278 Xiangshi: ί: field-effect transistor, connected to the first digit by one source / pole, connected to the first two wheels, connected to the second voltage source by one gate, and coupled by another source / drain Connected to the output terminal; and, the first% efficiency transistor is connected to the output port of the first digital analog converter by a source / drain, connected to the third voltage source by a gate, and connected to the source / drain Connect the output. 4 1 The driving circuit as described in item 40 of the scope of patent application, wherein the first field effect transistor is a PMOS transistor, and the second thunder and -NMOSt crystal. · Electric day and time body 42 · The driving circuit as described in item 28 of the patent application scope, wherein the first digital analog converter converts the first digital code into the first and the first output signals. ·, 43 · The driving circuit described in item 42 of the scope of patent application, further comprising a shifter, which adjusts the potential of a digital input signal to generate the 44th. · The driver described in item 43 of the scope of patent application A circuit, wherein the selection signal is coupled to the first digital analog conversion uo via the shifter. 45. The driving circuit according to item 28 in the scope of patent application, wherein the second digital analog converter converts a second digital code into the second signal. A pinpoint 4 6 · The drive circuit described in item 45 of the scope of patent application, further includes a shifter, which adjusts the potential of a digital input signal and generates 530278 VI. Patent application scope 47. The driving circuit according to item 46 of the patent application scope, wherein the selection signal is coupled to the first digital analog converter via the shifter. 48. The driving circuit as described in claim 28, wherein the selection signal is directly coupled to the first and second digital analog converters. i I 49. The driving circuit as described in item 28 of the scope of patent application, wherein: [The selection signal is coupled to the first and second digital analog converters via a decoder. 50. A driving method applicable to a circuit having a first circuit device, a second circuit device, and an output device; the driving method includes: enabling an output port of the first circuit device according to a selection signal Presenting a first preset state or outputting a first output signal, the first output signal is located within a first voltage range defined by a first voltage source and a second voltage source; The output state of the second circuit device presents a second preset state or outputs a second output signal, the second output signal is located in a second voltage range defined by a third voltage source and a fourth voltage source; And when the output port of the first circuit device presents the first preset state and the second circuit device outputs the second output signal, the output device outputs the second output signal; when the first circuit device outputs the first When the output signal and the output port of the second circuit device show the second preset state, the output device Page 26 530278 6. Scope of Patent Application | Set to output the first output signal. i 5 1. The driving method as described in item 50 of the scope of patent application, wherein when the selection signal is in the first logic state, the input of the first circuit device is made-the port presents the first preset State, so that the second circuit device outputs the second output signal, and the output circuit outputs the second output signal. 52. The driving method according to item 51 of the scope of patent application, wherein when the selection signal is in the second logic state, the first circuit device is caused to input the first output signal, so that the second circuit device The output port assumes the second | preset state, and the output circuit outputs the first output signal. 5 3 · The driving method as described in item 50 of the scope of patent application, wherein the potentials of the second voltage source and the third voltage source are approximately equal. 54. The driving circuit according to item 50 of the scope of patent application, wherein the first preset state is an electrically floating state. 55. The driving circuit according to item 50 of the scope of patent application, wherein the first preset state is outputting a first preset voltage. 56. The driving method according to item 54 of the scope of patent application, wherein a potential difference between the first preset voltage and the second voltage source is less than a threshold voltage of a field effect transistor; the first output signal and The potential difference between the second voltage sources is greater than the threshold voltage. 57. The driving method according to item 55 of the scope of patent application, wherein the potential between the first preset voltage and the second voltage source is approximately equal. 58. The driving circuit according to item 50 of the scope of patent application, wherein the second preset state is an electrically floating state. 5 9. The driving circuit as described in item 50 of the scope of patent application, wherein: Page 27 530278 6. Scope of Patent Application | The second preset state is outputting a second preset voltage. 6 〇. The driving method as described in item 59 of the scope of patent application, wherein j, the potential difference between the second preset voltage and the third voltage source is less than a threshold voltage of a field effect transistor; the second output The potential difference between the signal and the third voltage source is greater than the threshold voltage. 61. The driving method according to item 59 of the scope of patent application, wherein the potential between the second preset voltage and the third voltage source is approximately equal. 62. The driving method as described in claim 50 of the scope of patent application, further comprising: receiving an input signal with the first circuit device and the second circuit device respectively; wherein the first output signal and the second output signal are Corresponds to this