TW529144B - Structure of metal pad and bonding pad region - Google Patents
Structure of metal pad and bonding pad region Download PDFInfo
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- TW529144B TW529144B TW91109595A TW91109595A TW529144B TW 529144 B TW529144 B TW 529144B TW 91109595 A TW91109595 A TW 91109595A TW 91109595 A TW91109595 A TW 91109595A TW 529144 B TW529144 B TW 529144B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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Abstract
Description
529144 五、發明說明(1) 發明領域 本發明係有關於一種半導體積體電路(semic〇nduct〇r intAegrated drcuUs ; ICs)之構造,且特別是有關於一 種此夠防止接a墊(bonding pad)剝離(peeling)與阻礙裂 縫的延伸之接合墊區構造。 相關技術說明: 乂 §,體電路製造完成之後,形成於表面之頂部金屬層 係經界定成複數接合,(b〇nding pad),而分別與形成於 底層金屬墊(metal pad)成電性連接後,經打線機 (bonder)以金屬線連接於接合墊與導架相對應之導腳間。 換言之,接合墊係作為内部電路與外接信號導腳間之介 面,而外接信號不外乎就是電源信號、接地信號、或輸入 /輸出信號等等。 為了進 習知之 金屬墊 其上形 一平整 作為金 如是低 形或矩 半導體 金屬墊 步了解上述之問題,以下配合第1及2圖說明 金屬墊構造。首先,請參照第i圖,其繪示出習知 構造之剖面圖。其中,標號2〇〇為一半導體基底, 成有若干半導體元件,此處為簡化圖式,僅繪示出 基底。一第一圖案介電層202形成於此基底2〇〇上以 屬間介電層(inter-metal dielectric ;IMD),例 介電材料層,且一第一金屬墊單元2 〇1 ,外型為方 形’形成於上述金屬間介電層2〇2内,以作為上述 元件之導線。之後,在第一圖案介電層202及第一 單元201上形成有一第二圖案介電層204,而位於第529144 V. Description of the invention (1) Field of the invention The present invention relates to the structure of a semiconductor integrated circuit (semiconductor int Aegrated drcuUs; ICs), and in particular, to a structure that can prevent bonding pads. Peeling and pad structure that hinders crack propagation. Relevant technical description: 乂 § After the body circuit is manufactured, the top metal layer formed on the surface is defined as a plurality of bonding pads (bonding pads), and are electrically connected to the bottom metal pads. Then, a wire is connected between the bonding pad and the guide leg corresponding to the guide frame through a wire bonder. In other words, the bonding pad serves as an interface between the internal circuit and the external signal guide pins, and the external signal is nothing more than a power signal, a ground signal, or an input / output signal, and so on. In order to learn more about the metal pads, the shape is flat, as gold, if it is a low-shape or rectangular semiconductor metal pad. To understand the above problems, the metal pad structure is described below with reference to Figures 1 and 2. First, please refer to FIG. I, which is a sectional view showing a conventional structure. Among them, reference numeral 200 is a semiconductor substrate formed with a plurality of semiconductor elements. Here, for simplicity, only the substrate is illustrated. A first patterned dielectric layer 202 is formed on the substrate 200 with an inter-metal dielectric (IMD) layer, such as a dielectric material layer, and a first metal pad unit 201 with an external shape. A “square shape” is formed in the inter-metal dielectric layer 200 as the conductive wire of the above-mentioned element. Thereafter, a second patterned dielectric layer 204 is formed on the first patterned dielectric layer 202 and the first unit 201, and is located at the first
529144529144
一金屬墊單凡201上方之介電層2〇4形成有介層洞(via hole)204a ’介層洞2〇4a内有銅金屬插塞(piug)2〇4b,用 以電性連接第一金屬墊單元2〇1。接著,第二圖案介電層 204上形成有一第三圖案介電層2〇6及第二金屬墊單元 2 0 5。此金屬墊單元2〇5外型同樣為方形或矩形,係用以透 過插塞204b及第一金屬墊單元2〇1而與基底2〇〇上的半導體 元件作電性連接並作為連接外部電路之接合墊(b〇nding pad)。最後,在第二金屬墊單元2〇5周邊上方,形成有一 鈍態(passivation)保護層2〇8,以保護接墊2 0 5在後續封 裝(package)製程中不受到損害。上述保護層2〇8具有一開 口 208a而露出上述金屬層2〇5表面以作為後續打線機之金 屬線接合之部分。A metal pad has a via hole 204a formed in the dielectric layer 204 above the 201. The copper hole piug 204b is used in the dielectric hole 204a to electrically connect the A metal pad unit 201. Next, a third patterned dielectric layer 206 and a second metal pad unit 205 are formed on the second patterned dielectric layer 204. The shape of the metal pad unit 200 is also square or rectangular, and is used to electrically connect with the semiconductor element on the substrate 200 through the plug 204b and the first metal pad unit 201 and to connect external circuits. Bonding pad. Finally, a passivation protection layer 208 is formed above the periphery of the second metal pad unit 205 to protect the pad 205 from being damaged in the subsequent package process. The protective layer 208 has an opening 208a, and the surface of the metal layer 205 is exposed as a part of the metal wire bonding of the subsequent wire-bonding machine.
然而’請參照第2圖,其繪示出根據第1圖之第一圖案 介電層202及第一金屬墊單元2〇1之上視圖。如上所述,由 於第一圖案介電層2 0 2機械強度弱並且附著性 (bondability)不佳’因此在化學機械研磨(chem;[cai mechanical p〇l i Shi ng ; CMP)應力的作用下,容易在第一 金屬墊單元201的角落發生應力集中而介電層202產生龜 裂,嚴重影響元件的電特性及產品之品質。再者,經過打 線機施加的機械應力及超音波振盪之雙重作用之後,第一 介電層2 0 2會發生龜裂及剝離的現象,如第2圖所示。更嚴 重者,整個頂部金屬層2 〇 5及金屬層2 0 1會被打線機之金屬 線掀起而脫離(peeling)介電層(未繪示)而形成陷坑 (crater),造成半導體裝置失效。However, please refer to FIG. 2, which illustrates a top view of the first patterned dielectric layer 202 and the first metal pad unit 201 according to FIG. 1. As described above, the first patterned dielectric layer 202 has weak mechanical strength and poor bondability, so under the action of chemical mechanical polishing (chem; [cai mechanical pollination; CMP)] stress, Stress concentration easily occurs at the corners of the first metal pad unit 201 and cracks occur in the dielectric layer 202, which seriously affects the electrical characteristics of the device and the quality of the product. Furthermore, after the dual effects of mechanical stress and ultrasonic oscillation applied by the wire bonder, cracking and peeling of the first dielectric layer 202 may occur, as shown in FIG. 2. More severely, the entire top metal layer 205 and the metal layer 201 will be lifted up by the wire of the wire bonder and peeled away from the dielectric layer (not shown) to form a crater, causing the semiconductor device to fail.
529144 五、發明說明(3) 有鑑於此,為了解決上述問題 提供一種金屬墊與接合墊區之結構 之黏著性,進而防止金屬墊的剝離 且,能夠阻礙接合墊區之裂縫延伸 本發明主要目的在於 不但可以確保金屬墊 陷坑之情形發生,並 發明概述: 本發明之目的之一在於提供一種金屬墊之結構,設置 於一半導體 數凹陷部 黏著性。 基底上,其利用金屬墊具有之複數突出部與複 使得相鄰金屬墊相互牽制,可以增加金屬墊之 為獲致 包括:一圖 少一金屬墊 複數突出部 上述圖 墊單元係以 並且, 及不規則形 本發明 置於一形成 複數突出部 伸0 一第一 第一金属 上述之目的,本發明提出一種金屬墊之結構, 案介電層,形成於上述半導體基底上;以及至 單元,設置於上述圖案介電層内,其側面具有 與複數凹陷部。 案介電層係以低介電材料構成,並且上述金屬 銅金屬構成。 上述突出部係為多邊形,例如:矩形、三角形 狀之其中之一者。 之另一目的在於提供一種接合墊區之結構,設 有電路之半導體基底上,其藉由金屬墊單元之 相互對應、嵌合,可以阻礙接合墊區裂縫的延 圖案介電層,形成於上述半導體基底上;至少 墊單元,設置於上述第一圖案介電層内,與上529144 V. Description of the invention (3) In view of this, in order to solve the above problems, a structural adhesion between the metal pad and the bonding pad area is provided, so as to prevent the metal pad from peeling off and to prevent the cracks in the bonding pad area from extending. The purpose is not only to ensure that the occurrence of pits in the metal pads occurs, but also to summarize the invention: One of the objects of the present invention is to provide a structure of a metal pad, which is disposed on a semiconductor recessed part with adhesiveness. On the substrate, the use of a plurality of protrusions and a plurality of protrusions on a metal pad makes adjacent metal pads mutually restrained, which can be achieved by adding a metal pad, including: a drawing with less one metal pad, a plurality of protrusions, and the above picture pad unit; The present invention is arranged in a regular shape to form a plurality of protruding portions extending to a first first metal. The present invention proposes a structure of a metal pad, a dielectric layer formed on the above-mentioned semiconductor substrate; and a unit disposed on The pattern dielectric layer has a plurality of recessed portions on its side. The dielectric layer is made of a low-dielectric material and is made of the above-mentioned copper metal. The protrusion is a polygon, for example, one of a rectangular shape and a triangular shape. Another object is to provide a structure of a bonding pad region, on a semiconductor substrate provided with a circuit, and a metal pattern unit corresponding to each other and fitted, a patterned dielectric layer capable of blocking cracks in the bonding pad region, formed on the above. On a semiconductor substrate; at least a pad unit is disposed in the first patterned dielectric layer, and
0503-7580TWF(N) ; TSMC2001-1251 ; Felicia.ptd 第7頁 529144 五、發明說明(4) 述基底表面接觸,用 複數第一突出部與複 元,設置於上述第一 觸,用以電 第一金屬墊 數第二凹陷 性連接上 單元相鄰 部,其中 數第一凹陷 第一突出部 與第二金屬 露出上述金 接合的部分 如前所 介電層,形 元,設置於 屬墊單元、 於上述第二 以使上述頂 部金屬墊單 上述第 形、三角形 部 且上 ;以及一 墊單元之 屬第一金 以電性連接上述 數第一凹陷部; 圖案介電層内, 述電路,上述第 ,且其側面具有 上述複數第二突 述複數第二凹陷 保護層,設置於 周邊上方,上述 屬墊單元與第二 電路, 至少一 與上述 二金屬 複數第 出部相 部相對 上述第 保護層 金屬塾 且其側 第二金 基底表 塾單元 二突出 對應於 應於上 一金屬 具有一 一 早兀, 面具有 屬墊單 面接 與上述 部與複 上述複 述複數 墊單元 開口而 以做為 述,上述 成於上述 上述圖案 第二金屬 圖案介電 部金屬墊 元與上述 一突出部 接合墊區之結構 第一介電層上; 電層内, 之上方; 上述頂部 及不規則 部、第一凹陷部相對 上述保護層係以 以低介電材料構成。 合金構成,上述第一 第二介 墊單元 層内之 單元與 第二金 、第二 形狀之 應。 絕緣物 並且, 插塞係 上述第一 屬墊單元 突出部係 其中之一 構成,上 上述頂部 以鎢金屬 更包括:一圖案第二 至少二頂部金屬墊單 分別對應上述第一金 複數第一插塞,設置 金屬墊單元下方,用 金屬墊單元、上述頂 分別構成電性連接。 為多邊形,例如為矩 者,分別與第二凹陷 述第二圖案介電層係 金屬墊單元係以銅鋁 構成。0503-7580TWF (N); TSMC2001-1251; Felicia.ptd Page 7 529144 V. Description of the invention (4) The substrate surface is in contact with a plurality of first protrusions and restorations, which are arranged on the first contact for electricity The first metal pad is connected to the adjacent part of the upper unit with the second recess, and the first protruding part of the first recess and the second metal are exposed to the above-mentioned gold joint as the dielectric layer, the shape element, and are disposed on the pad unit. On the second so that the top metal pad forms the above-mentioned first and third triangular portions; and the first gold of a pad unit is electrically connected to the first plurality of recessed portions; the circuit is in the pattern dielectric layer, The first and the second side has the plurality of second protruding plural second protective protection layers, which are disposed above the periphery, the metal pad unit and the second circuit, at least one of which is opposite to the first metal and the plurality of second metal portions. Layer metal 塾 and its second gold base surface 塾 unit 2 protruded corresponding to the previous metal should have an early stage, the surface has a metal pad single-sided connection with the above part and the above The plurality of pad unit openings are described as described above. The above-mentioned pattern is formed on the first dielectric layer of the structure in which the metal pad of the second metal pattern dielectric portion of the above pattern and the protruding portion is bonded to the pad region; The top portion, the irregular portion, and the first recessed portion are made of a low-dielectric material with respect to the protective layer. It is made of alloy, and the cells in the first and second interlayer units mentioned above correspond to the second and second shapes. The insulator is composed of one of the protrusions of the first metal pad unit, and the top part is made of tungsten metal. The pattern includes at least two top metal pads corresponding to the first gold plural first plugs. The plug is arranged below the metal pad unit, and the metal pad unit and the top are respectively configured to be electrically connected. It is a polygon, such as a moment, and the second patterned dielectric layer system and the second recessed metal pad unit are respectively made of copper and aluminum.
0503-7580TWF(N) ; TSMC2001-1251 ; Felicia.ptd 第8頁 529144 五、發明說明(5) 為使本發明之上述目的、特徵和優點乾 下文特舉一較佳實施例,並配合所附圖式,更切I員易 下: 作詳纟田~ 十菱 貫施例: 弟一實施例 以下利用第3圖、第4圖與第5圖說明根说 ^ 寸嚴太π 貫施例之金屬墊之結構,設置於一形成有電取聲日月第 底上 體基 金屬墊之結構俯視圖。其中,標號1 04係為^ %實施你 首先,請先參照第3圖,其顯示根據本 聲 墊單元,其周邊具有複數第一突出部l〇4a逝Ί第 >、嗖數第 部I 0 4b。標號I 0 6係為複數第二金屬墊單元 複數第二突出部I 06a與第二凹陷部I 〇6b 其周 金屬 L ,邊具古 上述證 有 單元I 04與複數第二金屬墊單元I 06交錯排列,苹〜金屬塾 數第二突出部I 0 6a相對應於上述複數第—凹陷,中上述複 上述複數第二凹陷部I 06b相對應於上述複數^ ,且 I 〇4a。標號I 08表示為一鈍態保護層,其材質 犬出部 矽(S is N4)或氧化矽(S i 〇2),以保護上述第一 1如為氮化 〜中一金屬執留- 1 04與第二金屬墊單元丨06在後續封裝(pack f早% 受到損害。 & ^ I柱中不 接者 吓职不很據第3圖中AA, 接合墊區之剖面圖。圖中顯示一丰莫辦廿—丁 λ綠之 干等®基底1 0 0,卜诸主 導體基底⑽表面可能具有任何所需之半導體元件上:半0503-7580TWF (N); TSMC2001-1251; Felicia.ptd Page 8 529144 V. Description of the invention (5) In order to achieve the above-mentioned objects, features and advantages of the present invention, a preferred embodiment is exemplified below, and is accompanied by the accompanying The drawings are more relevant and easy to understand: For detailed description of Putian ~ Shiling Guan Example: The first embodiment will use Figure 3, Figure 4, and Figure 5 to explain the root cause ^ The structure of the metal pad is arranged on a top view of the structure of the body-based metal pad formed on the bottom of the sun and the moon. Among them, the reference number 104 is ^%. First of all, please refer to FIG. 3 first, which shows that according to this acoustic pad unit, the periphery has a plurality of first protrusions 104a, and the first one. 0 4b. The reference number I 0 6 is a plurality of second metal pad units, a plurality of second protruding portions I 06a and a second recessed portion I 〇6b, and a peripheral metal L thereof, with the above-mentioned proven unit I 04 and the plurality of second metal pad units I 06. In a staggered arrangement, the second protrusion I 0 6a corresponding to the first metal number corresponds to the first plurality of depressions, and the above-mentioned plurality of the second plurality of depressions I 06b corresponds to the above-mentioned plurality ^, and I 〇4a. The reference number I 08 indicates a passive protective layer, the material of which is silicon (S is N4) or silicon oxide (S i 〇2), in order to protect the first 1 as described above, such as nitriding ~ middle one metal retention-1 04 and the second metal pad unit 丨 06 in the subsequent package (pack f% damage early. &Amp; ^ I in the column is not connected with the frightening job is not very bad according to Figure 3 AA, the cross-sectional view of the bonding pad area. The figure shows Yifeng Moban-Ding λ Green Dry, etc. ® Substrate 100, the surface of the main substrate may have any required semiconductor components on it: half
529144 五、發明說明(6) 士二晶體、二極體以及任何習知之半導體元件,此處為 :二化圖示起見,圖中並未繪示。並且,一第一圖案介電 於上述半導體基底100上。上述第-圖案介電層 ^材貝,例如為氧化矽(si〇2)、磷矽玻璃(PSG)、硼磷 矽玻璃(BPSG)或是其他低介電係數材料,如氟矽玻璃 (FSG)。複數第一金屬墊單元1〇4與複數第二金屬墊單元 1〇6,分別交錯鑲嵌於上述第一圖案介電層ι〇2内,並且與 ^述基π底:100表面接觸,用以電性連接上述電路(未圖 示)。最後,一保護層1〇8,設置於上述第一金屬墊單元 104與第一金屬墊單元之周邊上方,並且上述保護層 W8具有一開口 i〇8a,用以露出上述第一金屬墊單元1〇4與 第一金屬墊單元1 0 6表面,以方便藉由打線製程而與外部 電路作電性連接。 本發明之特徵在於第一金屬墊單元1〇4之第一突出部 l〇4a對應於第二金屬墊單元1〇6之第二凹陷部i〇6b,並且 第一金屬墊單元104之第一凹陷部1〇4b對應於第二金屬墊 單元106之第二突出部i〇6a。上述第一突出部i〇4a與第二 突出部1 0 6 a的形狀係為例如為矩形、三角形、任意形狀… 等,根據本實施例之第3圖中係以矩形之突出部為例。另 外’苐4圖係為根據本發明之金屬墊結構,以三角形之突 出部為例。本發明更可應用於其他形狀之金屬墊,並不僅 以此為限。 第二實施例529144 V. Description of the invention (6) For crystals, diodes, and any conventional semiconductor components, here is: for the sake of illustration, it is not shown in the figure. In addition, a first pattern is dielectric on the semiconductor substrate 100. The first-patterned dielectric layer is, for example, silicon oxide (SiO2), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or other low dielectric constant materials, such as fluorosilicone glass (FSG). ). The plurality of first metal pad units 104 and the plurality of second metal pad units 106 are staggered and embedded in the first pattern dielectric layer ι02, respectively, and are in contact with the base surface 100: The circuit (not shown) is electrically connected. Finally, a protective layer 108 is disposed above the periphery of the first metal pad unit 104 and the first metal pad unit, and the protective layer W8 has an opening i08a for exposing the first metal pad unit 1 〇4 and the surface of the first metal pad unit 106, so as to facilitate electrical connection with external circuits through a wire bonding process. The present invention is characterized in that the first protruding portion 104a of the first metal pad unit 104 corresponds to the second recessed portion 106b of the second metal pad unit 106, and the first The recessed portion 104b corresponds to the second protruding portion 106a of the second metal pad unit 106. The shapes of the first protruding portion 104 and the second protruding portion 10 6 a are, for example, rectangular, triangular, arbitrary shapes, etc. The rectangular protruding portion is taken as an example in the third figure of this embodiment. In addition, FIG. 4 is a metal pad structure according to the present invention, and a triangular protrusion is taken as an example. The present invention can be applied to metal pads of other shapes, and is not limited to this. Second embodiment
0503-7580TWF(N) : TSMC2001-1251 ; Felicia.ptd 第10頁 529144 五、發明說明(7) ' --- 接著’以下利用第6圖說明根據本發明第二實施例之 接合墊區之結構。 如同第一實施例中所述之金屬墊結構,包含於根據本 發明·^接合塾區結構中。請參照第6圖,如前所述,其中 上述第一圖案介電層1〇2表面更設置一第二圖案介電層 112 ’形成於上述第一介電層1〇2上。上述第二圖案介電層 112的材質,例如為氧化矽(Si〇2)、磷矽玻璃(pSG)、硼磷 矽玻璃(BPSG)或是其他低介電係數材料,如氟矽玻璃 (FSj)。接著’至少二頂部金屬墊單元114,鑲嵌於上述圖 ,第二介電層1 12内,分別對應上述第一金屬墊單元1〇4、 第一金屬墊單元106之上方。其中,上述頂部金屬墊單元 114的材為例如為金屬銅(Cu)、金屬鋁(μ )或銅鋁(Cu —Al) 合金,並且其形狀為矩形。 …^此外’材質例如為金屬鎢(w)之複數插塞丨丨〇鑲嵌於上 述第二圖案介電層1〇2内之上述頂部金屬墊單元ιΐ4下方, 用以分別使上述頂部金屬墊單元丨丨4與上述第一金屬墊單 兀104、上述頂部金屬墊單元114與上述第二金屬墊單元 1 〇 6構成電性連接。而該實施例之保護層1 〇 8,形成於上述 複數頂部金屬墊單元114之周邊上方,其材質例如為氮化 矽(S I3 & )或氧化矽(s i 〇2),以保護上述第一金屬墊單元 104與第二金屬墊單元1〇6在後續封裝。““以)製程中不 受到損害、。並且,上述保護層1〇8具有—開口i〇8a,用以 露出上述複數頂部金屬墊單元丨14表面,做為後續打線製 程中,與打線機之金屬線接合部分。0503-7580TWF (N): TSMC2001-1251; Felicia.ptd Page 10 529144 V. Description of the invention (7) '---' Next, the structure of the bonding pad area according to the second embodiment of the present invention will be described using FIG. 6 . The metal pad structure as described in the first embodiment is included in the bonding pad structure according to the present invention. Referring to FIG. 6, as described above, a second patterned dielectric layer 112 ′ is further formed on the surface of the first patterned dielectric layer 102 and formed on the first dielectric layer 102. The material of the second patterned dielectric layer 112 is, for example, silicon oxide (SiO2), phosphosilicate glass (pSG), borophosphosilicate glass (BPSG), or other low dielectric constant materials, such as fluorosilicone glass (FSj ). Next, at least two top metal pad units 114 are embedded in the above figure, and the second dielectric layer 112 corresponds to the above first metal pad unit 104 and the first metal pad unit 106, respectively. The material of the top metal pad unit 114 is, for example, metal copper (Cu), metal aluminum (μ), or copper-aluminum (Cu-Al) alloy, and its shape is rectangular. ... ^ In addition, the material is, for example, a plurality of metal tungsten (w) plugs, which are embedded below the top metal pad unit ι4 in the second pattern dielectric layer 102, and are used to separately make the top metal pad unit. The first metal pad unit 104 and the top metal pad unit 114 are electrically connected to the second metal pad unit 106. The protective layer 10 of this embodiment is formed above the periphery of the plurality of top metal pad units 114, and the material is, for example, silicon nitride (S I3 &) or silicon oxide (si 〇2) to protect the first A metal pad unit 104 and a second metal pad unit 106 are subsequently packaged. "" Is not damaged in the process. " In addition, the protective layer 108 has an opening i08a for exposing the surface of the plurality of top metal pad units 14 as a joint portion with a wire of a wire bonding machine in a subsequent wire bonding process.
529144 五、發明說明(8) 發明特徵與功效 本發明之特徵在於以具複數突出部之金屬墊,用以電 性連接半導體電路,取代習知技術中方形或矩形之金屬 層,並且金屬墊之複數突出部與相鄰金屬墊之複數凹陷部 相互對應,使得相鄰金屬墊相互牽制。 根據本發明,利用相互對應之相鄰金屬墊的突出部與 凹陷部,可以有效阻礙接合墊區内外加應力所引發之裂縫 的延伸。再者,可以增加金屬墊之黏著性,避免在進行打 線接合時,打線機施加的機械應力及超音波振盪所造成金 屬墊剝離、陷坑的問題發生。 本發明雖以較佳實施例揭露如上,然其並非用以限定 本發明的範圍,任何熟習此項技藝者,在不脫離本發明之 精神和範圍内,當可做些許的更動與潤飾,因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。529144 V. Description of the invention (8) Features and effects of the invention The present invention is characterized in that a metal pad with a plurality of protrusions is used to electrically connect a semiconductor circuit, instead of the square or rectangular metal layer in the conventional technology, and the metal pad is The plurality of protruding portions and the plurality of recessed portions of the adjacent metal pads correspond to each other, so that the adjacent metal pads are restrained from each other. According to the present invention, the protrusions and depressions of adjacent metal pads corresponding to each other can effectively prevent the extension of cracks caused by the external stress in the bonding pad area. In addition, the adhesiveness of the metal pads can be increased to avoid the problems of peeling and pitting of the metal pads caused by the mechanical stress and ultrasonic oscillations applied by the wire bonder during wire bonding. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the scope of the present invention. Any person skilled in the art can make some modifications and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.
0503-7580TWF(N) ; TSMC2001-1251 ; Felicia.ptd 第 12 頁 529144 圖式簡單說明 第1圖係為根據習知之金屬墊構造之剖面圖。 第2圖係為根據習知之金屬墊構造之俯視圖。 第3圖係為根據本發明之一實施例之金屬墊之結構俯 視圖。 第4圖係為根據本發明之一實施例之金屬墊之結構俯 視圖。 第5圖係為根據第3圖中AA’線之接合墊區之剖面圖。 第6圖係為根據本發明之一實施例之接合墊區之剖面 圖。 符號說明: 100〜半導體基底; 104〜第一金屬墊單元; 104a〜第一突出部; 104b〜第一凹陷部; I 0 8〜保護層; II 0〜插塞; 102〜第一圖案介電層; 106〜第二金屬墊單元; 106a〜第二突出部; 1 0 6 b〜第二凹陷部; I 0 8 a〜保護層開口; II 4〜複數頂部金屬墊單元0503-7580TWF (N); TSMC2001-1251; Felicia.ptd Page 12 529144 Brief description of drawings Figure 1 is a cross-sectional view of a conventional metal pad structure. Fig. 2 is a plan view of a conventional metal pad structure. Fig. 3 is a plan view of the structure of a metal pad according to an embodiment of the present invention. Fig. 4 is a plan view of the structure of a metal pad according to an embodiment of the present invention. Fig. 5 is a sectional view of the bonding pad area according to the AA 'line in Fig. 3. Fig. 6 is a sectional view of a bonding pad region according to an embodiment of the present invention. Explanation of symbols: 100 to semiconductor substrate; 104 to first metal pad unit; 104a to first protruding portion; 104b to first recessed portion; I 0 8 to protective layer; II 0 to plug; 102 to first pattern dielectric Layer; 106 ~ second metal pad unit; 106a ~ second protruding part; 1 0 6b ~ second recessed part; I 0 8a ~ protective layer opening; II 4 ~ plural top metal pad unit
0503-7580TWF(N) ; TSMC2001-1251 ; Felicia.ptd 第13頁0503-7580TWF (N); TSMC2001-1251; Felicia.ptd page 13
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US8187965B2 (en) | 2003-07-23 | 2012-05-29 | Megica Corporation | Wirebond pad for semiconductor chip or wafer |
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